CTNF 18/194,327 CTNF 92202 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA 1 . Claim s 1-5, 9-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sarma (US 2020/0349216) in view of Mellempudi et al (US 2018/0322382, herein Mellempudi) . Regarding claim 1, Sarma teaches an apparatus comprising: an instruction to indicate at least one source floating-point vector, a destination storage location, and at least one value, the source floating-point vector to have a plurality of floating-point data elements, the at least one value to indicate at least one of: (a) a number of significand bits of the floating-point data elements; (b) a number of exponent bits of the floating-point data elements; (c) exponent bias information for the floating-point data elements; or (d) any combination thereof ([0042-0043], input operand source for matrix/vector processing via matrix computation instructions, [0041], floating-point data elements in registers, [0040-0041], memory and registers for storing output results, [0013], [0015], [0036], dynamic configuration of floating-point format to allocate precision between mantissa or exponent, use of configurable bias, “the bias is configurable by specifying a value corresponding to an exponent bias”, “a matrix instruction may specify a new bias that is used to reconfigure the reconfigurable bias”); and execution circuitry to perform operations according to the instruction ([0037], matrix processors), including to: interpret the floating-point data elements consistent with the at least one value; perform an operation specified by the instruction on the at least one source floating-point vector to generate a result floating-point vector ([0048-0052], use of configurable bias to calculate floating-point vector results in matrix processors); and store the result floating-point vector in the destination storage location ([0040-0041], memory and registers for storing output results). Sarma fails to teach the apparatus comprising decoder circuitry to decode the instruction. Mellempudi teaches an apparatus comprising decoder circuitry to decode an instruction to perform a floating-point operation using exponent bias information ([0087], claim 16, decode logic to decode instruction, [0139], [0145], dynamic configuration of exponent bias). It would have been obvious to one of ordinary skill in the art to combine the teachings of Sarma and Mellempudi to utilize standard processor circuitry such as an instruction decoder. While Sarma does not explicitly disclose the details of the matrix processor’s front-end circuitry, one of ordinary skill in the art would understand that an instruction decoder is a routine and conventional component within the microprocessor art. As both Sarma and Mellempudi disclose techniques for dynamically configuring an exponent bias value in floating point operations, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art. Regarding claim 2, the combination of Sarma and Mellempudi teaches the apparatus of claim 1, wherein the at least one value is to indicate at least the exponent bias information (Sarma [0015], [0048], exponent bias configured by instruction value). Regarding claim 3, the combination of Sarma and Mellempudi teaches the apparatus of claim 2, wherein the exponent bias information is either an exponent bias or an exponent bias offset (Sarma [0015], [0048], exponent bias configured by instruction value). Regarding claim 4, the combination of Sarma and Mellempudi teaches the apparatus of claim 2, wherein one of: the floating-point data elements are 16-bit floating-point data elements, having five exponent bits, and ten explicit significand bits, and the exponent bias information is to indicate an exponent bias to be used for the floating-point data elements that is not fifteen; the floating-point data elements are 16-bit floating-point data elements, having eight exponent bits, and seven explicit significand bits, and the exponent bias information is to indicate an exponent bias to be used for the floating-point data elements that is not one hundred twenty seven (Sarma [0052], [0065], 16-bit floating-point with eight exponent and seven mantissa [significand] bits, [0048-0049], reconfiguring exponent bias to different values & Mellempudi [0138-0139], [0141], bias dynamically adjusted as opposed to standard half-precision format using 127 as exponent bias); the floating-point data elements are 8-bit floating-point data elements, having five exponent bits, and two explicit significand bits, and the exponent bias information is to indicate an exponent bias to be used for the floating-point data elements that is not fifteen; and the floating-point data elements are 8-bit floating-point data elements, having four exponent bits, and three explicit significand bits, and the exponent bias information is to indicate an exponent bias to be used for the floating-point data elements that is not seven (Sarma [0016], [0048-0049], [0059-0060], 8-bit floating-point format with four exponent and three mantissa [significand] bits, example configurable bias of various values between 1 and 17). Regarding claim 5, the combination of Sarma and Mellempudi teaches the apparatus of claim 2, wherein the exponent bias information is allowed to indicate any one of several different exponent biases to be used for the floating-point data elements (Sarma [0048-0049], Mellempudi [0138-0141], reconfigurable exponent bias). Regarding claim 9, the combination of Sarma and Mellempudi teaches the apparatus of claim 1, wherein the at least one value includes a first value, a second value, and a third value, and wherein the first, second, and third values are to indicate at least any three of: (a) a number of significand bits of the floating-point data elements; (b) a number of exponent bits of the floating-point data elements; (c) exponent bias information for the floating-point data elements; (d) a number of bits of the floating-point data elements; or (e) any combination thereof ([0013], [0015], [0036], [0048-0052], dynamic configuration of floating-point format to allocate precision between mantissa or exponent, configurable exponent bias value). Regarding claim 10, the combination of Sarma and Mellempudi teaches the apparatus of claim 1, wherein the at least one value is not part of an opcode of the instruction, and wherein the at least one value comprises at least four bits (Sarma [0049], adjustable number of bits for bias value, [0060], 4 bit bias value & Mellempudi [0141], [0146], bias calculated dynamically according to maximum tensor value). Regarding claim 11, the combination of Sarma and Mellempudi teaches the apparatus of claim 1, further comprising a general-purpose register to store the at least one value, and wherein the instruction is to indicate the general-purpose register (Sarma [0051], configurable bias stored in register). Regarding claim 12, the combination of Sarma and Mellempudi teaches the apparatus of claim 1, further comprising a floating-point control register to store the at least one value (Sarma [0051], configurable bias stored in register). Regarding claim 13, the combination of Sarma and Mellempudi teaches the apparatus of claim 1, wherein the at least one value is part of an immediate (Sarma [0051], [0060], 3-bit configurable bias within instruction). Regarding claim 14, the combination of Sarma and Mellempudi teaches the apparatus of claim 1, wherein the instruction is an add instruction, wherein the at least one source floating-point vector includes a first source floating-point vector that is to have the plurality of floating-point data elements and a second source floating-point vector that is to have a plurality of floating-point data elements, and wherein the execution circuitry, to perform the operation specified by the instruction on the at least one source floating-point vector, is to add corresponding floating-point data elements of the first and second source floating-point vectors to generate the result floating-point vector (Sarma [0045-0046], floating-point addition instructions). Regarding claim 15, the combination of Sarma and Mellempudi teaches the apparatus of claim 1, wherein the instruction is a floating-point conversion instruction, wherein the at least one source floating-point vector includes a single source floating-point vector that is to have the plurality of floating-point data elements, and wherein the execution circuitry, to perform the operation specified by the instruction on the at least one source floating-point vector, is to convert the floating-point data elements of the single source floating-point vector to one of double precision, single precision, half precision, bfloat16, FP8 E5M2, or FP8 E4M3 floating-point data elements of the result floating-point vector (Sarma [0057], [0068], [0093], floating-point conversion operations, [0036], single and half precision formats, [0060], 8-bit format with E4M3 & Mellempudi, [0141], format conversion & [0073], double precision and other FP formats). Claims 16 and 17 refer to a method embodiment of the apparatus embodiment of claims 1 and 3, respectively. Therefore, the above rejections for claims 1 and 3 are applicable to claims 16 and 17, respectively. Regarding claim 19, Sarma teaches a system comprising: a processor to receive an instruction to indicate at least one source floating-point vector, a destination storage location, and at least one value, the source floating-point vector to have a plurality of floating-point data elements, the at least one value to indicate at least one of: (a) a number of significand bits of the floating-point data elements; (b) a number of exponent bits of the floating-point data elements; (c) exponent bias information for the floating-point data elements; or (d) any combination thereof ([0042-0043], input operand source for matrix/vector processing via matrix computation instructions, [0041], floating-point data elements in registers, [0040-0041], memory and registers for storing output results, [0013], [0015], [0036], dynamic configuration of floating-point format to allocate precision between mantissa or exponent, use of configurable bias, “the bias is configurable by specifying a value corresponding to an exponent bias”, “a matrix instruction may specify a new bias that is used to reconfigure the reconfigurable bias”); and execution circuitry to perform operations according to the instruction ([0037], matrix processors), including to: interpret the floating-point data elements consistent with the at least one value; perform an operation specified by the instruction on the at least one source floating-point vector to generate a result floating-point vector ([0048-0052], use of configurable bias to calculate floating-point vector results in matrix processors); and store the result floating-point vector in the destination storage location ([0040-0041], memory and registers for storing output results). Sarma fails to teach the system comprising an interconnect or dynamic random access memory (DRAM) coupled with the interconnect. Mellempudi teaches an system comprising an interconnect and dynamic random access memory (DRAM) coupled with the interconnect to perform a floating-point operation using exponent bias information ([0038], interconnect, [0084], DRAM & interconnects, [0139], [0145], dynamic configuration of exponent bias). It would have been obvious to one of ordinary skill in the art to combine the teachings of Sarma and Mellempudi to utilize standard processor circuitry such as an interconnect and DRAM. While Sarma does not explicitly disclose the details of the matrix processor’s auxiliary circuitry or memory, one of ordinary skill in the art would understand that both interconnects and DRAM are routine and conventional component within the microprocessor art. As both Sarma and Mellempudi disclose techniques for dynamically configuring an exponent bias value in floating point operations, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art. Claim 20 refers to a system embodiment of the apparatus embodiment of claim 3. Therefore, the above rejection for claim 3 is applicable to claim 20 . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 2 . Claim s 6-8 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 6 and 18 introduce limitations regarding the specific nature of the bit layout of the instruction “value” which add sufficient detail to the nature of this value to distinguish the claims from the previously cited prior art. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Dellinger (US 12,307,217) discloses a processor with a dynamically adjustable exponent bias. Da Costa (US 2023/0186095) discloses a processor that selects an exponent bias from a variety of different candidate formats. Huang (US 11,387,843) discloses a processor that dynamically adjusts a number of exponent bits and an exponent bias. Nair (US 2019/0042944) discloses a processor with variable precision 16-bit floating point values indicated by floating point instructions. Li (US 2018/0262205) discloses a processor utilizing multiple exponent bias values in a floating point operation. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL J METZGER/ Primary Examiner, Art Unit 2183 Application/Control Number: 18/194,327 Page 2 Art Unit: 2183 Application/Control Number: 18/194,327 Page 3 Art Unit: 2183 Application/Control Number: 18/194,327 Page 4 Art Unit: 2183 Application/Control Number: 18/194,327 Page 5 Art Unit: 2183 Application/Control Number: 18/194,327 Page 6 Art Unit: 2183 Application/Control Number: 18/194,327 Page 7 Art Unit: 2183 Application/Control Number: 18/194,327 Page 8 Art Unit: 2183 Application/Control Number: 18/194,327 Page 9 Art Unit: 2183
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