DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
It should be noted that: claim 20 was not in the latest claim set filed on 01/12/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, and 12-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by PARK et al. (US 2022/0165722 A1).
As to claim 1, PARK et al. disclose a semiconductor device (see Fig. 5), comprising:
a substrate (200) (Fig. 5, para. [0025]-[0027]);
a plurality of stacked circuit dies (“semiconductor chips” 500, 550) located above the substrate (200) (Fig. 5, para. [0039], [0068]);
a carrier (“second base layer” 610) located above one or more dies (“semiconductor chips” 500, 550) of the plurality of stacked circuit dies (Fig. 5, para. [0055]-[0057]); and
a plurality of redistribution layers (a plurality of “circuit patterns” 624, Fig. 5) in the carrier (“second base layer” 610) that provide lateral communication for one or more circuit dies (“semiconductor chips” 500, 550) of the plurality of stacked circuit dies (Fig. 5, para. [0057]-[0059], [0075]).
As to claim 2, as applied to claim 1 above, PARK et al. disclose in Fig. 5 all claimed limitations including the semiconductor device further comprising: at least one bump (“second connection terminals” 430) located above the substrate (200) and below the one or more dies (“semiconductor chips” 500, 550) of the plurality of stacked circuit dies (Fig. 5, para. [0043], [0045]), and wherein the plurality of redistribution layers (a plurality of “circuit patterns” 624, Fig. 5) in the carrier (“second base layer” 610) provides lateral communication between two or more circuit dies (“semiconductor chips” 500, 550) of the plurality of stacked circuit dies (Fig. 5, para. [0057]-[0059], [0075]).
As to claim 3, as applied to claim 1 above, PARK et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein the plurality of redistribution layers (a plurality of “circuit patterns” 624, Fig. 5) in the carrier (“second base layer” 610) provides lateral communication between two or more channels (“vias” 530 & 580) of a circuit die (“semiconductor chip” 500/550) of the plurality of stacked circuit dies (“semiconductor chips” 500, 550) (Fig. 5, para. [0071], [0073], [0089]-[0090]).
As to claim 4, as applied to claim 1 above, PARK et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein the carrier (“second base layer” 610) comprises a passive carrier (“second base layer” 610 may include “silicon (Si)”, para. [0056]) (Fig. 5, para. [0056]).
As to claim 5, as applied to claim 1 above, PARK et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein the carrier (“second base layer” 610) is attached to the plurality of stacked circuit dies (“semiconductor chips” 500, 550) by hybrid bonding (Fig. 5, para. [0058], [0073], [0075], [0078]).
As to claim 6, as applied to claim 1 above, PARK et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein: the plurality of stacked circuit dies (“semiconductor chips” 500, 550) includes layers of circuit dies (“semiconductor chips” 500, 550) all having a same size (see Fig. 5); and the semiconductor device (Fig. 5) has no bridge dies attached between the carrier (“second base layer” 610) and the plurality of stacked circuit dies (“semiconductor chips” 500, 550) (Fig. 5).
As to claim 12, PARK et al. disclose a carrier (Fig. 5) comprising: a first redistribution layer (see a first individual “circuit pattern” 624, Fig. 5) in the carrier (“second base layer” 610) (Fig. 5, para. [0057]-[0059]); and a second redistribution layer (see a second individual “circuit pattern” 624, Fig. 5) in the carrier (“second base layer” 610) (Fig. 5, para. [0057]-[0059]), wherein the first redistribution layer (see a first individual “circuit pattern” 624, Fig. 5) and the second redistribution layer (see a second individual “circuit pattern” 624, Fig. 5) are configured, when positioned above at least one die (“semiconductor chip” 500/550) of upon attachment of the carrier (“second base layer” 610) to a plurality of stacked circuit dies (“semiconductor chips” 500, 550) located above a substrate (200), to provide lateral communication for one or more circuit dies (“semiconductor chips” 500, 550) of the plurality of stacked circuit dies (Fig. 5, para. [0057]-[0059]).
As to claim 13, as applied to claim 12 above, PARK et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein the carrier (“second base layer” 610) comprises a passive carrier (“second base layer” 610 may include “silicon (Si)”, para. [0056]) (Fig. 5, para. [0056]).
As to claim 14, as applied to claim 12 above, PARK et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein the carrier (“second base layer” 610) is attachable to the plurality of stacked circuit dies (“semiconductor chips” 500, 550) by hybrid bonding (Fig. 5, para. [0058], [0073], [0075], [0078]).
As to claim 15, as applied to claim 12 above, PARK et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein the carrier (“second base layer” 610) is directly attachable to the plurality of stacked circuit dies (“semiconductor chips” 500, 550) (Fig. 5).
As to claim 16, as applied to claims 12 and 15 above, PARK et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein the first redistribution layer (see a first individual “circuit pattern” 624, Fig. 5) and the second redistribution layer (see a second individual “circuit pattern” 624, Fig. 5) are configured to provide lateral communication between two or more circuit dies (“semiconductor chips” 500, 550) of the plurality of stacked circuit dies without any bridge dies being attached between the carrier (“second base layer” 610) and the plurality of stacked circuit dies (“semiconductor chips” 500, 550) (Fig. 5).
As to claim 17, as applied to claims 12 and 15 above, PARK et al. disclose in Fig. 5 all claimed limitations including the limitation: wherein the first redistribution layer (see a first individual “circuit pattern” 624, Fig. 5) and the second redistribution layer (see a second individual “circuit pattern” 624, Fig. 5) are configured to provide lateral communication between two or more channels of a circuit die (“semiconductor chip” 500/550) of the plurality of stacked circuit dies (“semiconductor chips” 500, 550) (Fig. 5, para. [0057]-[0059], [0075]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6, and 12-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Tsai et al. (U.S 2023/0154913 A1) disclose the claimed invention (Fig. 32), and Ye et al. (U.S 2007/0045796 A1) disclose the claimed invention (Fig. 3D).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817
April 30, 2026
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