Prosecution Insights
Last updated: October 02, 2026
Application No. 18/194,452

LIGHT EMITTING MODULE WITH INTEGRATED LAMP AND DRIVER AND DISPLAY DEVICE

Final Rejection §102§103
Filed
Mar 31, 2023
Priority
Nov 14, 2022 — CN 202211425359.4
Examiner
DEGRASSE, IAN ISAAC
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
OA Round
4 (Final)
81%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
21 granted / 26 resolved
+12.8% vs TC avg
Minimal +2% lift
Without
With
+1.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
51 currently pending
Career history
78
Total Applications
across all art units

Statute-Specific Performance

§103
58.0%
+18.0% vs TC avg
§102
29.0%
-11.0% vs TC avg
§112
13.0%
-27.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 26 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4, 7, 10-13 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0327995 A1 to Yao et al. (hereinafter “Yao” – previously cited reference). Regarding claim 1, Yao discloses a light emitting module with integrated lamp and driver, comprising: a substrate (display substrate, panel, and device comprising substrate including base substrate 1 and insulating layer 7; Figs. 1-2; paragraphs [0002], [0067]-[0068]); a driving circuit layer disposed on the substrate, wherein the driving circuit layer comprises at least one first electrode disposed on a side close to the substrate (drive circuit layer including a horizontal layer having gate 22 disposed on first side of substrate and including conductive structure 5 and electrode 6 on a side close to substrate 1; Figs. 1-2; paragraph [0083]); a bonding electrode disposed on a side of the substrate away from the driving circuit layer, wherein the bonding electrode penetrates through the substrate and is electrically connected to a corresponding one of the at least one first electrode (bonding electrode 3 disposed on second side of substrate and disposed therethrough and electrically connected to electrode 6 via conductive structure 5; Figs. 1-2; paragraphs [0070]-[0073]); an insulating layer disposed on and in direct contact with an upper surface of the driving circuit layer, wherein the upper surface faces away from the substrate (insulating layer including portion of gate insulating layer 25 and/or interlayer insulating layer 26 disposed in direct contact with upper surface of horizontal layer having gate 22 of drive circuit layer away from substrate 1; Figs. 1-2; paragraph [0083]); a second electrode disposed on a side of the insulating layer away from the substrate and electrically connected to the driving circuit layer (source/drain electrode 23, 24 disposed on insulating layer away from substrate 1 and electrically connected to drive circuit layer; Figs. 1-2; paragraph [0083]); a third electrode disposed on a side of the second electrode away from the substrate and electrically connected to the second electrode (anode pixel electrode 8 disposed on side of source/drain 23, 24 away from substrate and electrically connected source/drain 23, 24; Figs. 1-2; paragraph [0083]); a light emitting layer electrically connected to and in direct contact with a surface of the third electrode facing away from the substrate (electroluminescent device or micro LED connected to and in direct contact with a surface of anode pixel electrode 8 that does not face substrate 1; Fig. 1; paragraph [0083]), wherein the third electrode electrically connects the light emitting layer to the second electrode (anode pixel electrode 8 electrically connects the electroluminescent device or micro LED to the source/drain 23, 24; Figs. 1-2; paragraph [0083]); and a plurality of driving chips arranged in the driving circuit layer, wherein the driving chips are configured to drive the light emitting layer (drive circuits 2 disposed within drive circuit layer and capable of driving electroluminescent device or micro LED; Fig. 1; paragraphs [0077], [0082]-[0083]). Regarding claim 2, Yao discloses the light emitting module with integrated lamp and driver according to claim 1, wherein at least one of the plurality of driving chips comprises at least one of a light emitting layer driving circuit, a data latch circuit, a data shaping circuit, a data forwarding circuit, and a pulse width modulation circuit (drive circuits 2 for driving electroluminescent device or micro LED; Fig. 1; paragraphs [0077], [0082]-[0083]). Regarding claim 3, Yao discloses the light emitting module with integrated lamp and driver according to claim 2, wherein a signal transmitted by the bonding electrode comprises at least one of a power signal, a data input signal, a data output signal, and a ground signal (bonding electrode 3 comprising signal line 4 may transmit data and scan signals; Fig. 1; paragraphs [0074], [0078]). Regarding claim 4, Yao discloses the light emitting module with integrated lamp and driver according to claim 3, further comprising: a first encapsulation layer surrounding the light emitting layer and extending over the insulating layer, the driving circuit layer, and the substrate (bottom half of planarization layer 10 surrounding electroluminescent device or micro LED and over insulating layer, drive circuit layer, and substrate; Figs. 1-2; paragraph [0083]); and a second encapsulation layer covering a side of the light emitting layer away from the substrate and extending to cover the first encapsulation layer (top half of planarization layer 10 disposed over bottom half of planarization layer 10; Fig. 1). Regarding claim 7, Yao discloses the light emitting module with integrated lamp and driver according to claim 1, further comprising: a bonding area and a bond area (bond and bonding area of substrate; Fig. 1; paragraph [0101]); wherein the at least one first electrode is located in the bonding area; wherein the light emitting layer is located within the bond area (electrodes and electroluminescent device or micro LED located within bond and bonding area of substrate; Fig. 1); wherein a projection of the bond area on the driving circuit layer is outside a projection of the bonding area on the driving circuit layer; or wherein the projection of the bond area on the driving circuit layer coincides with the projection of the bonding area on the driving circuit layer (bond area of drive circuit layer same as bonding area of drive circuit layer; Fig. 1). Regarding claim 10, Yao discloses a display device, comprising: a circuit board and a light emitting module with integrated lamp and driver, wherein the light emitting module with integrated lamp and driver comprises: a substrate (OLED display substrate, panel, and device comprising substrate including base substrate 1 and layer 7 and drive circuit 2 with integrated circuit; Fig. 1; paragraphs [0002], [0065], [0067]-[0068], [0078]); a driving circuit layer disposed on the substrate, wherein the driving circuit layer comprises at least one first electrode disposed on a side close to the substrate (drive circuit layer including a horizontal layer having gate 22 disposed on first side of substrate and including conductive structure 5 and electrode 6 on a side close to substrate 1; Figs. 1-2; paragraph [0083]); a bonding electrode disposed on a side of the substrate away from the driving circuit layer, wherein the bonding electrode penetrates through the substrate and is electrically connected to a corresponding one of the at least one first electrode (bonding electrode 3 disposed on second side of substrate and disposed therethrough and electrically connected to electrode 6 via conductive structure 5; Figs. 1-2; paragraphs [0070]-[0073]); an insulating layer disposed on and in direct contact with an upper surface of the driving circuit layer, wherein the upper surface faces away from the substrate (insulating layer including portion of gate insulating layer 25 and/or interlayer insulating layer 26 disposed in direct contact with upper surface of horizontal layer having gate 22 of drive circuit layer away from substrate 1; Figs. 1-2; paragraph [0083]); a second electrode disposed on a side of the insulating layer away from the substrate and electrically connected to the driving circuit layer (source/drain electrode 23, 24 disposed on insulating layer away from substrate 1 and electrically connected to drive circuit layer; Figs. 1-2; paragraph [0083]); a third electrode disposed on a side of the second electrode away from the substrate and electrically connected to the second electrode (anode pixel electrode 8 disposed on side of source/drain 23, 24 away from substrate and electrically connected source/drain 23, 24; Figs. 1-2; paragraph [0083]); a light emitting layer electrically connected to and in direct contact with a surface of the third electrode facing away from the substrate (electroluminescent device or micro LED connected to and in direct contact with a surface of anode pixel electrode 8 that does not face substrate 1; Fig. 1; paragraph [0083]), wherein the third electrode electrically connects the light emitting layer to the second electrode (anode pixel electrode 8 electrically connects the electroluminescent device or micro LED to the source/drain 23, 24; Figs. 1-2; paragraph [0083]); and a plurality of driving chips arranged in the driving circuit layer, wherein the driving chips are configured to drive the light emitting layer (drive circuits 2 disposed within drive circuit layer and capable of driving electroluminescent device or micro LED; Fig. 1; paragraphs [0077], [0082]-[0083]); wherein the light emitting module with integrated lamp and driver is electrically connected to the circuit board through the bonding electrode (OLED electrically connected to drive circuit 2 with integrated circuit through externally-disposed bonding electrode 3; Figs. 1-2; paragraphs [0002], [0065], [0067]-[0068], [0078], [0083]). Regarding claim 11, Yao discloses the display device according to claim 10, wherein at least one of the plurality of driving chips comprises at least one of a light emitting layer driving circuit, a data latch circuit, a data shaping circuit, a data forwarding circuit, and a pulse width modulation circuit (drive circuits 2 for driving electroluminescent device or micro LED; Fig. 1; paragraphs [0077], [0082]-[0083]). Regarding claim 12, Yao discloses the display device according to claim 11, wherein a signal transmitted by the bonding electrode comprises at least one of a power signal, a data input signal, a data output signal, and a ground signal (bonding electrode 3 comprising signal line 4 may transmit data and scan signals; Fig. 1; paragraphs [0074], [0078]). Regarding claim 13, Yao discloses the display device according to claim 12, further comprising: a first encapsulation layer surrounding the light emitting layer and extending over the insulating layer, the driving circuit layer, and the substrate (bottom half of planarization layer 10 surrounding electroluminescent device or micro LED and over insulating layer, drive circuit layer, and substrate; Figs. 1-2; paragraph [0083]); and a second encapsulation layer covering a side of the light emitting layer away from the substrate and extending to cover the first encapsulation layer (top half of planarization layer 10 disposed over bottom half of planarization layer 10; Fig. 1). Regarding claim 16, Yao discloses the display device according to claim 10, further comprising: a bonding area and a bond area (bond and bonding area of substrate; Fig. 1; paragraph [0101]); wherein the at least one first electrode is located in the bonding area; wherein the light emitting layer is located within the bond area (electrodes and electroluminescent device or micro LED located within bond and bonding area of substrate; Fig. 1); wherein a projection of the bond area on the driving circuit layer is outside a projection of the bonding area on the driving circuit layer; or wherein the projection of the bond area on the driving circuit layer coincides with the projection of the bonding area on the driving circuit layer (bond area of drive circuit layer same as bonding area of drive circuit layer; Fig. 1). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yao in further view of US 2022/0169864 A1 to Sun et al. (hereinafter “Sun” – previously cited reference). Regarding claims 5 and 14, Yao discloses the light emitting module with integrated lamp and driver and display device according to claims 4 and 13. Yao further discloses wherein a surface of the first encapsulation layer disposed on a side away from the substrate is flush with a surface of the light emitting layer disposed on a side away from the substrate (bottom half of planarization layer 10 flush with active layer 21 of electroluminescent device or micro LED; Fig. 1). Yao fails to disclose wherein a refractive index of the first encapsulation layer is less than 5%, and a material of the first encapsulation layer comprises one or more of a black epoxy resin, a black silica gel, and a black photoresist. However, Sun discloses wherein a refractive index of the first encapsulation layer is less than 5%, and a material of the first encapsulation layer comprises one or more of a black epoxy resin, a black silica gel, and a black photoresist (layered structure having black particles disposed within epoxy resin having reflectance of 15% or less; paragraphs [0026], [0065], [0114]-[0123]). Yao and Sun are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Yao to incorporate the teaching of Sun in order to potentially provide improved contrast, reduced ambient light reflection, and suppression of internal reflections. Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yao in further view of US 2017/0365756 A1 to Tsutsumi et al. (hereinafter “Tsutsumi” – previously cited reference). Regarding claims 6 and 15, Yao discloses the light emitting module with integrated lamp and driver and display device according to claims 4 and 13. Yao fails to disclose wherein a refractive index of the first encapsulation layer is greater than 90%, and a material of the first encapsulation layer comprises a white ink. However, Tu discloses wherein a refractive index of the first encapsulation layer is greater than 90%, and a material of the first encapsulation layer comprises a white ink (epoxy resin encapsulation layer having white pigment with a reflectance of 80% or more and above 90% in some cases; abstract; paragraphs [0008], [0028], [0113]-[0114]). Yao and Tsutsumi are both considered to be analogous to the claimed invention because they are in the same field of optical semiconductor elements. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Yao to incorporate the teaching of Tsutsumi in order to potentially provide enhanced light outcoupling efficiency, uniform light distribution, and improved color balance. Claims 8-9 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yao in further view of US 2022/0310877 A1 to Chen (hereinafter “Chen” – previously cited reference). Regarding claim 8, Yao discloses the light emitting module with integrated lamp and driver and display device according to claim 1, wherein the plurality of driving chips are independently arranged in the driving circuit layer and are in one-to-one correspondence with the plurality of light emitting units so that the plurality of driving chips are each configured to drive a corresponding one of the plurality of light emitting units independently (drive circuits 2 arranged within drive circuit layer, where each drive circuit 2 corresponds to a micro LED bound to pixel electrode 8 such that each circuit 2 is capable of driving a corresponding micro LED of the display panel; Fig. 1; paragraphs [0083], [0122]). Yao fails to disclose wherein the light emitting layer comprises a plurality of light emitting units, each of which comprises at least two light emitting chips with different colors. However, Chen discloses wherein the light emitting layer comprises a plurality of light emitting units comprising at least two light emitting chips with different colors (light emitting layer having light emitting units each comprising a micro LED chip 11 with red and green quantum dot patterns 13, 14; Fig. 9; paragraph [0047]). Yao and Chen are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Yao to incorporate the teaching of Chen in order to potentially provide full-color display capability, tunable color output, improved color gamut, and enhanced efficiency and brightness. Yao in view of Chen fails to disclose each light emitting unit comprising at least two light emitting chips. However, Chen already discloses each light emitting unit comprising a single light emitting chip and so it would be obvious to duplicate parts already disclosed by Chen for the same motivation provided above. Regarding claims 9 and 18, Yao in view of Chen discloses the light emitting module with integrated lamp and driver and display device according to claims 8 and 17. Yao fails to disclose wherein the light emitting chip comprises one or more of submillimeter light emitting diodes and micron light emitting diodes. However, Chen discloses wherein the light emitting chip comprises one or more of submillimeter light emitting diodes and micron light emitting diodes (micro LED chips 11; Fig. 9; paragraph [0047]). Yao and Chen are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Yao to incorporate the teaching of Chen in order to potentially provide superior brightness and efficiency, improved color performance, wider color gamut, and high contrast and truer blacks. Regarding claim 17, Yao discloses the light emitting module with integrated lamp and driver and display device according to claim 10. Yao fails to disclose wherein the light emitting layer comprises at least one light emitting unit, and each light emitting unit comprises at least two light emitting chips with different colors. However, Chen discloses wherein the light emitting layer comprises at least one light emitting unit, and each light emitting unit comprises at least two light emitting chips with different colors (light emitting layer having a light emitting unit comprising micro LED chips 11 with red and green quantum dot patterns 13, 14; Fig. 9; paragraph [0047]). Yao and Chen are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Yao to incorporate the teaching of Chen in order to potentially provide full-color display capability, tunable color output, improved color gamut, and enhanced efficiency and brightness. Response to Arguments Applicant's arguments filed June 10, 2026 have been fully considered. Applicant presents amendments to claims 1 and 10 and corresponding arguments. Specifically, Applicant reasserts the same claim that the drive circuit 2 being disposed in the driving circuit layer means that driving circuit layer must be equal in size or larger than the drive circuit 2. However, Applicant does not consider that the drive circuit 2 may be at least partially within the drive circuit layer and still satisfy the limitation of being within the drive circuit layer. Therefore, it is not true that driving circuit layer must be equal in size or larger than the drive circuit 2, but only that it may be. Further, ‘drive circuit layer’ is a broad phrase given that ‘layer’ may be construed broadly within the context of driving the device. Additionally, Applicant relies upon the dotted line box labeled with the numeral 2 in Figs. 1 and 2 of Yao as narrowly defining the driving circuit layer. However, it is clear that this box is drawn in a relatively arbitrary manner in such a way as to generally point out the area in which the drive circuit 2 structure and functionality is located. Further, Applicant references the exemplary instance dealing with vertical and horizontal dimensions that Examiner previously recited to show that Applicant’s construction of ‘in the driving circuit layer’ is far too narrow. Then Applicant states that, per Fig. 2 of Yao, the upper surface of the circuit 2 is the upper surface of the electrode 23, but this is clearly not shown in Figs. 1 or 2, unless Applicant agrees with Examiner that the dotted line box labeled with numeral 2 is relatively arbitrarily drawn. Therefore, Examiner again maintains that Yao discloses “an insulating layer disposed on in direct contact with an upper surface of the driving circuit layer.” Applicant’s final assertions regarding the layer 21 and the electrode 23 are moot in view of Examiner’s new interpretation of Yao and the corresponding updated mapping of Yao to claims 1 and 10 necessitated by Applicant’s amendments therein, which resulted in the new grounds of rejection under 35 USC 102 using Yao. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IAN DEGRASSE/Examiner, Art Unit 2818 /JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Show 2 earlier events
Sep 14, 2025
Response Filed
Oct 24, 2025
Final Rejection mailed — §102, §103
Dec 15, 2025
Response after Non-Final Action
Jan 23, 2026
Request for Continued Examination
Feb 02, 2026
Response after Non-Final Action
Apr 09, 2026
Non-Final Rejection mailed — §102, §103
Jun 10, 2026
Response Filed
Aug 31, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
81%
Grant Probability
83%
With Interview (+1.8%)
3y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 26 resolved cases by this examiner. Grant probability derived from career allowance rate.

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