Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed August 8, 2025.
Status of claims to be treated in this office action:
a. Independent: 1, 9, 10, 15
b. Pending: 1-3, 5-8, 15-18
Claims 1, 6, and 15 have been amended, claim 4 has been canceled, and claims 9-14 are non-elected.
Specification
The amendments to the Specification have been reviewed and are accepted by
the Examiner.
The disclosure is objected to because of the following informality: on page 2, para. [0007], add “An” before “embodiment”.
Appropriate correction is required.
Claim Objections
The claim objections are withdrawn pursuant to claim amendments.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 5-8, and 15-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. New grounds of rejection are made in view of a different embodiment of Lim et al. (US Pub. 20170154677 A1; “Lim”) and further in view of Yun et al. (CN 107045892 A; “Yun”). Lim teaches verification immediately after programming in Fig. 20 and paras. [0144]-[0148]. Yun teaches a second data that is received during the first program operation in Fig. 21 and para. [0164]. Specifically, Fig. 21 shows that second data D_P2 is received during the first program operation VPGM, which is immediately followed by verify operation VFY1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-8, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US Pub. 20170154677 A1) in view of Yun (CN 107045892 A).
Regarding independent claim 1, Lim discloses a method of operating a memory device (Fig. 20: operating method of a nonvolatile memory device; [0029]; Fig. 1: nonvolatile memory device 110; [0053]), comprising:
receiving a first data bit among a plurality of data bits (Fig. 20: step S410; [0144]) to be stored in each of a plurality of memory cells ([0070]: First bits to be programmed at memory cells of a physical page may constitute a first logical page; [0054]: The nonvolatile memory device 110 may include a plurality of nonvolatile memory cells) from a memory controller ([0089]: the controller 120 may transmit a data input command C_Din, an address ADDR_P, first data D_P1, a dump command C_DM, and an end command C_E1; Fig. 1: controller 120; [0053]-[0054]);
performing a program voltage apply operation on the plurality of memory cells ([0145]: In step S420, the nonvolatile memory device 110 may perform a program of a first program loop of a program operation) based on the first data bit ([0007]: The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command);
receiving a second data bit among the plurality of data bits from the memory controller while performing the program voltage apply operation ([0146]: In step S440, whether second data is received may be determined. For example, whether data of a second page or data of the remaining pages is loaded on the page buffer circuit 115 may be determined. When second data is not loaded on the page buffer circuit 115 until a program and a verification read of the first program loop are performed, the nonvolatile memory device 110 may stop the program operation and may wait until the second data is received. Examiner acknowledges that Lim does not teach receiving second data during the program voltage apply operation); and
applying a verify voltage to the plurality of memory cells based on the first data bit immediately after the program voltage apply operation ([0145]: In step S430, the nonvolatile memory device 110 may perform a verification read of the first program loop).
Lim does not explicitly disclose:
receiving a second data bit among the plurality of data bits from the memory controller while performing the program voltage apply operation; and
However, Yun teaches:
receiving a second data bit (Fig. 21: D_P2 overlaps with the first VPGM) among the plurality of data bits from the memory controller ([0107]: the controller 120 may sequentially provide a data input command C_Din, an address ADDR_P, second data D_P2 , and an end command C_E2 to the nonvolatile memory 110) while performing the program voltage apply operation ([0164]: When the program voltage VPGM is applied to the selected word line and the first verification voltage VFY1 is applied thereto, the second data D_P2 may be provided to the page buffer circuit 115 through the input/output line DQ); and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Yun to Lim wherein the method of operating a memory device comprises receiving a second data bit among the plurality of data bits from the memory controller while performing the program voltage apply operation in order to provide an improved operating speed (Yun, [0010]).
Regarding claim 2, Lim and Yun together disclose all the limitations of claim 1, and further through Lim:
wherein performing the program voltage apply operation (Fig. 20: S420; [0145]) comprises:
applying a program-inhibit voltage to memory cells to be programmed to an erase state ([0116]: For example, bit lines corresponding to memory cells E_E and E_P3 to be programmed (or maintained) to the erase state E and the third program state P3 may be set to be program-inhibited) among the plurality of memory cells ([0054]).
Regarding claim 3, Lim and Yun together disclose all the limitations of claim 2, and further through Lim:
wherein performing the program voltage apply operation (Fig. 20: S420) further comprises:
applying a program voltage to the plurality of memory cells after applying the program-inhibit voltage ([0116]: Afterwards, at T2, the row decoder circuit 113 may apply a program voltage VPGM to a selected word line).
Regarding claim 5, Lim and Yun together disclose all the limitations of claim 1, and further through Lim:
receiving a program command and an address from the memory controller (Fig. 1: 120; [0053]-[0054])) before receiving the first data bit (per Fig. 5 and [0089], the controller 120 may transmit a data input command C_Din and an address ADDR_P through the input/output lines DQ before transmitting first data D_P1) and receiving the second data bit (per Fig. 5 and [0094], the controller 120 may transmit another data input command C_Din and an address ADDR_P before transmitting second data D_P2).
Regarding claim 6, Lim and Yun together disclose all the limitations of claim 1, and further through Lim:
performing another program voltage apply operation (Fig. 20: step S460; [0104]) after performing the program voltage apply operation (S420) based on the first data bit ([0007]), the another program voltage apply operation (S460) based on the first data bit and the second data bit ([0007]: The nonvolatile memory device is configured to … continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device; also refer to Fig. 6, T7-T8 and [0096]).
Regarding claim 7, Lim and Yun together disclose all the limitations of claim 1, and further through Lim:
receiving a third data bit among the plurality of data bits ([0054]) after receiving the second data bit (Fig. 20: S440) from the memory controller ([0056]) while performing the program voltage apply operation (S420).
receiving a third data bit among the plurality of data bits (referring to a different embodiment, per [0139]: FIG. 19 shows a process in which a first program loop is performed when three bits are programmed at each memory cell) after receiving the second data bit (Fig. 19: data D_P3 is transmitted after data D_P2; per [0140], each page corresponds to one bit) from the memory controller ([0056]) while performing the program voltage apply operation (per Fig. 19, VPGM is applied and therefore the program voltage apply operation is performed while the second data bit is received; [0072]: a program voltage (e.g., VPGM)).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of a different embodiment of Lim to modified Lim wherein the method further comprises receiving a third data bit among the plurality of data bits after receiving the second data bit from the memory controller while performing the program voltage apply operation in order to program more than two bits at each memory cell (Lim, [0138]-[0139]).
Lim does not explicitly disclose:
receiving the second data bit from the memory controller while performing the program voltage apply operation.
However, Yun teaches:
receiving the second data bit (Fig. 21) from the memory controller ([0107]) while performing the program voltage apply operation ([0164]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Yun to modified Lim wherein the method of operating a memory device comprises receiving a second data bit from the memory controller while performing the program voltage apply operation in order to provide an improved operating speed (Yun, [0010]).
Regarding claim 8, Lim and Yun together disclose all the limitations of claim 7, and further through Lim:
after performing the program voltage apply operation on the plurality of memory cells ([0103]) based on the first data bit ([0007]), performing another program voltage apply operation on the plurality of memory cells based on the first data bit, the second data bit, and the third data bit.
after performing the program voltage apply operation on the plurality of memory cells (in a different embodiment, Fig. 19: program voltage VPGM at time T2) based on the first data bit, performing another program voltage apply operation on the plurality of memory cells based on the first data bit, the second data bit, and the third data bit (program voltage VPGM at T5; [0142]: a subsequent programming operation executed at time T5).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of a different embodiment of Lim to modified Lim wherein the method further comprises, after performing the program voltage apply operation on the plurality of memory cells ([0103]) based on the first data bit ([0007]), performing another program voltage apply operation on the plurality of memory cells based on the first data bit, the second data bit, and the third data bit in order to program more than two bits at each memory cell (Lim, [0138]-[0139]).
Regarding independent claim 15, Lim discloses a storage device (Fig. 1: storage device 100; [0053]), comprising:
a memory device (nonvolatile memory device 110; [0053]) including a plurality of memory cells ([0054]); and
a memory controller (Fig. 1: 120) configured to transmit a program command, an address, and a first data bit ([0089]: the controller 120 may transmit a data input command C_Din, an address ADDR_P, first data D_P1, a dump command C_DM, and an end command C_E1; per [0089], C_Din indicates that data to be programmed is received, so C_Din may be a program command) for the plurality of memory cells to the memory device (per [0056], the memory transmits data to the memory device through the input/output lines DQ), and transmit a second data bit to the memory device ([0056]) while the memory device is programming the first data bit to memory cells corresponding to the address among the plurality of memory cells in response to the program command ([0009]: first data corresponding to the address…The nonvolatile memory device, in response to receiving the first data, address and program start command, executes a first programming operation in which a programming voltage corresponding to the first data is applied to a memory cell of the nonvolatile memory device that is identified by the address; [0054]: The nonvolatile memory device 110 may receive a command and an address from the controller 120 through an input/output channel and may exchange data with the controller 120),
wherein programming the first data bit to the memory cells ([0007]) comprises:
performing a program voltage apply operation (Fig. 20: S420); and
performing a verify voltage apply operation immediately after the program voltage apply operation ([0145]).
Lim does not explicitly disclose:
transmit a second data bit to the memory device while the memory device is programming the first data bit to memory cells corresponding to the address among the plurality of memory cells
However, Yun teaches:
transmit a second data bit to the memory device while the memory device is programming the first data bit (Fig. 21; [0164]) to memory cells corresponding to the address among the plurality of memory cells in response to the program command ([0070]: The controller 120 may provide a command and an address to the nonvolatile memory 110 through the input/output line DQ, and may exchange data with the nonvolatile memory 110 through the input/output line DQ)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Yun to modified Lim wherein the memory controller is configured to transmit a second data bit to the memory device while the memory device is programming the first data bit to memory cells corresponding to the address among the plurality of memory cells in order to provide an improved operating speed (Yun, [0010]).
Regarding claim 16, Lim and Yun together disclose all the limitations of claim 15, and further through Lim:
wherein the memory device stores the first data bit to a page buffer group ([0008]: a page buffer circuit connected with the plurality of memory cells through bit lines and configured to store first data received from an external device; [0074]: During a program operation, the page buffer circuit 115 may store data to be programmed in memory cells) and thereafter transmits a ready signal to the memory controller (per [0054] & [0061], after data is exchanged between the controller 120 and the nonvolatile memory device 110 is programmed, the memory device may switch the state of its ready/busy signal RnB and transmit that to the controller).
Regarding claim 17, Lim and Yun together disclose all the limitations of claim 16, and further through Lim:
wherein the memory controller (Fig. 1: 120) receives the ready signal from the memory device and thereafter transmits the second data bit to the memory device ([0065]: Even though the nonvolatile memory device 110 sets the ready/busy signal RnB to a ready state after the first data is provided thereto and the program operation starts, the controller 120 may not allow other access operations except providing the second data).
Regarding claim 18, Lim and Yun together disclose all the limitations of claim 15, and further through Lim:
wherein the memory device (Fig. 1: 110) receives the second data bit ([0103]) and thereafter programs the first data bit and the second data bit to memory cells ([0007]) corresponding to the address (claim 18: the nonvolatile memory device, in response to receiving the second data, executes a second programming operation in which a programming voltage corresponding to both the first data and the second data is applied to the memory cell identified by the address).
The rejection below is a second rejection for claim 1 in order to help expedite the prosecution of the case.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Yun (CN 107045892 A).
Regarding independent claim 1, Yun discloses a method of operating a memory device (Fig. 21; [0163]: FIG. 21 illustrates a process of performing a first program loop of the program operation shown in FIG. 20. In FIG. 21, the abscissa represents time T, and the ordinate represents data transmitted through the input/output line DQ and a voltage V applied to a word line connected to a selected memory cell), comprising:
receiving a first data bit (first data D_P1; [0164]) among a plurality of data bits to be stored in each of a plurality of memory cells ([0012]: The nonvolatile memory includes a memory cell array having a plurality of memory cells, a page buffer circuit connected to the plurality of memory cells through bit lines and configured to store first data received from an external device) from a memory controller ([0011]: The memory device includes a nonvolatile memory and a controller configured to provide first data, an address, and a program start command to the nonvolatile memory and to provide second data to the nonvolatile memory after providing the program start command to the nonvolatile memory);
performing a program voltage apply operation on the plurality of memory cells based on the first data bit ([0164]: When the first data D_P1 is completely received, the page buffer circuit 115 may set the bit line BL based on the first data D_P1 . At T2 , the row decoder circuit 113 may apply the program voltage VPGM to the selected word line; [0085]: The row decoder circuit 113 may operate according to the control of the control logic circuit 119);
receiving a second data bit among the plurality of data bits from the memory controller ([0164]: When the program voltage VPGM is applied to the selected word line and the first verification voltage VFY1 is applied thereto, the second data D_P2 may be provided to the page buffer circuit 115 through the input/output line DQ; [0070]: The controller 120 may provide a command and an address to the nonvolatile memory 110 through the input/output line DQ) while performing the program voltage apply operation (Fig. 21 shows D_P2 concurrent with first VPGM); and
applying a verify voltage to the plurality of memory cells based on the first data bit ([0164]) immediately after the program voltage apply operation (Fig. 21 shows first verification voltage VFY1 after first VPGM).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824 9/29/2025
/E.R.A./Examiner, Art Unit 2824
9/26/2025