Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 2 is objected to because of the following informalities: the limitation “centers of other two of the plurality of first terminals” is grammatically incorrection. For examination purposes the limitation is read as “the centers of two other of the plurality of first terminals”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (hereinafter Chen, US 2023/0005970).
In regards to independent claim 1, Chen teaches
a first substrate (10) provided with a plurality of first via holes (103) (Chen, [0045], “the main substrate 10 may include a plurality of interconnection vias 103 that tapers downward”);
a first pixel-driving circuit module (120) disposed on a side of the first substrate (101), and comprising at least one first pixel-driving circuit (transistor, 120) (Chen, [0046], “The TFT module 12 is disposed adjacent to and electrically connected to the first surface 101 of the main substrate 10…the TFT module 12 may be or include a driving circuit electrically connected to the light emitting devices 140);
a light-emitting module (140) disposed on a side of the first pixel-driving circuit module away from the first substrate (above the transistor 120), and comprising at least one light-emitting unit corresponding to the first pixel-driving circuit (140 electrically connected to 120 through 132) (Chen, [0046], “the driving circuit is configured to send a driving current (or voltage) to the light emitting devices 140, and the light emitting devices 140 are driven by the driving current to emit light”);
a first packaging structure (150), disposed on a side of the first substrate facing the first pixel-driving circuit module (On side 101), and covering the first pixel-driving circuit module and the light-emitting module (Covers 140 and 120)(Chen, [0053], “The protection layer 150 covers the light emitting devices 140 to protect the light emitting devices 140”); and
a first terminal module (terminal attached to 103), disposed on a side of the first substrate away from the first pixel-driving circuit module (disposed on 102), and comprising at least one first terminal group corresponding to the first pixel-driving circuit (Terminals associated with 116a-c) (Chen, Fig. 2);
wherein the first terminal group comprises a plurality of first terminals electrically connected with the first pixel-driving circuit through the plurality of first via holes (Terminals on side 102 are connect to vias through the substrate to 116a-c) (Chen, Fig. 2).
Allowable Subject Matter
Claims 2-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art fails to disclose or teach an obvious combination of the following limitations when taken with the claim as a whole:
Claim 2:
wherein in the first terminal group, connecting lines between a center of one of the plurality of first terminals and centers of other two of the plurality of first terminals are parallel to a first direction and a second direction respectively, and the first direction is perpendicular to the second direction.
Claims 3-8 depend upon and allowable claim; therefore, they are allowable.
Claim 9:
a second terminal module disposed on a side of the second substrate
away from the second pixel-driving circuit module, and comprising at least
one second terminal group corresponding to the second pixel-driving
circuit;
wherein the second terminal group comprises a plurality of second
terminals electrically connected with the second pixel-driving circuit
through the plurality of second via holes;
the first pixel-driving circuit corresponds to the second pixel-driving
circuit, and the first pixel-driving circuit and the second pixel-driving
circuit correspondingly disposed are configured to driving the light-
emitting unit.
Claims 10-11 depend upon and allowable claim; therefore, they are allowable.
Claims 12-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
The prior art fails to disclose or teach an obvious combination of the following limitations when taken with the claim as a whole:
Claim 12:
a wiring layer disposed on a side of the substrate;
wherein the plurality of display modules are disposed on a side
of the wiring layer away from the substrate; the wiring layer comprises a
plurality of first wirings electrically connected with the first pixel-driving
circuit through the plurality of first terminals; and a thickness of the wiring
layer is larger than or equal to 10 µm.
Claims 13-20 depend upon and allowable claim; therefore, they are allowable.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C TRAPANESE whose telephone number is (571)270-3304. The examiner can normally be reached Monday - Friday 7am-12pm & 8pm-10pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM C TRAPANESE/ Primary Examiner, Art Unit 2812