CTNF 18/194,550 CTNF 90893 DETAILED ACTION Notice of AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statements (IDS) submitted on 04/11/2024 and 03/28/2025 have been considered by the examiner. . Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-15 AIA Claim s 1-6, 10-16, and 18-20, are rejected under 35 U.S.C. 102( a) (1)/(a) (2 ) as being anticipated by KAMGAING (US 20230197618 A1), hereinafter referenced as KAMGAING . Regarding claim 1, KAMGAING teaches a substrate (Fig. 2, #200 called a package core. Paragraph 2026]), comprising: a glass core (Fig. 2, #202c called a glass layer. Paragraph [0027]); a plurality of glass layers (Fig. 2, #202a-202b and #202d-202e called a glass layers. Paragraph [0027]) on the glass core (Fig. 2. Paragraph [0027]- KAMGAING discloses package core 200 shows a plurality of glass layers 202a-202e that are bonded together.), wherein some of the glass layers are above the glass core and some of the glass layers are below the glass core (Fig. 2, illustrates glass layers #202a-202b are located on the glass core #202c while glass layers #202a-202e located below the glass core #202c. Paragraph [0027-0028]); a plurality of conductive traces (Fig. 2, #204, #206, #208, #210, #212, #214, and #217, #220, #230 called conductive element, and electrical routings. Paragraph [0027 and 0028]) wherein the conductive traces are in the glass core (Fig. 2, #204, #206, #208, #210, #212, and #214, called conductive element, and electrical routings. Paragraph [0027 and 0028]) and at least some of the glass layers (Fig. 2, #204, #206, #208, #210, #212, #214, #217, and #220, #230, called conductive element, and electrical routings. Paragraph [0027 and 0028]) ; and a plurality of conductive contacts on one or more surfaces of the substrate (Fig. 2, illustrates a plurality of conductive contacts #210, #214 called electrical routing and pads respectively. Paragraph [0028 and 0029]). Regarding claim 2, KAMGAING teaches the substrate of Claim 1, KAMGAING further teaches wherein the conductive traces (Fig. 2, #204, #206, #208, #210, #212, #214, and #217, #220, #230 called conductive element, and electrical routings. Paragraph [0027 and 0028]) comprise: a plurality of vias (Fig. 2, #204 and #208 called a through vias and plated through vias respectively. Paragraph [0027]), wherein the vias are in the glass core and at least some of the glass layers (Fig. 2, #204 and #208 called a through vias and plated through vias respectively. Paragraph [0027]- KAMGAING discloses in particular through vias 204, plane 206, plated through vias 208 that include pads, electrical routings 210, 212, and pads 214.) ; and a plurality of horizontal traces (Fig. 2, #222a and #220a called second conductive element are located in glass layer #202d and #202a respectively. Paragraph [0028]) , wherein the horizontal traces are in at least some of the glass layers (Fig. 2, #222a and #220a called second conductive element are located in glass layer #202d and #202a respectively. Paragraph [0028]- KAMGAING discloses Capacitor 220 includes a first conductive element in the form of pad 214 that is at a surface of glass layer 202b, and a dielectric layer 220b on top of a second conductive element 220a that are at a surface of the glass layer 202a. Similarly, inductor 222 may be formed by a first conductive element in the form of pad 214 at the surface of glass layer 202c, a magnetic material 222b, and the second conductive element 222a when glass layer 202c is bonded with glass layer 202d.). Regarding claim 3, KAMGAING teaches the substrate of Claim 1, KAMGAING further teaches wherein at least some of the conductive contacts are to be electrically coupled to a circuit board or an integrated circuit package (Fig. 2, illustrates a conductive contact #204 is electrically coupled to a circuit board #202b called a glass layer. Paragraph [0028]-KAMGAING discloses Capacitor 220 includes a first conductive element in the form of pad 214 that is at a surface of glass layer 202b, and a dielectric layer 220b on top of a second conductive element 220a that are at a surface of the glass layer 202a. Similarly, inductor 222 may be formed by a first conductive element in the form of pad 214 at the surface of glass layer 202c, a magnetic material 222b, and the second conductive element 222a when glass layer 202c is bonded with glass layer 202d.). Regarding claim 4, KAMGAING teaches the substrate of Claim 1, KAMGAING further teaches wherein at least some of the conductive contacts are to be electrically coupled to an integrated circuit die (Fig. 2, illustrates the active die #247 is electrically coupled to the package substrate #200 and conductive contacts #210, #214 via the glass #202d, #202e. Paragraph [0031]-KAMGAING discloses embedded active die 240 includes a cavity 246, which may be similar to cavity 216, into the glass layer 202d. An active die 247 is inserted into the cavity 246, with electrical contacts 247a of the active die 247 touching an electrical routing layer at the bottom of the cavity 247 (not shown but similar to routing layer 116a of FIG. 1). A bottom of the active die 247 may be supported by a pad 214 embedded within glass layer 202c. Further in paragraph [0028]-KAMGAING discloses a first conductive element in the form of pad 214 at the surface of glass layer 202c. Please also read paragraph [0029]) . Regarding claim 5, KAMGAING teaches the substrate of Claim 4, KAMGAING further teaches wherein the conductive contacts to be electrically coupled to the integrated circuit die comprise: a plurality of micro-bumps; or a plurality of pads (Fig. 1-2, illustrates a plurality of pads #247a are located on the integrated circuit die #247. Paragraph [0031]- KAMGAING discloses embedded active die 240 includes a cavity 246, which may be similar to cavity 216, into the glass layer 202d. An active die 247 is inserted into the cavity 246, with electrical contacts 247a of the active die 247 touching an electrical routing layer at the bottom of the cavity 247 (not shown but similar to routing layer 116a of FIG. 1). A bottom of the active die 247 may be supported by a pad 214 embedded within glass layer 202c. Further in paragraph [0028]-KAMGAING discloses a first conductive element in the form of pad 214 at the surface of glass layer 202c. Please also read paragraph [0029]) . Regarding claim 6, KAMGAING teaches the substrate of Claim 5, KAMGAING further teaches wherein the pads are recessed relative to the glass layers (Fig. 1-2, illustrates the pads #214 are located within the surface, recessed relative to the glass layers #202a-e. Paragraph [0028]). Regarding claim 10, KAMGAING teaches the substrate of Claim 1, KAMGAING further teaches wherein the conductive traces comprise at least one of copper or titanium (Fig. 1-2. Paragraph [0022]-KAMGAING disclose the metal may include copper.) . Regarding claim 11, KAMGAING teaches an integrated circuit package (Fig. 1, #100a-c called a view of a glass layer. Paragraph [0021]- KAMGAING disclose figures herein may depict one or more layers of one or more package assemblies. Please also read paragraph [0022]), comprising: an integrated circuit die (Fig. 1-2, #247 called active die. Paragraph [0025]-KAMGAING discloses cavity #116 may have a depth, width, and length that is large enough to accommodate a die (not shown) that may be either an active die or a passive die. Further in paragraph [0031]-KAMGAING discloses an active die 247 is inserted into the cavity 246, with electrical contacts 247a of the active die 247 touching an electrical routing layer at the bottom of the cavity 247 (not shown but similar to routing layer 116a of FIG. 1).); and a package substrate (Fig. 2, #200 called a package core. Paragraph 2026]) electrically coupled to the integrated circuit die (Fig. 2, illustrates the active die #247 is electrically coupled to the package substrate #200. Paragraph [0031]-KAMGAING discloses embedded active die 240 includes a cavity 246, which may be similar to cavity 216, into the glass layer 202d. An active die 247 is inserted into the cavity 246, with electrical contacts 247a of the active die 247 touching an electrical routing layer at the bottom of the cavity 247 (not shown but similar to routing layer 116a of FIG. 1). A bottom of the active die 247 may be supported by a pad 214 embedded within glass layer 202c. Further in paragraph [0028]-KAMGAING discloses a first conductive element in the form of pad 214 at the surface of glass layer 202c. Please also read paragraph [0029]), wherein the package substrate (Fig. 2, #200 called a package core. Paragraph 2026]) comprises: a glass core (Fig. 2, #202c called a glass layer. Paragraph [0027]) ; a plurality of glass layers (Fig. 2, #202a-202b and #202d-202e called a glass layers. Paragraph [0027]) on the glass core (Fig. 2. Paragraph [0027]- KAMGAING discloses package core 200 shows a plurality of glass layers 202a-202e that are bonded together.) , wherein some of the glass layers are above the glass core and some of the glass layers are below the glass core (Fig. 2, illustrates glass layers #202a-202b are located on the glass core #202c while glass layers #202a-202e located below the glass core #202c. Paragraph [0027-0028]) ; a plurality of conductive traces (Fig. 2, #204, #206, #208, #210, #212, #214, and #217, called conductive element, and electrical routings. Paragraph [0027 and 0028]) , wherein the conductive traces are in the glass core (Fig. 2, #204, #206, #208, #210, #212, and #214, called conductive element, and electrical routings located in the glass core. Paragraph [0027 and 0028]) and at least some of the glass layers (Fig. 2, #204, #206, #208, #210, #212, #214, #217, and #220, #230, called conductive element, and electrical routings are located in the glass layers. Paragraph [0027 and 0028]) ; and a plurality of conductive contacts on one or more surfaces of the package substrate (Fig. 2, illustrates a plurality of conductive contacts #210, #214 called electrical routing and pads respectively. Paragraph [0028 and 0029]). Regarding claim 12, KAMGAING teaches the integrated circuit package of Claim 11, KAMGAING further teaches wherein at least some of the conductive contacts are to be electrically coupled to a circuit board or another integrated circuit package (Fig. 2, illustrates a conductive contact #204 is electrically coupled to a circuit board #202b called a glass layer. Paragraph [0028]-KAMGAING discloses Capacitor 220 includes a first conductive element in the form of pad 214 that is at a surface of glass layer 202b, and a dielectric layer 220b on top of a second conductive element 220a that are at a surface of the glass layer 202a. Similarly, inductor 222 may be formed by a first conductive element in the form of pad 214 at the surface of glass layer 202c, a magnetic material 222b, and the second conductive element 222a when glass layer 202c is bonded with glass layer 202d.). Regarding claim 13, KAMGAING teaches the integrated circuit package of Claim 11, KAMGAING further teaches wherein at least some of the conductive contacts are electrically coupled to the integrated circuit die (Fig. 2, illustrates the active die #247 is electrically coupled to the package substrate #200 and conductive contacts #210, #214 via the glass #202d, #202e. Paragraph [0031]-KAMGAING discloses embedded active die 240 includes a cavity 246, which may be similar to cavity 216, into the glass layer 202d. An active die 247 is inserted into the cavity 246, with electrical contacts 247a of the active die 247 touching an electrical routing layer at the bottom of the cavity 247 (not shown but similar to routing layer 116a of FIG. 1). A bottom of the active die 247 may be supported by a pad 214 embedded within glass layer 202c. Further in paragraph [0028]-KAMGAING discloses a first conductive element in the form of pad 214 at the surface of glass layer 202c. Please also read paragraph [0029]) . Regarding claim 14, KAMGAING teaches the integrated circuit package of Claim 11, KAMGAING further teaches wherein the integrated circuit die is embedded in a cavity of the package substrate (Fig. 2, illustrates the integrated circuit die #247 is embedded in a cavity #246. Paragraph [0031]-KAMGAING discloses embedded active die 240 includes a cavity 246, which may be similar to cavity 216, into the glass layer 202d. An active die 247 is inserted into the cavity 246, with electrical contacts 247a of the active die 247 touching an electrical routing layer at the bottom of the cavity 247 (not shown but similar to routing layer 116a of FIG. 1). A bottom of the active die 247 may be supported by a pad 214 embedded within glass layer 202c. Further in paragraph [0028]-KAMGAING discloses a first conductive element in the form of pad 214 at the surface of glass layer 202c. Please also read paragraph [0029]), Regarding claim 15, KAMGAING teaches the integrated circuit package of Claim 11, KAMGAING further teaches wherein the integrated circuit die comprises processing circuitry, communication circuitry, or memory circuitry (Fig. 7. Paragraph [0055]-KAMGAING discloses the integrated circuit 710 is complemented with a subsequent integrated circuit 711. Useful embodiments include a dual processor 713 and a dual communications circuit 715 and dual on-die memory 717 such as SRAM. In an embodiment, the dual integrated circuit 710 includes embedded on-die memory 717 such as eDRAM.). Regarding claim 16, KAMGAING teaches an electronic device (Fig. 7, #700a-c called an electronic system. Paragraph [0052]- KAMGAING disclose FIG. 7 is a schematic of a computer system 700, in accordance with an embodiment of the present invention. The computer system 700 (also referred to as the electronic system 700) as depicted can embody a multilayer glass substrate, according to any of the several disclosed embodiments and their equivalents as set forth in this disclosure.) , comprising: a circuit board (Fig. 2, #202b called a glass layer. Paragraph [0028]-KAMGAING discloses Capacitor 220 includes a first conductive element in the form of pad 214 that is at a surface of glass layer 202b, and a dielectric layer 220b on top of a second conductive element 220a that are at a surface of the glass layer 202a. Similarly, inductor 222 may be formed by a first conductive element in the form of pad 214 at the surface of glass layer 202c, a magnetic material 222b, and the second conductive element 222a when glass layer 202c is bonded with glass layer 202d.); and an integrated circuit package (Fig. 7, #710 called an integrated circuit. Paragraph [0054]) electrically coupled to the circuit board (Fig. 2. Paragraph [0054]-KAMGAING discloses the integrated circuit 710 includes a processor 712 that can be of any type. As used herein, the processor 712 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor 712 includes, or is coupled with, a multilayer glass substrate, as disclosed herein. Please also read paragraph [0058]), wherein the integrated circuit package (Fig. 7, #710 called an integrated circuit. Paragraph [0054 and 0058]) comprises: one or more integrated circuit dies (Fig. 1-2, #247 called active die. Paragraph [0025]-KAMGAING discloses cavity #116 may have a depth, width, and length that is large enough to accommodate a die (not shown) that may be either an active die or a passive die. Further in paragraph [0058]-KAMGAING disclose as shown herein, the integrated circuit 710 can be implemented in a number of different embodiments, including a package substrate having a multilayer glass substrate, according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit.) ; and a package substrate (Fig. 2, #200 called a package core. Paragraph 2026]) electrically coupled to the one or more integrated circuit dies (Fig. 2, illustrates the active die #247 is electrically coupled to the package substrate #200. Paragraph [0031]-KAMGAING discloses embedded active die 240 includes a cavity 246, which may be similar to cavity 216, into the glass layer 202d. An active die 247 is inserted into the cavity 246, with electrical contacts 247a of the active die 247 touching an electrical routing layer at the bottom of the cavity 247 (not shown but similar to routing layer 116a of FIG. 1). A bottom of the active die 247 may be supported by a pad 214 embedded within glass layer 202c. Further in paragraph [0028]-KAMGAING discloses a first conductive element in the form of pad 214 at the surface of glass layer 202c. Please also read paragraph [0029]), wherein the package substrate (Fig. 2, #200 called a package core. Paragraph 2026]) comprises: a glass core (Fig. 2, #202c called a glass layer. Paragraph [0027]) ; a plurality of glass layers (Fig. 2, #202a-202b and #202d-202e called a glass layers. Paragraph [0027]) on the glass core (Fig. 2. Paragraph [0027]- KAMGAING discloses package core 200 shows a plurality of glass layers 202a-202e that are bonded together.) , wherein some of the glass layers are above the glass core and some of the glass layers are below the glass core (Fig. 2, illustrates glass layers #202a-202b are located on the glass core #202c while glass layers #202a-202e located below the glass core #202c. Paragraph [0027-0028]) ; a plurality of conductive traces (Fig. 2, #204, #206, #208, #210, #212, #214, and #217, called conductive element, and electrical routings. Paragraph [0027 and 0028]) , wherein the conductive traces are in the glass core (Fig. 2, #204, #206, #208, #210, #212, and #214, called conductive element, and electrical routings located in the glass core. Paragraph [0027 and 0028]) and at least some of the glass layers (Fig. 2, #204, #206, #208, #210, #212, #214, #217, and #220, #230, called conductive element, and electrical routings are located in the glass layers. Paragraph [0027 and 0028]) ; and a plurality of conductive contacts on one or more surfaces of the package substrate (Fig. 2, illustrates a plurality of conductive contacts #210, #214 called electrical routing and pads respectively. Paragraph [0028 and 0029]). Regarding claim 18, KAMGAING teaches a method, comprising: receiving a glass core (Fig. 2, #202c called a glass layer. Paragraph [0027]); forming a plurality of glass layers (Fig. 2, #202a-202b and #202d-202e called a glass layers. Paragraph [0027]) on the glass core (Fig. 2. Paragraph [0027]- KAMGAING discloses package core 200 shows a plurality of glass layers 202a-202e that are bonded together.) , wherein some of the glass layers are formed above the glass core and some of the glass layers are formed below the glass core (Fig. 2, illustrates glass layers #202a-202b are located on the glass core #202c while glass layers #202a-202e located below the glass core #202c. Paragraph [0027-0028]) ; forming a plurality of conductive traces (Fig. 2, #204, #206, #208, #210, #212, #214, and #217, called conductive element, and electrical routings. Paragraph [0027 and 0028]) in the glass core (Fig. 2, #204, #206, #208, #210, #212, and #214, called conductive element, and electrical routings. Paragraph [0027 and 0028]) and at least some of the glass layers (Fig. 2, #204, #206, #208, #210, #212, #214, #217, and #220, #230, called conductive element, and electrical routings. Paragraph [0027 and 0028]) ; and forming a plurality of conductive contacts on one or more surfaces of the glass layers (Fig. 2, illustrates a plurality of conductive contacts #210, #214 called electrical routing and pads respectively. Paragraph [0028 and 0029]) . Regarding claim 19, KAMGAING teaches the method of Claim 18, KAMGAING further teaches further comprising: attaching an integrated circuit die to at least some of the conductive contacts (Fig. 2, illustrates the active die #247 is electrically coupled to the package substrate #200 and conductive contacts #210, #214 via the glass #202d, #202e. Paragraph [0031]-KAMGAING discloses embedded active die 240 includes a cavity 246, which may be similar to cavity 216, into the glass layer 202d. An active die 247 is inserted into the cavity 246, with electrical contacts 247a of the active die 247 touching an electrical routing layer at the bottom of the cavity 247 (not shown but similar to routing layer 116a of FIG. 1). A bottom of the active die 247 may be supported by a pad 214 embedded within glass layer 202c. Further in paragraph [0028]-KAMGAING discloses a first conductive element in the form of pad 214 at the surface of glass layer 202c. Please also read paragraph [0029]) . Regarding claim 20, KAMGAING teaches the method of Claim 18, KAMGAING further teaches further comprising: forming a cavity in the glass core (Fig. 2, illustrates a cavity #246 in the glass core #202c. Paragraph [0031]) and/or at least some of the glass layers (Fig. 2. Paragraph [0031]-KAMGAING discloses embedded active die 240 includes a cavity 246, which may be similar to cavity 216, into the glass layer 202d. An active die 247 is inserted into the cavity 246, with electrical contacts 247a of the active die 247 touching an electrical routing layer at the bottom of the cavity 247 (not shown but similar to routing layer 116a of FIG. 1). A bottom of the active die 247 may be supported by a pad 214 embedded within glass layer 202c.); and embedding an integrated circuit die in the cavity (Fig. 2. Paragraph [0031]-KAMGAING discloses embedded active die 240 includes a cavity 246, which may be similar to cavity 216, into the glass layer 202d. An active die 247 is inserted into the cavity 246, with electrical contacts 247a of the active die 247 touching an electrical routing layer at the bottom of the cavity 247 (not shown but similar to routing layer 116a of FIG. 1). A bottom of the active die 247 may be supported by a pad 214 embedded within glass layer 202c.) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 7, is rejected under 35 U.S.C. 103 as being unpatentable over KAMGAING (US 20230197618 A1), hereinafter referenced as KAMGAING in view of Darmawikarta et al. (US 20230094686 A1), hereinafter referenced as Darmawikarta . Regarding claim 7, KAMGAING teaches the substrate of Claim 1, KAMGAING fail to explicitly teach wherein the glass core has a thickness ranging from approximately 100-1000 microns. However, Darmawikarta explicitly teaches wherein the glass core has a thickness ranging from approximately 100-1000 microns (Fig. 2A. Paragraph [0027]- Darmawikarta discloses Referring to FIGS. 2A-2C, the glass substrate 102 of the illustrated example has an overall thickness 214 between the first surface 106a and the second surface 106b. In the orientation of FIG. 2A, the overall thickness 214 extends in a z-direction of a reference cartesian coordinate system (e.g., a vertical or stack-up/build-up direction in the orientation of FIG. 1). In some examples, the overall thickness 214 can be between 100 micrometers (μm) and 1 millimeter (mm).). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of KAMGAING of having a substrate, comprising: a glass core; a plurality of glass layers on the glass core, wherein some of the glass layers are above the glass core and some of the glass layers are below the glass core; a plurality of conductive traces, wherein the conductive traces are in the glass core and at least some of the glass layers; and a plurality of conductive contacts on one or more surfaces of the substrate, with the teachings of Darmawikarta of having wherein the glass core has a thickness ranging from approximately 100-1000 microns. Wherein having KAMGAING`s wherein the glass core has a thickness ranging from approximately 100-1000 microns. The motivation behind the modification would have been to obtain an electrical device system that enhances that use multiple glass layers may improve the rigidity of the package and reduce warpage of the package stack up and have an improved package substrate, since both KAMGAING and Darmawikarta comprises of semiconductor materials and glass substrate, wherein KAMGAING electrical device that use multiple glass layers may improve the rigidity of the package and reduce warpage of the package stack up in contrast to legacy packages that use CCL layers while Darmawikarta semiconductor material comprises for smaller sized package assemblies (e.g., thin or low profile packages for mobile or other devices), a core of the substrate assembly needs to have improved total thickness variation (TTV), lower coefficient of thermal expansion (CTE), lower shrinkage, and higher elastic modulus. To improve such characteristics of a package substrate, glass layers can be employed. Please see KAMGAING et al. (US 20230197618 A1), Paragraph [0012] and Darmawikarta et al. (US 20230094686 A1), Paragraph [0014] . 07-21-aia AIA Claim 8, is rejected under 35 U.S.C. 103 as being unpatentable over KAMGAING (US 20230197618 A1), hereinafter referenced as KAMGAING in view of Hu et al. (US 20140299999 A1), hereinafter referenced as Hu . Regarding claim 8, KAMGAING teaches the substrate of Claim 1, KAMGAING fail to explicitly teach wherein at least some of the glass layers have a thickness ranging from approximately 10-50 microns. However, Hu explicitly teaches wherein at least some of the glass layers have a thickness ranging from approximately 10-50 microns (Fig. 1-2. Paragraph [0027]- Hu discloses the glass material of the solder mask layer 105 may include, for example, silica, quartz, nano fiber enhanced glass/organic or other similar glass materials. In some embodiments, the solder mask layer 105 has a thickness of the glass material ranging from 15 to 50 microns in a direction (e.g., up and down in FIG. 1) that is substantially perpendicular to a plane formed by the solder mask layer 105.). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of KAMGAING of having a substrate, comprising: a glass core; a plurality of glass layers on the glass core, wherein some of the glass layers are above the glass core and some of the glass layers are below the glass core; a plurality of conductive traces, wherein the conductive traces are in the glass core and at least some of the glass layers; and a plurality of conductive contacts on one or more surfaces of the substrate, with the teachings of Hu of having wherein at least some of the glass layers have a thickness ranging from approximately 10-50 microns. Wherein having KAMGAING`s wherein at least some of the glass layers have a thickness ranging from approximately 10-50 microns. The motivation behind the modification would have been to obtain an electrical device system that enhances that use multiple glass layers may improve the rigidity of the package and reduce warpage of the package stack up and have an improved package substrate reducing moisture, since both KAMGAING and Hu integrated circuit package comprises of semiconductor materials and glass substrate, wherein KAMGAING electrical device that use multiple glass layers may improve the rigidity of the package and reduce warpage of the package stack up in contrast to legacy packages that use CCL layers while Hu semiconductor material comprises the glass material may reduce a moisture update (e.g., provide greater barrier to undesirable moisture in the package. Thus, increase power efficiency for the electrical signals in the IC package assembly 100. Please see KAMGAING et al. (US 20230197618 A1), Paragraph [0012] and Hu et al. (US 20140299999 A1), Paragraph [0031] . 07-21-aia AIA Claim 9, is rejected under 35 U.S.C. 103 as being unpatentable over KAMGAING (US 20230197618 A1), hereinafter referenced as KAMGAING in view of PAPAKONSTANTINOU et al. (US 20220017415 A1), hereinafter referenced as PAPAKONSTANTINOU . Regarding claim 9, KAMGAING teaches the substrate of Claim 1, KAMGAING fail to explicitly teach wherein at least some of the glass layers comprise silicon and oxygen. However, PAPAKONSTANTINOU explicitly teaches wherein at least some of the glass layers comprise silicon and oxygen (Fig. 1. Paragraph [0044]- PAPAKONSTANTINOU discloses the silicate glass may comprise (e.g. consist of) predominantly silicon and oxygen. However, the silicate glass may also contain one or more elements in addition to silicon and oxygen. For example, the silicate glass may contain aluminium, sodium, iron, chromium, lead, zinc, calcium, manganese, magnesium, barium, potassium, boron, fluorine, germanium, sulphur, selenium and/or tellurium, in addition to silicon and oxygen.) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of KAMGAING of having a substrate, comprising: a glass core; a plurality of glass layers on the glass core, wherein some of the glass layers are above the glass core and some of the glass layers are below the glass core; a plurality of conductive traces, wherein the conductive traces are in the glass core and at least some of the glass layers; and a plurality of conductive contacts on one or more surfaces of the substrate, with the teachings of PAPAKONSTANTINOU of having wherein at least some of the glass layers comprise silicon and oxygen. Wherein having KAMGAING`s wherein at least some of the glass layers comprise silicon and oxygen. The motivation behind the modification would have been to obtain an electrical device system that enhances that use multiple glass layers may improve the rigidity of the package and reduce warpage of the package stack up in contrast to legacy packages that use CCL layers, since both KAMGAING and PAPAKONSTANTINOU comprises of semiconductor materials, wherein KAMGAING electrical device that use multiple glass layers may improve the rigidity of the package and reduce warpage of the package stack up in contrast to legacy packages that use CCL layers while PAPAKONSTANTINOU semiconductor material comprises of thermally insulating product. Please see KAMGAING et al. (US 20230197618 A1), Paragraph [0012] and PAPAKONSTANTINOU et al. (US 20220017415 A1), Paragraph [0037] . 07-21-aia AIA Claim 17, is rejected under 35 U.S.C. 103 as being unpatentable over KAMGAING (US 20230197618 A1), hereinafter referenced as KAMGAING in view of LEVESQUE et al. (US 20150189223 A1), hereinafter referenced as LEVESQUE . Regarding claim 17, KAMGAING teaches the electronic device of Claim 16, KAMGAING further teaches wherein the electronic device is a cell phone, a computer, a server (Fig. 1. Paragraph [0052]-KAMGAING discloses the computer system 700 may be a mobile device such as a netbook computer. The computer system 700 may be a mobile device such as a wireless smart phone. The computer system 700 may be a desktop computer. The computer system 700 may be a hand-held reader. The computer system 700 may be a server system.), a display device, a camera, or an appliance (Fig. 1. Paragraph [0057]-KAMGAING discloses the electronic system 700 also includes a display device 750, an audio output 760. In an embodiment, the electronic system 700 includes an input device such as a controller 770 that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system 700. In an embodiment, an input device 770 is a camera. In an embodiment, an input device 770 is a digital sound recorder. In an embodiment, an input device 770 is a camera and a digital sound recorder.). KAMGAING fail to explicitly teach wherein the electronic device is a wearable device, a video playback device, a video game console, or a vehicle control unit. However, LEVESQUE discloses wherein the electronic device is a wearable device (Fig. 1. Paragraph [0034]-LEVESQUE discloses an electronic handheld device, which may be a phone or a tablet, or a wearable device, such as a smartwatch, bracelet, necklace, headband, glasses, head mounted display,), a video playback device (Fig. 1. Paragraph [0035]- LEVESQUE discloses the electronic playback device 130 may be the same device as the electronic device 140 that includes the sensor 102, the video recorder 104, and the audio recorder 106. Please also read paragraph [0031]) , a video game console (Fig. 1. Paragraph [0043]- LEVESQUE discloses the playback device may be a gaming console connected to a television having the display 120 and the speaker 122, and also connected to a gaming peripheral, such as a gamepad, that includes the haptic output device 118 to provide the haptic effect.) , or a vehicle control unit (Fig. 1. Paragraph [0040]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of KAMGAING of having a substrate, comprising: a glass core; a plurality of glass layers on the glass core, wherein some of the glass layers are above the glass core and some of the glass layers are below the glass core; a plurality of conductive traces, wherein the conductive traces are in the glass core and at least some of the glass layers; and a plurality of conductive contacts on one or more surfaces of the substrate, with the teachings of LEVESQUE of having wherein the electronic device is a wearable device, a video playback device, a video game console, or a vehicle control unit. Wherein having KAMGAING`s wherein the electronic device is a wearable device, a video playback device, a video game console, or a vehicle control unit. The motivation behind the modification would have been to obtain an electrical device system that enhances that use multiple glass layers may improve the rigidity of the package and reduce warpage of the package stack up in contrast to legacy packages that use CCL layers, since both KAMGAING and LEVESQUE are electrical device with magnetic materials, wherein KAMGAING electrical device that use multiple glass layers may improve the rigidity of the package and reduce warpage of the package stack up in contrast to legacy packages that use CCL layers while LEVESQUE electrical device that provide an even more realistic and immersive experience for the viewer watching the point-of-view video and feeling haptic sensation playback. Please see KAMGAING et al. (US 20230197618 A1), Paragraph [0012] and LEVESQUE et al. (US 20150189223 A1), Paragraph [0005]. Conclusion Listed below are the prior arts made of record and not relied upon but are considered pertinent to applicant’s disclosure. (a) POLLARD et al. (US 20190341320 A1)- Electronics packages that incorporate components such as glass-based interposer assemblies are disclosed, as well as methods of forming thereof. A method includes bonding a glass-based substrate to a carrier, applying a metallization layer and/or a dielectric layer over the glass-based substrate to obtain a layered structure bonded to the carrier, removing sections of the layered structure such that portions of the layered structure remain on the carrier with a space between each thereof, attaching one or more dies to the portions,...... ...... (Fig. 1, Abstract). (b) Duan et al. (US 20240030204 A1)- Panel-level high performance computing (HPC) computing architectures and methods for making the same are disclosed. Panel architectures with and without glass cores comprise dielectric layers with interconnect structures (vias, conductive traces) to translate die-level pinouts arranged at a fine pitch to panel-level pinouts arranged at a coarser pitch. Local interconnects and local interconnect components provide for electrical communication between integrated circuit dies in a panel. Coreless panel architectures can comprise a glass reinforcement layer to provide additional mechanical stiffness...... ...... (Figs. 1-4, Abstract). (c) KIM et al. (US 20190144332 A1)- According to an embodiment, a cover glass includes a glass plate forming at least a portion of an electronic device, and a first coat layer deposited on a surface of the glass plate, the first coat layer at least partially including a network structure. The first coat layer includes silicon (Si), oxygen (O), and at least one impurity, and such that Si—O bonds are 80% or more by weight of the first coat layer. A polysilazane-applied coat is laid over one surface of the reinforced glass plate, providing an elegant haze glass cover....... ...... (Fig. 1, Abstract). (c) Gamba et al. (US 20200066626 A1)- Disclosed herein are pocket structures, materials, and methods for integrated circuit (IC) package supports. For example, in some embodiments, an IC package support may include: an interconnect pocket having sidewalls provided by a dielectric material; and a conductive contact at a bottom of the interconnect pocket,...... ...... (Figs. 1 and 2, Abstract). Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHINEYERE D WILLS-BURNS whose telephone number is (571)272-9752. The examiner can normally be reached on Monday -Friday, 7:00 am - 5:00 pm. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHINEYERE WILLS-BURNS/Supervisory Patent Examiner, Art Unit 2673 Application/Control Number: 18/194,550 Page 2 Art Unit: 2673 Application/Control Number: 18/194,550 Page 3 Art Unit: 2673 Application/Control Number: 18/194,550 Page 4 Art Unit: 2673 Application/Control Number: 18/194,550 Page 5 Art Unit: 2673 Application/Control Number: 18/194,550 Page 6 Art Unit: 2673 Application/Control Number: 18/194,550 Page 7 Art Unit: 2673 Application/Control Number: 18/194,550 Page 8 Art Unit: 2673 Application/Control Number: 18/194,550 Page 9 Art Unit: 2673 Application/Control Number: 18/194,550 Page 10 Art Unit: 2673 Application/Control Number: 18/194,550 Page 11 Art Unit: 2673 Application/Control Number: 18/194,550 Page 12 Art Unit: 2673 Application/Control Number: 18/194,550 Page 13 Art Unit: 2673 Application/Control Number: 18/194,550 Page 14 Art Unit: 2673 Application/Control Number: 18/194,550 Page 15 Art Unit: 2673 Application/Control Number: 18/194,550 Page 16 Art Unit: 2673 Application/Control Number: 18/194,550 Page 17 Art Unit: 2673 Application/Control Number: 18/194,550 Page 18 Art Unit: 2673 Application/Control Number: 18/194,550 Page 19 Art Unit: 2673 Application/Control Number: 18/194,550 Page 20 Art Unit: 2673
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