DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 04, 2026 has been entered.
Information Disclosure Statement
The information disclosure statement filed March 5, 2026 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered.
An English translation of the non-patent literature document “Office Action for Korean Patent Application No.10-2022-0110094 issued by the Korean Patent Office on February 24, 2026 is not provided.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Regarding claim 12. Claim 12 recites the limitation “wherein in the second region, the dummy dielectric plugs and the plug isolation layers are alternately arranged, along an extending direction of the bit lines, between adjacent bit lines” in the last paragraph of the claim language.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 4 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kim et al (U.S. 2021/0125998).
Regarding claim 1. Kim et al discloses a semiconductor device (FIG. 1A-1C) comprising:
a substrate (FIG. 1A-1C, item 100) including first (FIG. 1A-1C, item CAR) and second regions (FIG. 1A-1C, item INT);
a plurality of bit lines (FIG. 1A-1C, items BL) disposed over the substrate (FIG. 1A-1C, item 100);
spacers (FIG. 1A-1C, items SP) formed on both sidewalls ([0048]) of the bit lines (FIG. 1A-1C, items BL);
a plurality of storage node contact plugs (FIG. 1A-1C, items BC) formed between spacers (FIG. 1A-1C, items SP) formed on facing sidewalls ([0035]) of adjacent bit lines (FIG. 1A-1C, items BL) disposed over the first region (FIG. 1A-1C, item CAR) of the substrate (FIG. 1A-1C, item 100); and
a plurality of dummy dielectric plugs (FIG. 1A-1C, items 40r) formed between spacers (FIG. 1A-1C, items SP) formed on facing sidewalls ([0035]) of adjacent bit lines (FIG. 1A-1C, items BL) disposed over the second region (FIG. 1A-1C, item INT) of the substrate (FIG. 1A-1C, item 100), and
plug isolation layers (FIG. 1A-1C, item 25r) disposed between spacers (FIG. 1A-1C, items SP) formed on facing sidewalls ([0035]) of adjacent bit lines (FIG. 1A-1C, items BL)
wherein the dummy dielectric plugs (FIG. 1A-1C, items 40r) are disposed between the plug isolation layers (FIG. 1A-1C, item 25r) over the second region (FIG. 1A-1C, item INT) of the substrate (FIG. 1A-1C, item 100),
wherein the dummy dielectric plugs (FIG. 1A-1C, items 40r) include a dielectric material ([0035]).
Regarding claim 3. Kim et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein the plug isolation layers (FIG. 1A-1C, item 25r) include a dielectric material ([0042],[0060]).
Regarding claim 4. Kim et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein the plug isolation layers (FIG. 1A-1C, item 25r; [0042],[0060]) and the dummy dielectric plugs (FIG. 1A-1C, items 40r; [0035]) include silicon nitride ([0035]; [0042],[0060]), and wherein the storage node contact plugs (FIG. 1A-1C, items BC) include polysilicon ([0035]).
Claims 1, 2, 5-7, 12-14 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Jeon et al (U.S. 2022/0406789).
Regarding claim 1. Jeon et al discloses a semiconductor device (FIG. 1A-1B, item 100) comprising:
a substrate (FIG. 1A-1B, item 201) including first (FIG. 1A-1B, item CA) and second regions (FIG. 1A-1B, item ME);
a plurality of bit lines (FIG. 1A-1B, items 213) disposed over the substrate (FIG. 1B, item 201);
spacers (FIG. 1B, items BLS; [0022]) formed on both sidewalls ([0022]) of the bit lines (FIG. 1A-1B, items 213);
a plurality of storage node contact plugs (FIG. 1A-1B, item 221 in item CA) formed between spacers (FIG. 1B, items BLS; [0022]) formed on facing sidewalls ([0022]) of adjacent bit lines (FIG. 1A-1B, items 213) disposed over the first region (FIG. 1A-1B, item CA) of the substrate (FIG. 1B, item 201); and
a plurality of dummy dielectric plugs (FIG. 1A-1B, item 222 in ME; [0027]) formed between spacers (FIG. 1B, items BLS; [0022]) formed on facing sidewalls ([0022]) of adjacent bit lines (FIG. 1A-1B, items 213) disposed over the second region (FIG. 1A-1B, item ME) of the substrate (FIG. 1B, item 201), and
plug isolation layers (FIG. 1A, items 221D in ME, and items 222 in CA) disposed between spacers (FIG. 1B, items BLS; [0022]) formed on facing sidewalls ([0022]) of adjacent bit lines (FIG. 1A, items 213)
wherein the dummy dielectric plugs (FIG. 1A-1B, item 222 in ME; [0027]) are disposed between the plug isolation layers (FIG. 1A-1B, items 221D in ME) over the second region (FIG. 1A-1B, items ME) of the substrate (FIG. 1B, item 201),
wherein the dummy dielectric plugs (FIG. 1A-1B, item 222 in ME; [0027]) include a dielectric material ([0027]).
Regarding claim 2. Jeon et al discloses all the limitations of the semiconductor device of claim 1 above.
Jeon et al wherein the storage node contact plugs (FIG. 1A, item 221 in item CA) are disposed between ([0024]) the plug isolation layers (FIG. 1A, item 222 in item CA).
Regarding claim 5. Jeon et al discloses all the limitations of the semiconductor device of claim 1 above.
Jeon et al further discloses wherein bottom surfaces (FIG. 1B, bottom of item 222 in ME) of the dummy dielectric plugs (FIG. 1B, item 222 in ME) are disposed at a higher level (FIG. 1B, bottom of item 222 in ME is higher than a bottom of item 221) than a bottom surface (FIG. 1B, bottom of item 221) of the storage node contact plugs (FIG. 1B, item 221).
Regarding claim 6. Jeon et al discloses all the limitations of the semiconductor device of claim 1 above.
Jeon et al further discloses wherein each of the spacers (FIG. 1A-1B, items BLS) includes a multi-layered spacer ([0022]).
Regarding claim 7. Jeon et al discloses all the limitations of the semiconductor device of claim 1 above.
Jeon et al further discloses wherein a bottom surface (FIG. 1B, top surface of item 222 in ME) of the dummy dielectric plugs (FIG. 1B, item 222 in ME) is disposed at a higher surface (FIG. 1B, bottom of 222 in ME is higher than a bottom on item 221 in CA) than a bottom surface (FIG. 1B, bottom surface of item 221 in CA) of the conductive contact plugs (FIG. 1B, item 221 in CA).
Regarding claim 12. Jeon et al discloses a semiconductor device (FIG. 1A-1B, item 100) comprising:
a substrate (FIG. 1A-1B, item 201) including first (FIG. 1A-1B, item CA) and second regions (FIG. 1A-1B, item ME);
a plurality of bit lines (FIG. 1A-1B, items 213) disposed over the substrate (FIG. 1B, item 201);
a plurality of storage node contact plugs (FIG. 1A-1B, items 221 in CA) formed between adjacent bit lines (FIG. 1A-1B, items 213 in CA) disposed over the first region (FIG. 1A-1B, item CA) of the substrate (FIG. 1B, item 201);
a plurality of dummy dielectric plugs (FIG. 1A-1B, items 222 in ME) disposed between adjacent bit lines (FIG. 1A-1B, items 213 in ME) over the second region (FIG. 1A-1B, item CA) of the substrate (FIG. 1A-1B, items 201); and
plug isolation layers (FIG. 1B, items 221D in ME; FIG. 1B, item BLS in CA, [0022]) disposed between adjacent bit lines (FIG. 1A-1B, items 213),
wherein in the second region (FIG. 1A-1B, item ME), the dummy dielectric plugs (FIG. 1A-1B, items 222 in ME) and the plug isolation layers (FIG. 1A-1B, items 221D in ME) are alternately arranged ([0024]), along an extending direction (FIG. 1A-1B, item D2) of the bit lines (FIG. 1B, items 213), between adjacent bit lines (FIG. 1B, items 213).
Regarding claim 13. Jeon et al discloses all the limitations of the semiconductor device of claim 12 above.
Jeon et al further discloses wherein the dummy dielectric plugs (FIG. 1A-1B, items 222 in ME; [0027]) include a dielectric material ([0027]).
Regarding claim 14. Jeon et al discloses all the limitations of the semiconductor device of claim 12 above.
Jeon et al further discloses wherein the plug isolation layers (FIG. 1B, item BLS in CA, [0022]) and the dummy dielectric plugs (FIG. 1A-1B, items 222 in ME; [0027]) include a dielectric material ([0022]; [0027]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al (U.S. 2022/0406789) as applied to claim 1 above, and further in view of Kim et al (U.S. 2021/0125998).
Regarding claim 3. Jeon et al discloses all the limitations of the semiconductor device of claim 1 above.
Jeon et al further discloses wherein the plug isolation layers and the dummy dielectric plugs include a dielectric material.
Regarding claim 4. Jeon et al discloses all the limitations of the semiconductor device of claim 1 above.
Jeon et al further discloses wherein the storage node contact plugs include polysilicon.
wherein the plug isolation layers and the dummy dielectric plugs include silicon nitride, and wherein the storage node contact plugs include polysilicon.
Response to Arguments
Applicant's arguments filed March 04, 2026 have been fully considered but they are not persuasive.
On page 12-13 of applicant’s remarks, applicant appears to argue that Jeon et al fails to disclose dummy dielectric plugs having the following features: i) being formed between spacers formed on facing sidewalls of adjacent bit lines disposed over the second region of the substrate, ii) being disposed between plug isolation layers over the second region of the substrate, and iii) including a dielectric material.
Examiner respectfully disagrees with applicant’s assertion.
Examiner respectfully points out that Jeon et al discloses dummy dielectric plugs (FIG. 1A-1B, item 222 in ME) having the following features: i) being formed between spacers (item BLS) formed on facing sidewalls of adjacent bit lines (item 213) disposed over the second region (item ME) of the substrate (item 201), ii) being disposed between plug isolation layers (item 221D in ME) over the second region (item ME) of the substrate (item 201), and iii) including a dielectric material ([0027]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lim (U.S. 2014/0021521) discloses MOS CAPACITOR, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE USING THE SAME.
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/S.E.B./ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815