DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1, 2, 4-7, 9-12 are pending. Claims 9-11 are withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 24, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2021/0125998), and further in view of Kim et al (U.S. 2002/0001889).
Regarding claim 1. Kim et al (‘998) discloses a semiconductor device (FIG. 1A-1C) comprising:
a substrate (FIG. 1A-1C, item 100) including first (FIG. 1A-1C, item CAR) and second regions (FIG. 1A-1C, item INT);
a plurality of bit lines (FIG. 1A-1C, items BL) disposed over the substrate (FIG. 1A-1C, item 100);
spacers (FIG. 1A-1C, items SP) formed on both sidewalls ([0048]) of the bit lines (FIG. 1A-1C, items BL);
a plurality of storage node contact plugs (FIG. 1A-1C, items BC) formed between spacers (FIG. 1A-1C, items SP) formed on facing sidewalls ([0035]) of adjacent bit lines (FIG. 1A-1C, items BL) disposed over the first region (FIG. 1A-1C, item CAR) of the substrate (FIG. 1A-1C, item 100); and
a plurality of dummy dielectric plugs (FIG. 1A-1C, items 40r) formed between spacers (FIG. 1A-1C, items SP) formed on facing sidewalls ([0035]) of adjacent bit lines (FIG. 1A-1C, items BL) disposed over the second region (FIG. 1A-1C, item INT) of the substrate (FIG. 1A-1C, item 100), and
plug isolation layers (FIG. 1A-1C, item 25r) disposed between the spacers (FIG. 1A-1C, items SP) formed on facing sidewalls ([0035]) of adjacent bit lines (FIG. 1A-1C, items BL) over the first region (FIG. 1A-1C, item CAR) and the second region (FIG. 1A-1C, item INT) of the substrate (FIG. 1A-1C, item 100); and
wherein over the second region (FIG. 1A-1C, item INT) of the substrate (FIG. 1A-1C, item 100), the dummy dielectric plugs (FIG. 1A-1C, items 40r) are disposed between the plug isolation layers (FIG. 1A-1C, item 25r),
wherein the dummy dielectric plugs (FIG. 1A-1C, items 40r, [0045]) and the plug isolation layers (FIG. 1A-1C, item 25r, [0042],[0060]), include a dielectric material ([0045], [0042],[0060]).
Kim et al (‘998) fails to explicitly disclose
a stopper structure disposed over the second region of the substrate,
wherein over the second region of the substrate, the dummy dielectric plugs and the plug isolation layers have bottom surfaces disposed directly on the stopper region.
However, Kim et al (‘889) teaches
a stopper structure (FIG. 14, item 1390; [0077]) disposed over the second region (FIG. 14, item A1-A1’) of the substrate (FIG. 14, item 1100),
wherein over the second region (FIG. 14, item A1-A1’) of the substrate (FIG. 14, item 1100), the dummy dielectric plugs (FIG. 14, item 1450) and the plug isolation layers (FIG. 14, item 1700) have bottom surfaces disposed directly ([0087]-[0097]) on the stopper structure (FIG. 14, item 1390).
Since Kim et al (‘998) and Kim et al (‘889) teach bit lines, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Kim et al (‘998) with the teachings of a stopper structure disposed over the second region of the substrate, wherein over the second region of the substrate, the dummy dielectric plugs and the plug isolation layers have bottom surfaces disposed directly on the stopper region as disclosed by Kim et al (‘889). The use of the stopper layer as an etch stopper provides for the dummy dielectric layer pattern can be selectively removed without damage to a lower stopper (Kim et al (‘889), [0097]).
Regarding claim 4. Kim et al (‘998) and Kim et al (‘889) discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al (‘998) further discloses wherein the plug isolation layers (FIG. 1A-1C, item 25r; [0042],[0060]) and the dummy dielectric plugs (FIG. 1A-1C, items 40r; [0045]) include silicon nitride ([0045]; [0042],[0060]), and wherein the storage node contact plugs (FIG. 1A-1C, items BC) include polysilicon ([0035]).
Claims 1, 2, 5-7, 12 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al (U.S. 2022/0406789) and Kim et al (U.S. 2002/0001889).
Regarding claim 1. Jeon et al discloses a semiconductor device (FIG. 1A-1B, item 100) comprising:
a substrate (FIG. 1A-1B, item 201) including first (FIG. 1A-1B, item CA) and second regions (FIG. 1A-1B, item ME);
a plurality of bit lines (FIG. 1A-1B, items 213) disposed over the substrate (FIG. 1B, item 201);
spacers (FIG. 1B, items BLS; [0022]) formed on both sidewalls ([0022]) of the bit lines (FIG. 1A-1B, items 213);
a plurality of storage node contact plugs (FIG. 1A-1B, item 221 in item CA) formed between spacers (FIG. 1B, items BLS; [0022]) formed on facing sidewalls ([0022]) of adjacent bit lines (FIG. 1A-1B, items 213) disposed over the first region (FIG. 1A-1B, item CA) of the substrate (FIG. 1B, item 201); and
a plurality of dummy dielectric plugs (FIG. 1A-1B, item 222 in ME; [0027]) formed between spacers (FIG. 1B, items BLS; [0022]) formed on facing sidewalls ([0022]) of adjacent bit lines (FIG. 1A-1B, items 213) disposed over the second region (FIG. 1A-1B, item ME) of the substrate (FIG. 1B, item 201), and
plug isolation layers (FIG. 1A, items 221D in ME, and items 222 in CA) disposed between the spacers (FIG. 1B, items BLS; [0022]) formed on facing sidewalls ([0022]) of adjacent bit lines (FIG. 1A, items 213) over the first region (FIG. 1A-1B, item CA) and the second region (FIG. 1A-1B, items ME) of the substrate (FIG. 1A-1B, items ME)
wherein over the second region (FIG. 1A-1B, items ME) of the substrate (FIG. 1B, item 201) the dummy dielectric plugs (FIG. 1A-1B, item 222 in ME; [0027]) are disposed between the plug isolation layers (FIG. 1A-1B, items 221D in ME)
wherein the dummy dielectric plugs (FIG. 1A-1B, item 222 in ME; [0027]) include a dielectric material ([0027]).
Jeon et al fails to explicitly disclose
wherein the plug isolation layers include a dielectric material
a stopper structure disposed over the second region of the substrate,
wherein over the second region of the substrate, the dummy dielectric plugs and the plug isolation layers have bottom surfaces disposed directly on the stopper region,
However, Kim et al teaches
wherein the plug isolation layers (FIG. 14, item 1700) include a dielectric material ([0090])
a stopper structure (FIG. 14, item 1390; [0077]) disposed over the second region (FIG. 14, item A1-A1’) of the substrate (FIG. 14, item 1100),
wherein over the second region (FIG. 14, item A1-A1’) of the substrate (FIG. 14, item 1100), the dummy dielectric plugs (FIG. 14, item 1450) and the plug isolation layers (FIG. 14, item 1700) have bottom surfaces disposed directly ([0087]-[0097]) on the stopper structure (FIG. 14, item 1390).
Since Jeon et al and Kim et al teach bit lines, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Jeon et al with the teachings of wherein the plug isolation layers include a dielectric material, a stopper structure disposed over the second region of the substrate, wherein over the second region of the substrate, the dummy dielectric plugs and the plug isolation layers have bottom surfaces disposed directly on the stopper region as disclosed by Kim et al. The use of the stopper layer as an etch stopper provides for the dummy dielectric layer pattern can be selectively removed without damage to a lower stopper (Kim et al, [0097]).
Regarding claim 2. Jeon et al and Kim et al discloses all the limitations of the semiconductor device of claim 1 above.
Jeon et al wherein the storage node contact plugs (FIG. 1A, item 221 in item CA) are disposed between ([0024]) the plug isolation layers (FIG. 1A, item 222 in item CA).
Regarding claim 5. Jeon et al and Kim et al discloses all the limitations of the semiconductor device of claim 1 above.
Jeon et al further discloses wherein bottom surfaces (FIG. 1B, bottom of item 222 in ME) of the dummy dielectric plugs (FIG. 1B, item 222 in ME) are disposed at a higher level (FIG. 1B, bottom of item 222 in ME is higher than a bottom of item 221) than a bottom surface (FIG. 1B, bottom of item 221) of the storage node contact plugs (FIG. 1B, item 221).
Regarding claim 6. Jeon et al and Kim et al discloses all the limitations of the semiconductor device of claim 1 above.
Jeon et al further discloses wherein each of the spacers (FIG. 1A-1B, items BLS) includes a multi-layered spacer ([0022]).
Regarding claim 7. Jeon et al and Kim et al discloses all the limitations of the semiconductor device of claim 1 above.
Jeon et al further discloses wherein a bottom surface (FIG. 1B, top surface of item 222 in ME) of the dummy dielectric plugs (FIG. 1B, item 222 in ME) is disposed at a higher surface (FIG. 1B, bottom of 222 in ME is higher than a bottom on item 221 in CA) than a bottom surface (FIG. 1B, bottom surface of item 221 in CA) of the conductive contact plugs (FIG. 1B, item 221 in CA).
Regarding claim 12. Jeon et al discloses a semiconductor device (FIG. 1A-1B, item 100) comprising:
a substrate (FIG. 1A-1B, item 201) including first (FIG. 1A-1B, item CA) and second regions (FIG. 1A-1B, item ME);
a plurality of bit lines (FIG. 1A-1B, items 213) disposed over the substrate (FIG. 1B, item 201);
a plurality of storage node contact plugs (FIG. 1A-1B, items 221 in CA) disposed between adjacent bit lines (FIG. 1A-1B, items 213 in CA) over the first region (FIG. 1A-1B, item CA) of the substrate (FIG. 1B, item 201);
a plurality of dummy dielectric plugs (FIG. 1A-1B, items 222 in ME) disposed between adjacent bit lines (FIG. 1A-1B, items 213 in ME) over the second region (FIG. 1A-1B, item CA) of the substrate (FIG. 1A-1B, items 201);
plug isolation layers (FIG. 1B, items 221D in ME; FIG. 1B, item BLS in CA, [0022]) disposed between adjacent bit lines (FIG. 1A-1B, items 213),over at least the second region (FIG. 1A-1B, item CA) of the substrate (FIG. 1A-1B, items 201).
wherein over the second region (FIG. 1A-1B, item ME), the dummy dielectric plugs (FIG. 1A-1B, items 222 in ME) and the plug isolation layers (FIG. 1A-1B, items 221D in ME) are alternately arranged ([0024]) between adjacent bit lines (FIG. 1B, items 213) along an extending direction (FIG. 1A-1B, item D2) of the bit lines (FIG. 1B, items 213),
wherein the dummy dielectric plugs (FIG. 1A-1B, item 222 in ME; [0027]) include a dielectric material ([0027]).
Jeon et al fails to explicitly disclose
a stopper structure disposed over the second region of the substrate,
wherein over the second region of the substrate, the dummy dielectric plugs and the plug isolation layers have bottom surfaces disposed directly on the stopper region,
wherein the plug isolation layers include a dielectric material.
However, Kim et al teaches
a stopper structure (FIG. 14, item 1390; [0077]) disposed over the second region (FIG. 14, item A1-A1’) of the substrate (FIG. 14, item 1100),
wherein over the second region (FIG. 14, item A1-A1’) of the substrate (FIG. 14, item 1100), the dummy dielectric plugs (FIG. 14, item 1450) and the plug isolation layers (FIG. 14, item 1700) have bottom surfaces disposed directly ([0087]-[0097]) on the stopper structure (FIG. 14, item 1390),
wherein the plug isolation layers (FIG. 14, item 1700) include a dielectric material ([0090]).
Since Jeon et al and Kim et al teach bit lines, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Jeon et al with the teachings of a stopper structure disposed over the second region of the substrate, wherein over the second region of the substrate, the dummy dielectric plugs and the plug isolation layers have bottom surfaces disposed directly on the stopper region, wherein the plug isolation layers include a dielectric material as disclosed by Kim et al. The use of the stopper layer as an etch stopper provides for the dummy dielectric layer pattern can be selectively removed without damage to a lower stopper (Kim et al, [0097]).
Response to Arguments
Applicant's arguments filed June 24, 2026 have been fully considered but they are not persuasive.
Regarding 102/103 rejection.
On page 15 of applicant’s remarks, applicant appears to argue that Kim et al (‘998) fails to disclose in the second region, bottom surfaces of both dummy dielectric plugs and the plug isolation layers are disposed directly on the stopper structure.
Examiner respectfully points out that Kim et al (‘998) was not used to disclose applicant’s amended claim limitation and that Kim et al (‘889) teaches applicant’s amended claim limitation.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 16 of applicant’s remarks, applicant appears to argue that Jeon et al fails to disclose applicant’s amended claim 1 for the similar reasons as above.
Examiner respectfully disagrees with applicant’s remarks for the same analogous reasons as above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lim (U.S. 2014/0021521) discloses MOS CAPACITOR, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE USING THE SAME.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
Prosecution Insights