DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 6/25/2026. Claims 1-23 are pending in this application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1, 3-10, 15-21 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Keesu et al. (KR 2019-0052852).
Re claim 1, Keesu teaches, under BRI, Fig. 1, page 7, a printed circuit board comprising:
-a first insulating layer (10);
-a wiring pattern (circuit pattern 15) disposed in an upper side of the first insulating layer;
-a second insulating layer (30) disposed on and being in contact (via 20) with an upper surface of the first insulating layer (10) and having a cavity (C) exposing the wiring pattern (15); and
-an insulating pattern (20) disposed between the first and second insulating layers (10, 30), and having a side surface partially exposed by the cavity (C), while having an upper surface entirely covered by the second insulating layer (30).
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Note: in contact # directly/physically contact.
Re claim 3, Keesu teaches, Fig. 1, a portion of the side surface of the insulating pattern (20) exposed by the cavity (C) is substantially coplanar with a wall surface (at 32) of the cavity (C).
Re claim 4, Keesu teaches, Fig. 1, the insulating pattern (20) is disposed to surround the cavity (C).
Re claim 5, Keesu teaches, Fig. 1, the insulating pattern (20) has a thickness greater than a thickness of the wiring pattern (of 16).
Re claims 6 & 7, Keesu teaches, Fig. 1, the cavity (C) penetrates between an upper surface and a lower surface of the second insulating layer (30); wherein the cavity (c) exposes at least a portion of the upper surface of the fist insulating layer (10).
Re claim 8, Keesu teaches, Fig. 1, page 3, 1st par., a plurality of first wiring layers (15) respectively disposed on or within the first insulating layer (top & bottom surfaces of 10); and a plurality of first via layers (e.g., vias) respectively disposed within the first insulating layer (10) and connecting the plurality of first wiring layers to each other, wherein an uppermost layer among the plurality of first wiring layers includes the wiring pattern (15 with 16, 17 at top surface of 10).
Re claim 9, Keesu teaches, Fig. 1, a second wiring layer (at pattern 35) disposed on an upper surface of the second insulating layer (30); and a second via layer (within 30) disposed within the second insulating layer (30) and connecting the second wiring layer (35) to the plurality of first wiring layers (15).
Re claim 10, Keesu teaches, Fig. 1, a first resist layer (50) disposed on the upper surface of the second insulating layer (30) and including a first opening exposing the cavity (C) and a second opening (at 35) exposing at least a portion of the second wiring layer (at 35).
Re claim 15, Keesu teaches, under BRI, Fig. 1, pages 2, 3 & 7, a printed circuit board comprising:
-a first insulating layer (10);
-a wiring pattern (15) disposed in an upper side of the first insulating layer (10);
-a second insulating layer (30) disposed on and being in contact (via 20) with an upper surface of the first insulating layer (10) and having a cavity (C) exposing the wiring pattern (15); and
-an insulating pattern (20) disposed along a wall surface of the cavity (C), at least partially buried in the second insulating layer (30), and including a thermosetting resist material (e.g., thermosetting resin, material of 20 is similar to material of 10).
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Re claim 16, Keesu teaches the thermosetting resist material (e.g., epoxy resin, col. 2, last par.) reacts faster to sodium hydroxide (NaOH) than the wiring pattern (15) or the second insulating layer.
Re claim 17, Keesu teaches, under BRI, Fig. 1, page 7, a printed circuit board comprising:
-a first insulating layer (10);
-a wiring pattern (15) protruding (e.g., conductive post 35) from an upper surface of the first insulating layer (10);
-an insulating pattern (40) protruding from the upper surface of the first insulating layer (10); and
-a second insulating layer (20) disposed on the upper surface of the first insulating layer (10) to cover the insulating pattern (40) and having a cavity exposing the wiring pattern (15),
wherein the insulating pattern (40) includes one side surface (left side) and another side surface (right side) opposing each other, and
at least a portion of the one side surface of insulating pattern (40) is exposed to the cavity (C) and the another side surface of insulating pattern (40) is covered by the second insulating layer (20).
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Re claim 18, Keesu teaches, Fig. 1, the insulating pattern (40) surrounds the cavity (C).
Re claim 19, Keesu teaches, Fig. 1, the insulating pattern (40) has a thickness greater than a thickness of the wiring pattern (of 16).
Re claim 20, Keesu teaches, Fig. 1, a second wiring layer (35) disposed on an upper surface of the second insulating layer (20); and a second via (within 20) disposed in the second insulating layer (20) and connecting the second wiring layer (35) to another wiring pattern (under 20) protruding from the upper surface of the first insulating layer (10).
Re claim 21, Keesu teaches, Fig. 1, a first resist layer (50) disposed on the upper surface of the second insulating layer (20) and including a first opening exposing the cavity (C) and a second opening (at 35) exposing at least a portion of the second wiring layer (35).
Re claim 23, Keesu teaches, Fig. 1, an inclination angle of a wall surface (vertical wall at 90oC) of the cavity (C) with respect to the upper surface of the first insulating layer (10) is greater than an inclination angle of a wall surface of the second via (within 20, less than 90oC) with respect to the upper surface of the first insulating layer (10).
3. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US 2017/0077023).
Re claim 1, Tsai teaches, under BRI, Figs. 1-2, [0021, 0025, 0033], a printed circuit board comprising:
-a first insulating layer (36);
-a wiring pattern (123) disposed in an upper side of the first insulating layer (36);
-a second insulating layer (14, 26, 28) disposed on and being in contact (via 12) with an upper surface of the first insulating layer (36) and having a cavity (24) exposing the wiring pattern (123); and
-an insulating pattern (12) disposed between the first and second insulating layers (36 & 14, 26, 28), and having a side surface partially exposed by the cavity (24), while having an upper surface entirely covered by the second insulating layer (14, 26, 28).
Note: in contact # directly/physically contact.
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Keesu.
The teachings of Keesu have been discussed above.
Re claim 2, Keesu teaches, Fig. 1, the insulating pattern (20) is disposed on the upper surface of the first insulating layer (10) and at least partially buried in the second insulating layer (30), and a portion of the side surface of the insulating pattern (20) is exposed from the second insulating layer (30).
Keesu does not explicitly teach another side of the insulating pattern opposing the side surface is covered with the second insulating layer.
Keesu does teach, Fig. 1, surfaces of the insulating pattern (consider 20, 40) covered with the second insulating layer (30) & further teaches various techniques (e., laser, drilling, sandblasting) to form the cavity (C) (page 3, 7th-8th pars.).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Keesu to obtain another side of the insulating pattern opposing the side surface is covered with the second insulating layer as claimed, because, without due experimentation & based on various techniques, one of ordinary skill in the art would obtain same result desired structure that including another side of the insulating pattern opposing the side surface is covered with the second insulating layer.
5. Claims 11, 13, 14 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Keesu in view of Lee (US 2017/0019989).
The teachings of Keesu have been discussed above.
Re claims 11 & 22, Keesu does not explicitly teach a first electronic component disposed on the cavity and the first opening and connected to the wiring pattern;
and a second electronic component disposed on the second opening and connected to the at least a portion of the second wiring layer.
Lee teaches, Fig. 9, [0130, 0131], first electronic component (chip 400) disposed on the cavity (CA) and the first opening and connected to the wiring pattern (214); and a second electronic component (solder ball 500) disposed on the second opening and connected to the at least a portion of the second wiring layer (240).
As taught by Lee, one of ordinary skill in the art would utilize & modify the above teaching to obtain a first electronic component disposed on the cavity and the first opening and connected to the wiring pattern; and a second electronic component disposed on the second opening and connected to the at least a portion of the second wiring layer as claimed, because it aids in facilitating interconnection & achieving a desired semiconductor package that has a smaller size.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lee in combination with Keesu due to above reason.
Re claim 13, in combination cited above, Lee teaches, Fig. 9, [0050], a third insulating layer (220) disposed on a lower surface of the first insulating layer (210); a third wiring layer (232) disposed on a lower surface of the third insulating layer (220); and a third via layer (224) disposed within the third insulating layer (220) and connecting the third wiring layer (232) to the plurality of first wiring layers (212).
Re claim 14, in combination cited above, Lee teaches, Fig, 9, a second resist layer (320) disposed on the lower surface of the third insulating layer (220) and including a third opening exposing at least a portion of the third wiring layer (232).
6. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Keesu as modified by Lee as applied to claims 1 & 8-11 above, and further in view of Kwak et al. (US 2008/0272469).
The teachings of Keesu/Lee have been discussed above.
Re claim 12, in combination cited above, Lee teaches, Fig. 9, [0125], a molding material (sealing member 900) covering the first and second electronic components.
Keesu/Lee does not explicitly teach a metal layer disposed on an outer surface of the molding material.
Kwak teaches, Fig. 1, [0020], a metal layer (140) disposed on an outer surface of the molding material (150).
As taught by Kwak, one of ordinary skill in the art would utilize & modify the above teaching to obtain a metal layer disposed on an outer surface of the molding material, because it aids in achieving a package provided with shielding electromagnetic wave with small volume.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kwak in combination with Keesu/Lee due to above reason.
7. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Sakurai et al. (US 2012/0081864).
Re claim 15, Tsai teaches, under BRI, Figs. 1-2, [0021, 0023, 0033], a printed circuit board comprising:
-a first insulating layer (36);
-a wiring pattern (123) disposed in an upper side of the first insulating layer (36);
-a second insulating layer (14, 26, 28) disposed on and being in contact (via 12) with an upper surface of the first insulating layer (36) and having a cavity (24) exposing the wiring pattern (123); and
-an insulating pattern (12) disposed along a wall surface of the cavity (24), at least partially buried in the second insulating layer (14, 26, 28).
Note: in contact # directly/physically contact.
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Tsai does not explicitly teach including a thermosetting resist material.
Sakurai teaches including a thermosetting resist material [0031].
As taught by Sakurai, one of ordinary skill in the art would utilize the above teaching to obtain thermosetting resist material as claimed, because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Sakurai in combination with Tsai due to above reason.
Response to Arguments
8. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Applicant submits “Keesu does not disclose, among other things, “a second insulating disposed on and being in contact with an upper surface of the first insulating layer…”.
The examiner respectfully disagrees.
Under BRI, Keesu teach a second insulating (30) disposed on and being in contact (via 20) with an upper surface of the first insulating layer (10). Since the claim does not limit or exclude any intervene layers between first/second insulating layer, hence, given a broadest reasonable interpretation, Keesu meets the claimed invention. Similar reason applied to Tsai’s Fig. 2, and Tsai teaches a second insulating (14, 26, 28) disposed on and being in contact (via 12) with an upper surface of the first insulating layer (36).
Applicant submits, claim 17, “Keesu and Tsai each do not disclose “wherein the insulating pattern includes on side surface…and the another side surface of the insulating pattern is covered by the second insulating layer”.
The examiner respectfully disagrees.
Shown in Fig. 1, Keesu teaches the insulating pattern (40) includes one side surface (left side) and another side surface (right side) opposing each other, and at least a portion of the one side surface of insulating pattern (40) is exposed to the cavity (C) and the another side surface of insulating pattern (40) is covered by the second insulating layer (20). Hence, given a broadest reasonable interpretation, Keesu meets the claimed invention.
Details included in the above rejection.
Conclusion
9. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 7/12/26
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