Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of the amendment filed April 22, 2026, in which: claim(s) 10, 14-15, 18, 21, 24, and 27-29 is/are amended; claim(s) 1-9 and 11 is/are cancelled; new claim(s) 30 is/are added; and the rejection of the claims is traversed. Claim(s) 10 and 12-30 is/are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant's arguments filed April 22, 2026, with respect to the rejection(s) of claim(s) 16-20 have been fully considered but they are not persuasive.
In response to Applicant’s argument that Chung requires that the bonding bump contacts the annular ring, the examiner recognizes and previously stated that Chung does not explicitly teach the limitation “each bonding bump bonds to a corresponding bonding pad but not to the annular ring encircling the corresponding bonding pad.” The rejection, as previously set forth, relies solely upon Chen, W. to disclose, in Fig. 9 and associated text, attaching bumps to the bonding pads wherein each bump (132) bonds to a corresponding bonding pad (128’) but not to the annular ring (128) encircling the corresponding bonding pad.
Additionally, in response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chung and Hsu to provide semiconductor devices connected by bonding bumps as disclosed by Hsu because it is a suitable means to integrate the first semiconductor device into a package, to provide it with a redistribution layer, and/or to enhance the mechanical strength of the first semiconductor device (Hsu [0060]-[0062]). Additionally, it would have further been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Chung, Hsu, and Chen, W. to provide bumps bonded to the bond pad and not to an annular ring because the spacing between the solder bump and annular ring contains, for example, solder flux within the UBM, preventing damage to other features (Chen, W. [0011]).
Finally, in response to applicant’s argument that the proposed modification of Chung by Chen W. would render the prior art unsatisfactory for its original purpose, it can be seen from Chung Fig. 1 and 17 and associated text that, while embodiments featuring more than one outer ring of UBM 150, the benefits of the invention – that the adhesion between conductive ball 160 and UBM 150 is increased by a first locking portion 162 – can be realized with a single annular ring (Chung [0033]). Furthermore, as described supra, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the invention of Chung with the solder bump of Chen, W. not being on the annular ring because the spacing between the solder bump and annular ring contains, for example, solder flux within the UBM, preventing damage to other features (Chen, W. [0011]). It can be seen from Chen, W. Fig. 10A and associated text that this advantage can be realized even in embodiments wherein polymer layer 126 is in trench 130, as would be the case in the combined structure. An example of a structure combining the features of both Chung and Chen, W. without rendering either invention unsatisfactory for its original purpose includes an inner annular ring and pocket around a bond pad provided for improved adhesion in addition to portion(s) of an at least one polymer annular structure of the photoresist remaining between the bond pad and at least one outer annular ring, corresponding to the annular ring and annular structure claimed, wherein the bonding bump is not bonded to the outer annular ring(s) to further enable, for example, the containment of solder flux and protection of other features.
Applicant’s arguments with respect to the rejection(s) of claim(s) 10, 12-15, and 21-29 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chung et al. (US 20210257325 A1, hereinafter C1), and further in view of and Zhu et al. (CN 101728347 A, hereinafter Z1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10, 13, 21, 22, 23, 26, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US 20210257325 A1, hereinafter C1), and further in view of Zhu et al. (CN 101728347 A, hereinafter Z1).
Regarding claim 10, C1 discloses in C1 FIG. 5-6, 10, 18, and 20 and associated text, a method of manufacturing a semiconductor package comprising:
forming an under-bump metallization, including disposing a polymer on a substrate (FIG. 5, element 180; col 5, lines 7-8, photoresist is disposed over a substrate, photoresist being a specific kind of polymer);
that polymer layer being patterned (FIG. 5, elements 182 and 184; col 5 lines 9-12); and
forming a bonding pad and a guard ring on the patterned polymer layer, the guard ring including an annular ring encircling the bonding pad and a connector ring connecting between the bonding pad and the annular ring (FIG. 6, elements 150 and 172; col 5, lines 15-28, seed layer 172 is exposed to annular openings 182 and 184, thus connecting to the bonding pad and annular ring 150), the guard ring forming an annular pocket encircling the bonding pad, the annular pocket being filled with a portion of the patterned polymer layer (FIG. 6, please see attached figure);
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forming a redistribution layer comprising a plurality of metallization layers embedded in intermetal dielectric material, the metallization layers of the redistribution layer electrically connecting a semiconductor die with the under-bump metallization (FIG. 18, elements 350 (semiconductor die), 123 (redistribution layer), and 160 (conductive ball mounted on under-bump metallization) redistribution layer includes a plurality of dielectric and metal layers connecting the semiconductor die to UBM, please see attached figure);
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attaching a second component comprising a semiconductor die or semiconductor package to the under-bump metallization (RDL 370, corresponding to the under-bump metallization as interpreted above because it has the same structures as those in C1 FIG. 10 (C1 [0097]), is attached to semiconductor package 400).
C1 does not explicitly disclose with the annular pocket filled with the portion of the patterned polymer layer, attaching the second component to the under-bump metallization.
However, in the same field of endeavor, Z1 discloses in Z1 Fig. 6 and 19 and associated text with the annular pocket filled with the portion of the patterned polymer layer, attaching the second component to the under-bump metallization (an annular pocket, corresponding to main opening 22 and auxiliary opening 21, is filled with stress buffer layer 40, a polymer (Z1 [0047]), when attaching substrate 90, a second component).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of manufacturing a semiconductor package of C1 with the inclusion of the annular pocket filled with polymer during bonding disclosed by Z1 to provide bonded packages with a mechanical locking effect that prevents a crack from expanding and improves reliability of the package (Z1 [0023]). As explained supra, with respect to the combination of C1 with a similar feature of C2, it is possible to combine this feature of Z1 with the method of C1 without rendering the invention unsatisfactory for C1’s intended purpose.
Regarding claim 13, C1, as modified by Z1 further teaches forming the bonding pad and guard ring by copper plating (C1 col 4, lines 30-35, seed layer 172 may be copper and may be used in a plating process for forming the UBM 150, inherently a copper plating process by the composition of the seed layer).
Regarding claim 21, C1, as modified by Z1 further teaches the method of claim 10, wherein the portion of the patterned polymer layer filling the annular pocket is bounded by the bonding pad, guard ring, and connector ring (C1 FIG 6., please see attached figure).
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Regarding claim 22, C1, as modified by Z1 further teaches
the guard ring further includes a second annular ring encircling the annular ring, the connector ring further connecting between the annular ring and second annular ring (C1 FIG. 14 element 150a; col 7, line 48 through col 8, line 6, the openings 194 and 196 may be annular, resulting in annular rings encircling a bonding pad after copper plating of seed layer 172, please see attached figure); and
a second annular pocket is formed between the annular ring and the second annular ring, the second annular ring being filled with a second portion of the patterned polymer layer (C1 FIG. 14, please see attached figure).
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Regarding claim 23, C1, as modified by Z1 further teaches the second portion of the patterned polymer layer filling the second annular pocket is bounded by the annular ring, second annular ring, and connector ring (C1 FIG 14, please see the figure attached above).
Regarding claim 26, C1, as modified by Z1 further teaches the bonding pad, annular ring, and connector ring each comprise copper, aluminum, a copper alloy, or an aluminum alloy (paragraph [0034], lines 6-10, C1 discloses a process of forming the bonding pad, connector ring, and annular ring using plating on a copper seed layer, inherently making the guard ring and bonding pad therein copper or an alloy thereof). Notably, aluminum and aluminum alloys are also well known in the art for their use in under-bump metallizations.
Regarding claim 28, C1 discloses in C1 FIG. 5-6, 10, 18, and 20 and associated text a method of manufacturing a semiconductor package comprising:
forming an under-bump metallization, including disposing a polymer on a substrate (FIG. 5, element 180; col 5, lines 7-8);
that polymer layer being patterned to have openings (FIG. 5, elements 182 and 184; col 5 lines 9-12); and
forming a bonding pad on the patterned polymer layer, the bonding pad surrounded by an isolated portion of the patterned polymer layer that is isolated from a remainder of the patterned polymer layer (FIG. 6, please see attached figure); and
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forming a redistribution layer comprising a plurality of metallization layers embedded in intermetal dielectric material, the metallization layers of the redistribution layer electrically connecting a semiconductor die with the under-bump metallization (FIG. 18, please see attached figure); and
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attaching a second component comprising a semiconductor die or semiconductor package to the under-bump metallization (RDL 370, corresponding to the under-bump metallization as interpreted above because it has the same structures as those in C1 FIG. 10 (C1 [0097]), is attached to semiconductor package 400).
C1 does not explicitly disclose with the isolated portion of the patterned polymer layer in place, attaching the second component to the under-bump metallization.
However, in the same field of endeavor, Z1 discloses in Z1 Fig. 6 and 19 and associated text with the isolated portion of the patterned polymer layer in place, attaching the second component to the under-bump metallization (an annular pocket, corresponding to main opening 22 and auxiliary opening 21, is filled with stress buffer layer 40, a polymer (Z1 [0047]), when attaching substrate 90, a second component).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of manufacturing a semiconductor package of C1 with the inclusion of the annular pocket filled with polymer during bonding disclosed by Z1 to provide bonded packages with a mechanical locking effect that prevents a crack from expanding and improves reliability of the package (Z1 [0023]). As explained supra, it is possible to combine this feature of Z1 with the method of C1 without rendering the invention unsatisfactory for C1’s intended purpose.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over C1, and further in view of Z1.
Regarding claim 24, C1, as modified by Z1, teaches the method of claim 10. C1, as modified by Z1, does not explicitly teach that the annulus of the annular pocket has a width between 30 and 40 microns. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to try various ranges of annular pocket width to optimize the under-bump metallization surface area for packing density or contact surface properties such as durability, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Claim(s) 12 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over C1, and further in view of Z1 and Chen, Wei-Yu et al. (US 20170005052 A1, hereinafter C2).
Regarding claim 12, C1, as modified by Z1, teaches the method of claim 10. C1, as modified by Z1, does not explicitly teach that patterning the polymer layer is performed through a photolithography process. However, in the same field of endeavor C2 teaches that patterning the polymer layer (126) is performed through a photolithographic process (paragraph [0032]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of C1, as modified by Z1, and C2 to provide a repeatable and precise method of patterning the polymer layer.
Regarding claim 25, C1, as modified by Z1, teaches the method of claim 24, but does not explicitly teach that the annulus of the annular ring has a width between 10 microns and 40 microns inclusive. However, in the same field of endeavor, C2 teaches an annular ring width of 10 microns to 20 microns (C2 Fig. 6B, element W7; col 7, lines 21-22). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of C1, as modified by Z1, and C2 to try various ranges of annular pocket width including those which are known and industrially tested, as with the range taught by C2, to optimize the under-bump metallization surface area for packing density or contact surface properties such as durability, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Claim(s) 15, 27, and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over C1, and further in view of Z1 and Hsu et al. (US 20180151495 A1, hereinafter H1).
Regarding claim 15, C1, as modified by Z1, discloses in C1 FIG. 20 and associated text the method of claim 10, wherein: the attaching uses a solder bump that is disposed between the second component and the bonding pad (conductive bumps 460 are solder balls (C1 [0086])), and is bonded to the bonding pad during the attaching (conductive bumps 460 are bonded to RDL 370, which has structures substantially the same as those in C1 FIG. 10 (C1 [0097]), which would include the bonding pad as interpreted above). C1, as modified by Z1, does not explicitly teach; and the method further comprises, after the attaching, disposing underfill material between the second component and the under-bump metallization.
However, in the same field of endeavor, H1 teaches in FIG. 2 with associated text after the attaching, disposing underfill material (UF) between the second component and the under-bump metallization.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of C1, as modified by Z1, and H1 to provide combined semiconductor packages with adhesion and protection from foreign contaminants improved by the underfill.
Regarding claim 29, C1, as modified by Z1, teaches in C1 FIG. 20 and associated text the method of claim 28, wherein: the attaching uses a solder bump that is disposed between the second component and the bonding pad (conductive bumps 460 are solder balls (C1 [0086])), and is bonded to the bonding pad during the attaching (conductive bumps 460 are bonded to RDL 370, which has structures substantially the same as those in C1 FIG. 10 (C1 [0097]), which would include the bonding pad as interpreted above). C1, as modified by Z1, does not explicitly teach; and the method further comprises, after the attaching, disposing underfill material between the second component and the under-bump metallization.
However, in the same field of endeavor, H1 teaches in FIG. 2 with associated text after the attaching, disposing underfill material (UF) between the second component and the under-bump metallization.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of C1, as modified by Z1, and H1 to provide combined semiconductor packages with adhesion and protection from foreign contaminants improved by the underfill.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over C1, and further in view of C2. and H1.
Regarding claim 16, C1 teaches in C1 FIG. 3-6 and associated text a method of manufacturing a semiconductor package, the method comprising: forming an under-bump metallization (150, 172) on a surface of a first semiconductor component (110), the under-bump metallization including a set of bonding pads (center portion of 150) each encircled by a guard ring comprising an annular ring (outer portions of 150) encircling the bonding pad and a connector ring (172) connecting between the bonding pad and the annular ring, wherein an annular structure comprising a polymer material is located between the bonding pad and the annular ring (portion of 180 in the gaps between portions of 150). C1 does not explicitly teach bonding a second semiconductor component to the surface of the first semiconductor component using bonding bumps that bond to the bonding pads wherein each bonding bump bonds to a corresponding bonding pad but not to the annular ring encircling the corresponding bonding pad.
However, in the same field of endeavor, H1 teaches in FIG. 2 bonding a second semiconductor (210) component to the surface of the first semiconductor component (110) using bonding bumps (162,164) that bond to the bonding pads (PAD) wherein each bump bonds to a corresponding bonding pad. H1 does not explicitly teach that the bonding bumps do not bond to the annular ring encircling the corresponding bonding pad.
C2 teaches in Fig. 9 and associated text attaching bumps to the bonding pads wherein each bump (132) bonds to a corresponding bonding pad (128’) but not to the annular ring (128) encircling the corresponding bonding pad.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of C1 and H1 to provide semiconductor devices connected by bonding bumps as disclosed by H1 because it is a suitable means to integrate the first semiconductor device into a package, to provide it with a redistribution layer, and/or to enhance the mechanical strength of the first semiconductor device (H1 [0060]-[0062]). Additionally, it would have further been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of C1, H1, and C2. to provide bumps bonded to the bond pad and not to an annular ring because the spacing between the solder bump and annular ring contains, for example, solder flux within the UBM, preventing damage to other features (C2 [0011]). As explained supra, it is possible to combine this feature of C2 with the method of C1 without rendering the invention unsatisfactory for C1’s intended purpose.
Regarding claim 17, C1, as modified by H1 and C2, teaches in H1 Fig. 9 and associated text disposing underfill material (UF) between the second semiconductor component (210) and the surface of the first semiconductor component (110), the underfill material at least partially surrounding the bonding bumps (162, 164).
Regarding claim 18, C1, as modified by H1 and C2, further teaches in C1 FIG. 14 and associated text each bonding pad is further encircled by a second guard ring of an electrically conductive material, the second guard ring comprising a second annular ring encircling the annular ring and the connector ring further connecting between the annular ring and the second annular ring (please see attached figure).
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Regarding claim 19, C1, as modified by H1 and C2, further teaches the bonding pad and the guard ring are formed by copper plating (C1 col 4, lines 30-35, seed layer 172 may be copper and may be used in a plating process for forming the UBM 150, inherently a copper plating process by the composition of the seed layer).
Regarding claim 20, C1, as modified by H1 and C2, further teaches in C1 FIG. 6 and associated text the guard ring forms an annular pocket (gaps between portions of 150) encircling the bonding pad, the annular pocket being filled with the annular structure (180).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over C1, and further in view of Z1, H1, and Chen, Yu-Feng et al. (US 20160020186 A1, hereinafter C3).
Regarding claim 14, C1, as modified by Z1, teaches the method of claim 10, but does not explicitly teach prior to the attaching, depositing pre-solder on the bonding pad, after depositing the pre-solder, performing the attaching of the second component comprising a semiconductor die to the under-bump metallization using a solder bump that attaches to the bonding pad via the pre-solder, the attaching leaving solder flux residue on the solder bump after the attaching is complete; and disposing underfill material between the second component and the under- bump metallization.
However, in the same field of endeavor, C3 teaches in FIG. 10 and associated text prior to the attaching, depositing pre-solder on the bonding pad (solder bump 118 on UBM 114 includes a pre-solder (C3 [0027])), after depositing the pre-solder, attaching a second component comprising a semiconductor die (200) to the under-bump metallization (114) using a solder bump (206) that attaches to the bonding pad via the pre-solder, the attaching leaving solder flux residue on the solder bump after the attaching is complete (col 9, lines 31-34, the attaching process may include flux application and residue). C3 does not teach after the attaching, disposing underfill material between the second component and the under-bump metallization.
However, in the same field of endeavor, H1 teaches in FIG. 2 after the attaching, disposing underfill material (UF) between the second component (210) and the under-bump metallization (PAD).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of C1, as modified by Z1, with H1 and C3. to provide attached semiconductor packages with improved adhesion and durability from pre-solder and solder flux application on the bonding bumps and/or pads and underfill between packages to seal the electrical connections and protect against external contaminants.
Claims 27 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over C1, and further in view of Z1, H1, and Ito et al. (US 20110193224 A1, hereinafter I1).
Regarding claim 27, C1, as modified by Z1 and H1, discloses in Z1 FIG. 19 and associated text, the method of claim 15 wherein the method further comprises: during the disposing of the underfill material between the second component and the under-bump metallization, a crack in the underfill material (a crack forms in the underfill 91 and stress buffer layer 40 (Z1 [0062])). C1, as modified by Z1 and H1, does not explicitly teach blocking, by the guard ring, a crack propagating into the portion of the patterned polymer layer filling the annular pocket from penetrating into the redistribution layer.
However, in the same field of endeavor, I1 discloses in I1 FIG. 1-2 and associated text blocking, by the guard ring, a crack propagating into the portion of the patterned polymer layer filling the annular pocket from penetrating into the redistribution layer (a crack propagating through surface-protective film 5, corresponding to the patterned polymer layer filling the annular pocket is terminated at the slit 5b (I1 [0031])). Though not shown, I1 further discloses an embodiment wherein a portion of the bump electrode 6 is formed in opening 5a/slit 5b (I1 [0050]), which may correspond more closely to the guard ring claimed, showing that the function of the slit 5b described is compatible with embodiments according to the combined references.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package of C1, as modified by Z1 and H1, with the function of an analogous guard ring disclosed by I1 to provide protection of the redistribution layer from cracks because I1 discloses that the combined structure is capable of doing so (I1 [0031]).
Regarding dependent claim 30, C1, as modified by Z1 and H1, discloses in Z1 FIG. 19 and associated text, the method of claim 29, further comprising: propagation of a crack in the underfill material (a crack forms in the underfill 91 and stress buffer layer 40 (Z1 [0062])). C1, as modified by Z1 and H1, does not explicitly teach trapping propagation of a crack in the underfill material in the isolated portion of the patterned polymer.
However, in the same field of endeavor, I1 discloses in I1 FIG. 1-2 and associated text trapping propagation of a crack in the underfill material in the isolated portion of the patterned polymer (a crack propagating through surface-protective film 5, corresponding to the patterned polymer layer filling the annular pocket, is terminated at the slit 5b (I1 [0031])). Though not shown, I1 further discloses an embodiment wherein a portion of the bump electrode 6 is formed in opening 5a/slit 5b, which may correspond more closely to the guard ring claimed, showing that the function of the slit 5b described is compatible with embodiments according to the combined references.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor package of C1, as modified by Z1 and H1, with the function of an analogous guard ring disclosed by I1 to provide protection of the redistribution layer from cracks because I1 discloses that the combined structure is capable of doing so (I1 [0031]).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
US-20210151369-A1, a prior patent application disclosing a semiconductor package with an under-bump metallization including a pad with a center portion and a peripheral portion.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571)272-9559. The examiner can normally be reached Mon - Thu: 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/ Examiner, Art Unit 2897
/CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897
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