Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 12 are rejected under 35 U.S.C. 103 as being unpatentable over Jang ( Pub. No. US 20200220018 A1 ), hereinafter Jang, in view of Chu ( Pub. No. US 20220069135 A1 ), hereinafter Chu.
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Regarding Independent Claim 1 ( Original ), Jang teaches a semiconductor device comprising:
a substrate ( Jang, FIG. 2, 101; [0022], substrate 101 );
an active region ( Jang, FIG. 2, 105; [0022], active region 105 ) extending in a first direction ( Jang, FIG. 2, x direction ) on the substrate ( Jang, FIG. 2, 101 );
a plurality of semiconductor layers ( Jang, FIG. 2, 140, 141, 142, 143; [0022], channel structures 140 including a plurality of channel layers 141, 142, and 143 ) spaced apart from each other in a vertical direction ( Jang, FIG. 2, z direction ) on the active region ( Jang, FIG. 2, 105 ), the plurality of semiconductor layers comprising a lower semiconductor layer ( Jang, FIG. 2, 141 ) and an upper semiconductor layer ( Jang, FIG. 2, 143 ) on the lower semiconductor layer ( Jang, FIG. 2, 141 );
a gate structure ( Jang, FIG. 2,160; [0022], gate structures 160 ) extending in a second direction ( Jang, FIG. 2, y direction ) on the substrate ( Jang, FIG. 2, 101 ) and intersecting the active region ( Jang, FIG. 2, 105 ) and the plurality of semiconductor layers ( Jang, FIG. 2, 140, 141, 142, 143 ), the gate structure ( Jang, FIG. 2,160 ) surrounding the plurality of semiconductor layers ( Jang, FIG. 2, 140, 141, 142, 143 ); and
a source/drain region ( Jang, FIG. 2, 150; [0022], source/drain regions 150 ) provided on the active region ( Jang, FIG. 2, 105 ) on at least one side adjacent to the gate structure ( Jang, FIG. 2,160 ) and contacting the plurality of semiconductor layers ( Jang, FIG. 2, 140, 141, 142, 143 ),
wherein the source/drain region ( Jang, FIG. 2, 150 ) comprises first epitaxial layers ( Jang, FIG. 2, 152; [0029], first epitaxial layers 152 ) and a second epitaxial layer ( Jang, FIG. 2, 154; [0029], a second epitaxial layer 154 ),
wherein the first epitaxial layers ( Jang, FIG. 2, 152 ) comprise a first layer ( Jang, FIG. 2, 152A, [0030], first layers 152A ) contacting a side surface of the lower semiconductor layer ( Jang, FIG. 2, 141 ) in the first direction ( Jang, FIG. 2, x direction ), and a second layer ( Jang, FIG. 2, 152B; [0030], second layers 152B ) provided on and contacting the active region ( Jang, FIG. 2, 105 ),
wherein the second epitaxial layer ( Jang, FIG. 2, 154 ) contacts ( Jang, [0035], damage to a film caused by an ion implantation process when the first epitaxial layer 152 and the second epitaxial layer 154 are formed as doping regions may be avoided; [0065], The first epitaxial layer 152c may be disposed as a single layer covering a surface on which the third epitaxial layers 151 are not in contact with the first to third channel layers 141, 142, and 143 ) a side surface of the upper semiconductor layer ( Jang, FIG. 2, 143 ) in the first direction ( Jang, FIG. 2, x direction ), and
wherein the first layer ( Jang, FIG. 2, 152A ) is between the second epitaxial layer ( Jang, FIG. 2, 154 ) and the side surface of the lower semiconductor layer ( Jang, FIG. 2, 141 ).
Jang did not explicitly to disclose:
wherein the second epitaxial layer contacts a side surface of the upper semiconductor layer in the first direction,
However, Chu teaches:
wherein the second epitaxial layer contacts a side surface of the upper semiconductor layer in the first direction ( Chu, FIG. 19B, 2360B contacts a side surface of 2080; [0011], while a doping concentration in the source/drain feature may be increased to lower the resistance, a greater dopant concentration may lead to more defects at the interface between the source/drain feature and the channel members; [0012], The first epitaxial layer serves as a transition layer to interface the channel member and to reduce interfacial defects; [0029], As a result, the second substrate portion 2360B merges with the second channel sidewall portions 2360T in contact with the bottommost channel layer 208 ),
Jang and Chu are both considered to be analogous to the claimed invention because they are forming a gate structure wrapping around each of the plurality of channel members, and a source/drain feature. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jang ( FIG. 2, drain epitaxial first layers 152A contact channel 141; [0035], damage to a film caused by an ion implantation process when the first epitaxial layer 152 and the second epitaxial layer 154 are formed as doping regions may be avoided ), to incorporate the teachings of Chu ( FIG. 19B, second substrate portion 2360B contacts channel 2080 ), to reduce the defects at the interface between channel and source/drain , and implement wherein the second epitaxial layer ( Jang, FIG. 2, 154 ) contacts a side surface of the upper semiconductor layer ( Jang, FIG. 2, 143, by avoiding the form of doping region152A ) in the first direction. Doing so would provide specific contacts between channel and source/drain, and therefore the defects at the interface between channel and source/drain can be reduced.
Regarding Claim 2 ( Original ), Jang and Chu teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Jang further teaches:
wherein each of the first epitaxial layers ( Jang, FIG. 2, 152 ) has a first impurity concentration ( Jang, FIG. 4A, C1; [0049], first epitaxial layer 152 may include impurities in a first concentration C1 ), and
wherein the second epitaxial layer ( Jang, FIG. 2, 154 ) has a second impurity concentration ( Jang, FIG. 4A, C2; [0049], second epitaxial layer 154 may include impurities in a second concentration C2 ) that is higher than the first impurity concentration ( Jang, FIG. 4A, [0049], second concentration C2 higher than the first concentration C1 ).
Regarding Claim 3 ( Original ), Jang and Chu teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Jang further teaches: further comprising:
inner spacer layers ( Jang, FIG. 2, 130; 0022), internal spacer layers 130 ) provided on opposite sides adjacent to the gate structure ( Jang, FIG. 2, 160 ) in the first direction ( Jang, FIG. 2, x direction ) on a lower surface of each of the plurality of semiconductor layers ( Jang, FIG. 2, 140, 141, 142, 143 ) and vertically overlapping the plurality of semiconductor layers ( Jang, FIG. 2, 140, 141, 142, 143 ).
Regarding Claim 4 ( Original ), Jang and Chu teach the semiconductor device as claimed in claim 3, on which this claim is dependent, Jang further teaches:
wherein the first layer ( Jang, FIG. 2, 152A ) protrudes more towards the second epitaxial layer ( Jang, FIG. 2, 154 ) as compared to the inner spacer layers ( Jang, FIG. 2, 130 ).
Regarding Claim 5 ( Original ), Jang and Chu teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Jang further teaches:
wherein at least a portion of the first layer ( Jang, FIG. 2, 152A ) of the first epitaxial layers ( Jang, FIG. 2, 152 ) vertically overlaps the second epitaxial layer ( Jang, FIG. 2, 154 ).
Regarding Claim 6 ( Original ), Jang and Chu teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Jang further teaches:
wherein the upper semiconductor layer ( Jang, FIG. 2, 143 ) has a central region and an outer region ( Jang, [0028], In example embodiment, the first to third channel layers 141, 142, and 143 may include an impurity region disposed in a region adjacent to the source/drain region 150 ) on an outer side of the central region in the first direction, and the outer region is different from the central region.
Regarding Claim 7 ( Original ), Jang and Chu teach the semiconductor device as claimed in claim 6, on which this claim is dependent, Jang further teaches:
wherein the central region lacks impurities ( Jang, [0071], the plurality of channel layers 141, 142, and 143 may or may not include impurities ), and
wherein the outer region comprises impurities ( Jang, [0028], In example embodiment, the first to third channel layers 141, 142, and 143 may include an impurity region disposed in a region adjacent to the source/drain region 150 ).
Regarding Claim 8 ( Original ), Jang and Chu teach the semiconductor device as claimed in claim 7, on which this claim is dependent, Jang further teaches:
wherein the impurities in the outer region comprise at least one of silicon (Si), phosphorus (P), or arsenic (As) ( Jang, [0032], For example, the first epitaxial layer 152 may include n-type impurities such as arsenic (As) and/or phosphorus (P). The first epitaxial layer 152 may be, for example, a SiAs layer, a SiP layer, a SiPC layer, a SiC layer, a SiPAs layer, or a SiGeP layer ).
Regarding Claim 9 ( Original ), Jang and Chu teach the semiconductor device as claimed in claim 6, on which this claim is dependent, Jang further teaches:
wherein a material of the outer region ( Jang, [0028], In example embodiment, the first to third channel layers 141, 142, and 143 may include an impurity region disposed in a region adjacent to the source/drain region 150 ) has a crystallinity that is lower than a crystallinity of a material of the central region ( Jang, [0071], the plurality of channel layers 141, 142, and 143 may or may not include impurities ).
Regarding Claim 10 ( Original ), Jang and Chu teach the semiconductor device as claimed in claim 9, on which this claim is dependent, Jang further teaches:
wherein the material of the central region comprises single-crystalline silicon ( Jang, [0071], the plurality of channel layers 141, 142, and 143 may or may not include impurities ), and
wherein the material of the outer region comprises amorphous silicon ( Jang, [0035], Thus, damage to a film caused by an ion implantation process when the first epitaxial layer 152 and the second epitaxial layer 154 are formed as doping regions may be avoided ).
Regarding Claim 11 ( Original ), Jang and Chu teach the semiconductor device as claimed in claim 6, on which this claim is dependent, Jang further teaches:
wherein the outer region ( Jang, [0035], Thus, damage to a film caused by an ion implantation process when the first epitaxial layer 152 and the second epitaxial layer 154 are formed as doping regions may be avoided ) has a shape that is convex toward the central region ( Jang, [0071], the plurality of channel layers 141, 142, and 143 may or may not include impurities ).
Regarding Claim 12 ( Original ), Jang and Chu teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Jang further teaches:
wherein the lower semiconductor layer ( Jang, FIG. 2, 141, 142 ) comprises a first semiconductor layer ( Jang, FIG. 2, 141 ) and a second semiconductor layer ( Jang, FIG. 2, 142 ) stacked on the first semiconductor layer ( Jang, FIG. 2, 141 ),
wherein the first layer ( Jang, FIG. 2, 152A ) comprises a first lower layer ( Jang, FIG. 2, 152A contacting 141 ) contacting a side surface of the first semiconductor layer ( Jang, FIG. 2, 141 ), and a first upper layer ( Jang, FIG. 2, 152A contacting 142 ) contacting a side surface of the second semiconductor layer ( Jang, FIG. 2, 142 ), and
wherein a first distance from a vertical central axis of the source/drain region ( Jang, FIG. 2, 150 ) in the first direction ( Jang, FIG. 2, x direction ) to the first lower layer ( Jang, FIG. 2, 152A contacting 141 ), a second distance from the vertical central axis to the first upper layer ( Jang, FIG. 2, 152A contacting 142 ).
Jang does not explicitly disclose:
wherein a first distance from a vertical central axis of the source/drain region in the first direction to the first lower layer is smaller than a second distance from the vertical central axis to the first upper layer.
However, Jang teaches:
FIG. 8, [0062], a thickness of the first epitaxial layer 152b may not be uniform. The first epitaxial layer 152b may have a third maximum thickness T3 on side walls of the first to third channel layers 141, 142, and 143, and may have a fourth maximum thickness T4 greater than the third maximum thickness T3 at a lower portion.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jang ( FIG. 8, bottom T4 greater than sidewall T3 ), to get “sidewall T3 near bottom” greater than “sidewall T3 near top”, and “FIG. 9, third epitaxial layers 151 near bottom” greater than “FIG. 9, third epitaxial layers 151 near top”, to implement that wherein a first distance from a vertical central axis of the source/drain region in the first direction to the first lower layer (Jang, FIG. 9, third epitaxial layers 151 near bottom) is smaller than a second distance from the vertical central axis to the first upper layer (Jang, FIG. 9, third epitaxial layers 151 near top). Doing so would provide specific contacts between channel and source/drain, and therefore the defects at the interface between channel and source/drain can be reduced.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817