Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to communication filed 11/20/2025. Claims 1-20 are currently pending and claims 1, 8, and 15 are the independent claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
As per independent claim 1, it recites “One or more processors, comprising: circuitry to calculate a plurality of performance metrics estimating a change in a performance of a software program caused by replacing one or more memory operations with two or more candidate replacement memory operations from a set of candidate replacement memory operations; select a replacement memory operation based, at least in part, on the replacement memory operation having a lower cost than a second one of the two or more candidate replacement memory operations; and replace the one or more memory operations with the replacement memory operation.”
The limitations “calculate a plurality of performance metrics estimating a change in a performance of a software program caused by replacing one or more memory operations with two or more candidate replacement memory operations from a set of candidate replacement memory operations” and “select a replacement memory operation based, at least in part, on the replacement memory operation having a lower cost than a second one of the two or more candidate replacement memory operations”, as drafted, are function that, under broadest reasonable interpretation, recite functions that could reasonably be performed in the mind, including with the aid of pen and paper, but for the recitation of generic computer components, and as such recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the function through observation, evaluation, judgment, and/or opinion, or even with the aid of pen and paper. For example, a human may mentally/manually/with pen and paper/etc. judge/calculate/evaluate/analyze/predict/observe/etc. the effect of replacing memory operations with candidate replacement operations of a set of candidate replacement memory operations and judge/decide/determine/estimate/predict/etc. performance metrics corresponding to the judged/estimated/predicted/etc. effect, and may mentally/manually/with pen and paper/etc. judge/calculate/determine/observe/decide/etc. a cost of each candidate replacement memory operations and select/judge/decide/determine/etc. a candidate replacement operation having a lower cost than other candidate replacement operations to replace the memory operations. Thus, this limitation recites and falls within the “Mental Processes” grouping of abstract ideas.
This judicial exception is not integrated into a practical application. The claim recites the additional elements “One or more processors, comprising: circuitry to …”, and “replace the one or more memory operations with the replacement memory operation”. The additional elements “One or more processors, comprising: circuitry to” recites that high level/generic computer components/processors/circuitry are used to implement/perform/etc. the abstract idea/mental process, and as such amounts to no more than mere instructions to apply the exception using generic computer, and/or mere computer components. The additional elements “replace the one or more memory operations with the replacement memory operation”, with broadest reasonable interpretation, amounts to instructions perform/implement/output/etc. the judged/decided/selected/etc. operation/activity/etc. resulting from performing the abstract idea/mental process by merely updating data/replacing operations/etc., and as such is at best the equivalent of merely adding the words “apply it” to the judicial exception/abstract idea resulting in performing an insignificant extra solution activity of updating/changing/replacing/storing/etc. data/information/operations by updating/replacing data/memory operation/etc. and the courts have identified functions such as gathering, displaying, updating, transmitting and storing data as well-understood, routine, conventional activity, see MPEP 2106.05(d). Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f), 2106.05(g).
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to mere instructions to apply the exception using generic computer, and/or mere computer components, and the equivalent of merely adding the words “apply it” to the judicial exception/abstract idea resulting in performance of an insignificant extra solution activity of updating/storing/etc. of data/changing information/replacing memory operations/etc., and the courts have identified functions such as gathering, displaying, updating/modifying, transmitting, and storing data as well-understood, routine, conventional activity, thus do not amount to significantly more than the judicial exception. See MPEP 2106.05(d). The recitation of generic computer components to apply the judicial exception, and the equivalent of merely reciting “apply it” by performing an insignificant extra solution activity to perform/output/etc. the result of the abstract idea/mental process do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101.
As per claim 2, it incorporates the deficiencies of claim 1, upon which it depends, and further recites “…wherein the circuitry is to cause a compiler to select the replacement memory operation from the set of candidate replacement memory operations based, at least in part, on a plurality of performance metrics associated with the set of candidate replacement memory operations” which, conceptually, with broadest reasonable interpretation, provides further clarification as to the performance of the performance of the abstract idea/mental process/the making of the selection/judgment/decision/etc., and as such does not integrate the abstract idea/mental process into a practical application and is not significantly more than the abstract idea/mental process. Therefore, claim 2 fails to correct the deficiencies of claim 1, and is rejected for similar reasoning as claim 1, above.
As per claim 3, it incorporates the deficiencies of claim 1, upon which it depends, and further recites “…wherein the replacement memory operation is to reduce a demand for registers during performance of the software program” which, conceptually, with broadest reasonable interpretation, provides further clarification as to the performance of the performance of the abstract idea/mental process/estimation and selection/etc., and as such does not integrate the abstract idea/mental process into a practical application and is not significantly more than the abstract idea/mental process. Therefore, claim 3 fails to correct the deficiencies of claim 1, and is rejected for similar reasoning as claim 1, above.
As per claim 4, it incorporates the deficiencies of claim 1, upon which it depends, and further recites “…wherein the circuitry is to store information indicating one or more estimated performance metrics of the one or more memory operations” which, with broadest reasonable interpretation, merely recites that the high level/generic computer components/circuity are to perform an insignificant extra solution activity of storing data/storing information/storing indicating of estimated performance metrics with memory operations/etc., which does not integrate the abstract idea into a practical application and the courts have identified functions such as gathering, displaying, updating/modifying, transmitting, and storing data as well-understood, routine, conventional activity, thus do not amount to significantly more than the judicial exception. See MPEP 2106.05(d). Therefore, claim 4 fails to correct the deficiencies of claim 1, and is rejected for similar reasoning as claim 1, above.
As per claim 5, it incorporates the deficiencies of claim 1, upon which it depends, and further recites “…wherein the circuitry is to cause a compiler to use one or more heuristics to measure performance effects of replacing the one or more memory operations with the two or more candidate replacement memory operations” which, with broadest reasonable interpretation, merely recites that the high level/generic computer components/circuity and compiler/etc. are to perform an insignificant extra solution activity of gathering data/obtaining information/measure performance effects/etc., which does not integrate the abstract idea into a practical application and the courts have identified functions such as gathering, displaying, updating/modifying, transmitting, and storing data as well-understood, routine, conventional activity, thus do not amount to significantly more than the judicial exception. See MPEP 2106.05(d). Therefore, claim 5 fails to correct the deficiencies of claim 1, and is rejected for similar reasoning as claim 1, above.
As per claim 6, it incorporates the deficiencies of claim 1, upon which it depends, and further recites “…wherein the circuitry is further to replace the one or more memory operations with the replacement memory operation based, at least in part, on an indication of priority of the replacement memory operation” which, with broadest reasonable interpretation, merely recites further clarification as to the insignificant extra solution activity of updating/replacing/storing/etc. data/information/further clarification as to operations performed to apply the result of performing the abstract idea/apply the selected operation resulting from performing the abstract idea/etc. and the courts have identified functions such as gathering, displaying, updating/modifying, transmitting, and storing data as well-understood, routine, conventional activity, thus do not amount to significantly more than the judicial exception. See MPEP 2106.05(d). Therefore, claim 6 fails to correct the deficiencies of claim 1, and is rejected for similar reasoning as claim 1, above.
As per claim 7, it incorporates the deficiencies of claim 1, upon which it depends, and further recites “…wherein the plurality of performance metrics include runtime, power consumption, and memory requirements” which, conceptually, with broadest reasonable interpretation, provides further clarification as to the performance of the performance of the abstract idea/mental process/the making of the estimation/judgement/what is being estimated/judged/observed/etc., and as such does not integrate the abstract idea/mental process into a practical application and is not significantly more than the abstract idea/mental process. Therefore, claim 7 fails to correct the deficiencies of claim 1, and is rejected for similar reasoning as claim 1, above.
As per claims 8-9 and 11, they recite systems comprising one or more circuits having similar limitations to the one or more processors comprising circuitry of claims 1-2 and 4, respectively, and are therefore rejected for similar reasoning as claims 1-2 and 4, respectively, above.
As per claim 10, it incorporates the deficiencies of claim 8, upon which it depends, and further recites “…wherein the replacement memory operation is to reduce register pressure of one or more portions of the software program” which, conceptually, with broadest reasonable interpretation, provides further clarification as to the performance of the performance of the abstract idea/mental process/estimation and selection/etc., and as such does not integrate the abstract idea/mental process into a practical application and is not significantly more than the abstract idea/mental process. Therefore, claim 10 fails to correct the deficiencies of claim 8, and is rejected for similar reasoning as claim 8, above.
As per claim 12, it incorporates the deficiencies of claim 8, upon which it depends, and further recites “…wherein the one or more circuits are to cause one of the one or more memory operations within the software program to be automatically replaced by two or more replacement memory operations of different types” which, with broadest reasonable interpretation, merely recites further clarification as to the insignificant extra solution activity of updating/replacing/storing/etc. data/information/further clarification as to operations performed to apply the result of performing the abstract idea/apply the selected operation resulting from performing the abstract idea/etc. and the courts have identified functions such as gathering, displaying, updating/modifying, transmitting, and storing data as well-understood, routine, conventional activity, thus do not amount to significantly more than the judicial exception. See MPEP 2106.05(d). Therefore, claim 12 fails to correct the deficiencies of claim 8, and is rejected for similar reasoning as claim 8, above.
As per claim 13, it incorporates the deficiencies of claim 8, upon which it depends, and further recites “…wherein the one or more circuits are to store two or more replacement memory operations in a priority queue” which, with broadest reasonable interpretation, merely recites that the high level/generic computer components/circuity and queue/etc. are used to perform an insignificant extra solution activity of storing data/storing information/storing replacement memory operations in a queue/etc., which does not integrate the abstract idea into a practical application and the courts have identified functions such as gathering, displaying, updating/modifying, transmitting, and storing data as well-understood, routine, conventional activity, thus do not amount to significantly more than the judicial exception. See MPEP 2106.05(d). Therefore, claim 13 fails to correct the deficiencies of claim 8, and is rejected for similar reasoning as claim 8, above.
As per claim 14, it incorporates the deficiencies of claim 8, upon which it depends, and further recites “…wherein the one or more memory operations are associated with one or more portions of the software program” which, conceptually, with broadest reasonable interpretation, provides further clarification as to the performance of the performance of the abstract idea/mental process/etc., and as such does not integrate the abstract idea/mental process into a practical application and is not significantly more than the abstract idea/mental process. Therefore, claim 14 fails to correct the deficiencies of claim 8, and is rejected for similar reasoning as claim 8, above.
As per claim 15, it recites a method having similar limitations as the one or more processors of claim 1 and is therefore rejected for similar reasoning as claim 1 above.
As per claim 16, it incorporates the deficiencies of claim 15, upon which it depends, and further recites “…selecting the replacement memory operations is futher based, at least in part, on one or more threshold performance metric values” which, conceptually, with broadest reasonable interpretation, provides further clarification as to the performance of the abstract idea/mental process/the making of the selection/judgment/decision/etc., and as such does not integrate the abstract idea/mental process into a practical application and is not significantly more than the abstract idea/mental process. Therefore, claim 16 fails to correct the deficiencies of claim 15, and is rejected for similar reasoning as claim 15, above.
As per claim 17, it incorporates the deficiencies of claim 15, upon which it depends, and further recites “…wherein the replacement memory operation is to reduce register pressure of one or more portions of the software program prior to a register allocation phase of compilation” which, conceptually, with broadest reasonable interpretation, provides further clarification as to the performance of the performance of the abstract idea/mental process/estimation and selection/etc., and as such does not integrate the abstract idea/mental process into a practical application and is not significantly more than the abstract idea/mental process. Therefore, claim 17 fails to correct the deficiencies of claim 15, and is rejected for similar reasoning as claim 15, above.
As per claim 18, it incorporates the deficiencies of claim 15, upon which it depends, and further recites “…wherein the calculating is based, at least in part, on measuring a difference between the two or more candidate replacement memory operations” which, conceptually, with broadest reasonable interpretation, provides further clarification as to the performance of the performance of the abstract idea/mental process/judgement/analyzing/evaluation/comparing and selection/etc., and as such does not integrate the abstract idea/mental process into a practical application and is not significantly more than the abstract idea/mental process. Therefore, claim 18 fails to correct the deficiencies of claim 15, and is rejected for similar reasoning as claim 15, above.
As per claim 19, it incorporates the deficiencies of claim 15, upon which it depends, and further recites “…wherein the one or more memory operations are automatically replaced with the replacement memory operation based, at least in part, on a heterogeneous set of replacement memory operations” which, with broadest reasonable interpretation, merely recites further clarification as to the insignificant extra solution activity of updating/replacing/storing/etc. data/information/memory operations/further clarification as to operations performed to apply the result of performing the abstract idea/apply the selected operation resulting from performing the abstract idea/etc. and the courts have identified functions such as gathering, displaying, updating/modifying, transmitting, and storing data as well-understood, routine, conventional activity, thus do not amount to significantly more than the judicial exception. See MPEP 2106.05(d). Therefore, claim 19 fails to correct the deficiencies of claim 15, and is rejected for similar reasoning as claim 15, above.
As per claim 20, it incorporates the deficiencies of claim 15, upon which it depends, and further recites “…wherein the one or more memory operations are automatically replaced with the replacement memory operation based, at least in part, on selecting the replacement memory operation from a priority queue” which, conceptually, with broadest reasonable interpretation, provides further clarification as to the performance of the abstract idea/mental process/the making of the selection/judgment/decision/etc., and as such does not integrate the abstract idea/mental process into a practical application and is not significantly more than the abstract idea/mental process. Therefore, claim 20 fails to correct the deficiencies of claim 15, and is rejected for similar reasoning as claim 15, above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7-10, 12, 14-16, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bikshandi et al. (herein called Bikshandi) (US Patent 9,372,678 B2) and Gao et al. (herein called Gao) (US PG Pub. 2020/0293295 A1) in further view of Schuchman et al. (herein called Schuchman) (US PG Pub. 2016/0259628 A1).
As per claim 1, Bikshandi teaches: One or more processors, comprising: circuitry to
calculate a plurality of performance metrics estimating a change in a performance of a software program caused by replacing one or more memory operations with two or more candidate replacement memory operations (col.3 line 62-col. 4 line 20, col. 5 line 60-col. 6 line 10, col. 6 lines 18-30, code/source code/software/etc. (software program) includes executable statements/segments/etc. (operations within software program) such as loops which may be optimized/replaced/etc. based on whether or not loop with fit in memory/cache/etc. (as loops/statements/segments/etc. are included in code/software/etc. and have a memory size and are to fit/be stored in/etc. memory, they are memory operations within software program), and replacing input code segment/loop/etc. includes replacing the segment/loop with modified code/smaller blocks/loop tiles/replacing loop with a pair of nested loops/etc. which fit inside cache memory improving thereby improving performance by reducing bandwidth pressure (estimated performance metrics estimating change in performance of software caused by replacing memory operations with candidate replacement memory operations/fit inside cache memory/etc.), as such memory operations/input code segment/loop within a software program is automatically replaced by one or more replacement memory operations/pair of nested loops/loop tiles/smaller blocks/etc. based on performance metrics estimating a change in a performance of the software program caused by replacing the one or more memory operations with two or more candidate replacement memory operations/replacement code segments/pair of nested loops that fit inside cache memory/etc. thereby improving performance by reducing memory bandwidth pressure/etc.).).
While Bikshandi teaches optimizing code by replacing operations/statements/segments/loops/etc. of code/software/etc. with other operations/statements/segments/etc. based on performance metrics estimating/predicting/etc. a change in performance of the software program caused by replacing the operations/statements/segments with the replacement operations/segments/statements/etc., it does not explicitly disclose selecting the replacement operations/statements/segments/etc. from a set of candidate replacement operations, and as such does not explicitly state, however Gao teaches:
candidate replacement memory operations from a set of candidate replacement memory operations (pars. [0054]-[0055], [0071], [0084]-[0090], optimization is transformation/modification/etc. performed on source code such as in-lining functions, code hoisting, loop unrolling, code motion, tiling, memory hierarchy optimization, replacing loop with nested loops, etc. (code optimizations are replacing/transforming/modifying/etc. memory operations in software program/code and as such are replacement memory operations), and multiple/possible/various/etc. optimization schemes/code transformations/code replacements/etc. to optimize source code are determined (candidate replacement memory operations from set/multiple/various/two or more/etc. candidate code replacement memory operations) and analyzed/compared/evaluated/etc. and an optimization scheme/replacement memory operation is selected/recommended/determined/etc. and used to optimize/transform/replace/etc. code causing bottleneck/performance issues/etc.);
select a replacement memory operation (pars. [0054], [0071], [0084]-[0088], [0090], optimization is transformation/modification/etc. performed on source code such as in-lining functions, code hoisting, loop unrolling, code motion, tiling, memory hierarchy optimization, replacing loop with nested loops, etc. (code optimizations are replacing/transforming/modifying/etc. memory operations in software program/code), and multiple/possible/various/etc. optimization schemes/code transformations/code replacements/etc. to optimize source code are determined and analyzed/compared/evaluated/etc. and an optimization scheme having best performance is selected/recommended/determined/etc. and used to optimize/transform/replace/etc. code causing bottleneck/performance issues/etc. (selection of the one or more replacement memory operations/code optimizations/etc. to replace the one or more memory operations, the selection based on the plurality of performance metrics/comparing/analyzing/evaluating of possible/plurality/multiple code optimizations/candidate replacement memory operations and selecting/recommending/determining optimization with best performance/performance metrics).); and
replace the one or more memory operations with the replacement memory operation (pars. [0059], [0071], [0109], optimization scheme/recommended optimization scheme/replacement memory operation is selected and implemented in code/code is transformed/optimized/etc. based on the optimizations/optimization scheme (replace memory operations with replacement memory operation).).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add candidate replacement memory operations from a set of candidate replacement memory operations; select a replacement memory operation; and replace the one or more memory operations with the replacement memory operation, as conceptually taught by Gao, into that of Bikshandi because these modifications allow for multiple/different/several/etc. replacement memory operations/code optimizations/etc. to be considered and a desired replacement memory operation/code optimization to be selected/determined/etc. and used/implemented/etc. thereby helping to ensure that the replacement memory operation is a desired memory operation that ensures the code/software performs/operates as desired/required.
While Bikshandi and Gao teach optimizing code by replacing operations/statements/segments/loops/etc. of code/software/etc. with operations/statements/segments/etc. from a set of candidate operations they do not explicitly state, however Schuchman teaches:
select a replacement memory operation based, at least in part, on the replacement memory operation having a lower cost than a second one of the two or more candidate replacement memory operations (pars. [0030], [0038], [0058]-[0060], [0072], [0081], [0099]-[0100], cost analysis is performed on replacement operations from replacement code database and replacement operation that is most cost effective/less costly/has lowest cost/etc. is used to replace original code/candidate code/etc. (select replacement memory operation/replacement code/replacement operation/etc. based on replacement operation having lower cost/being cost effective/less costly/etc. than second/other/etc. candidate replacement operation).).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add select a replacement memory operation based, at least in part, on the replacement memory operation having a lower cost than a second one of the two or more candidate replacement memory operations, as conceptually taught by Schuchman, into that of Bikanshandi and Gao because these modifications allow for the code/memory operation/replacement operation/etc. that is most cost effective/has lowest cost/etc. to be used to replace/update/modify/etc. code/operations/etc., which is desirable as it reduces costs of the code and helps ensure that the code executes efficiently, effectively, and without errors while saving/reducing costs of execution, thereby making the code more desirable to users.
As per claim 2, Bikshandi further teaches:
cause a compiler to select the replacement memory operation based, at least in part, on a plurality of performance metrics associated with the set of replacement memory operations (col. 6 lines 1-30, col. 8 lines 50-61, memory operation/loop is replaced with nested loops/replacement memory operations which are evaluated to determine whether they fit in the cache memory (performance metrics associated with replacement memory operations) and if not then replacement with nested loops is applied recursively until a set of nested loops/replacement memory operations is determined/selected/identified/etc. that fit in the cache memory (selecting/determine/identify/etc. the one or more replacement memory operations/nested loops/etc. based, at least in part, on one or more estimated performance metrics associated with replacement memory operations/nested loops fitting inside cache memory/have size that is not larger than cache memory size/etc.).).
Bikshandi does not explicitly state, however Gao teaches: wherein the circuitry is to cause a compiler to
select the replacement memory operation from the set of candidate replacement memory operations based, at least in part, on a plurality of performance metrics associated with the set of candidate replacement memory operations (pars. [0071], [0084]-[0088], multiple/possible/various/etc. optimization schemes/code transformations/code replacements/etc. (set of candidate replacement memory operations) to optimize source code are determined and analyzed/compared/evaluated/etc. and an optimization scheme having best performance is selected/recommended/determined/etc. (select replacement memory operation from set of candidate replacement memory operations based on performance metrics associated with set of candidate replacement memory operations) and used to optimize/transform/replace/etc. code causing bottleneck/performance issues/etc.. As the optimization scheme/replacement memory operation with the best performance of the possible/various/candidate replacement memory operations is selected, it is obvious that the selection is based on the plurality of performance metrics associated with the set of candidate replacement memory operations as the optimization scheme/replacement operation with the best performance is selected.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add select the replacement memory operation from the set of candidate replacement memory operations based, at least in part, on a plurality of performance metrics associated with the set of candidate replacement memory operations, as conceptually taught by Gao, into that of Bikshandi because these modifications allow for multiple/different/several/etc. replacement memory operations/code optimizations/etc. to be considered and a desired replacement memory operation/code optimization having the best/desired/etc. performance to be selected/determined/etc. and used/implemented/etc. thereby helping to ensure that the replacement memory operation is a desired memory operation that ensures the code/software performs/operates as desired/required.
As per claim 3, Bikshandi further teaches: wherein the replacement memory operation is to reduce a demand for registers during performance of the software program (col. 5 line 64-col. 6 line 30, loop/input code segment/etc. having size exceeding/larger than/etc. available cache memory is replaced with pair of nested loops (replacement memory operations) that fit in memory to improve performance by reducing memory bandwidth pressure during code execution (reduce a demand/memory bandwidth pressure/etc. for registers/memory/cache memory/etc. during performance of the software program). As the specification of this application discloses that a register is a type of memory (ex: par. [0048] “…In at least one embodiment, a register is a type of memory…”) with broadest reasonable interpretation, a register may be interpreted to be a memory and as such Bikshandi’s replacing input code segments/loops/memory operation having a size that exceeds/is larger than/etc. available memory with a pair of nested loops/replacement memory operations that fit in available memory to improve performance by reducing memory bandwidth pressure during code execution is replacement memory operations/nested loops/etc. are to reduce a demand for registers/memory/cache/etc. during performance of the software program/reducing memory bandwidth pressure during code execution/etc.).
As per claim 5, Bikshandi does not explicitly state, however Gao teaches:
wherein the circuitry is to cause a compiler to use one or more heuristics to measure performance effects of replacing the one or more memory operations with the two or more candidate replacement memory operations (pars. [0059], [0070]-[0071], [0084]-[0087], performance/performance parameters/performance metrics/etc. of possible/various/etc. code optimization schemes/candidate replacement memory operations are determined/measured (use heuristics to measure/determine/etc. performance effects/performance parameters/performance metrics/etc. of replacing memory operations with the candidate replacement memory operations/code optimization schemes) such as execution time, memory access issues, tiling size, etc. and optimization scheme/candidate replacement memory operation with best performance is selected.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add wherein the circuitry is to cause a compiler to use one or more heuristics to measure performance effects of replacing the one or more memory operations with the two or more candidate replacement memory operations, as conceptually taught by Gao, into that of Bikshandi because these modifications allow for an effective and efficient method of analyzing/comparing/evaluating/etc. candidate replacement operations/possible optimizations and determining/selecting/etc. a desired operation/optimization to be used/implemented/etc., thereby helping to ensure that optimization/replacement operation selected is desirable and meets requirements and the code/software operates/performs/etc. as desired.
As per claim 7, Bikshandi does not explicitly state, however Gao teaches:
wherein the plurality of performance metrics include runtime, power consumption, and memory requirements (par. [0054], performance metrics include a target power consumption (power consumption requirement), a target execution speed (runtime/execution requirement), a predetermined number of cache misses, register spills (memory/cache/register/etc. requirements), etc.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add wherein the plurality of performance metrics include runtime, power consumption, and memory requirements, as conceptually taught by Gao, into that of Bikshandi because these modifications allow for additional performance metrics to be considered when determining and selecting replacement memory operations/code optimizations/etc. thereby helping to ensure that the selected replacement operation/code optimization meets requirements/performs as desired/etc. and allows for the code/software to operate/perform as desired/required.
As per claims 8-9, they recite systems having similar limitations as the processors of claims 1-2, respectively, and are therefore rejected for similar reasoning as claims 1-2, respectively, above.
As per claim 10, Bikshandi further teaches: wherein the replacement memory operation is to reduce register pressure of one or more portions of the software program (col. 5 line 64-col. 6 line 30, loop/input code segment/etc. having size exceeding/larger than/etc. available cache memory is replaced with pair of nested loops (replacement memory operations) that fit in memory to improve performance by reducing memory bandwidth pressure during code execution (reduce pressure/memory bandwidth pressure/etc. for registers/memory/cache memory/etc. of one or more portions of the software program). As the specification of this application discloses that a register is a type of memory (ex: par. [0048] “…In at least one embodiment, a register is a type of memory…”) with broadest reasonable interpretation, a register may be interpreted to be a memory and as such Bikshandi’s replacing input code segments/loops/memory operation having a size that exceeds/is larger than/etc. available memory with a pair of nested loops/replacement memory operations that fit in available memory to improve performance by reducing memory bandwidth pressure is replacement memory operations/nested loops/etc. are to reduce registers/memory/cache/etc. pressure/memory bandwidth pressure/etc.).
As per claim 12, Bikshandi further teaches: wherein the one or more circuits are to cause one of the one or more memory operations within the software program to be automatically replaced by two or more replacement memory operations of different types (col. 6 lines 20-40, col. 8 lines 22-25, input code segment/loop/exponential function call/etc. (memory operation within software program) is replaced with modified code/smaller blocks/tiles that fit inside memory cache, for example, loop/memory operation is replaced/automatically replaced/etc. with a pair of nested loops/outer loop and inner loop/multiply operation and table lookup/etc. (two replacement memory operations). And as the memory operation/loop/exponential function call is replaced with nested loops/outer and inner loop/multiply operation and table lookup, the memory operation is replaced by replacement operations of a different types/nested loops/inner and outer loop/multiply operation and table lookup/etc. type instead of singular loop/exponential function call/etc. type.).
As per claim 14, Bikshandi further teaches: wherein the one or more memory operations are associated with one or more portions of the software program (col. 4 line 59-67, col. 5 line 60-col. 6 line 30, input code segment from source code (portion of software program) is read and determination is made that a loop exceeding/larger than/etc. size of cache memory (memory operation) is included in the code segment (one or more memory operations/loop exceeding cache memory size/etc. is associated with/included in/etc. portion of software program/code segment of software program/etc.).).
As per claims 15, it recites a method having similar limitations as the processor of claims 1, and is therefore rejected for similar reasoning as claim 1, above.
As per claim 16, Bikshandi further teaches: selecting the one or more replacement memory operations is further based, at least in part, on one or more threshold performance metric values (col. 6 lines 1-30, col. 8 lines 50-61, memory operation/loop is replaced with nested loops/replacement memory operations which are evaluated to determine whether they fit in the cache memory (threshold performance metric value) and if not then replacement with nested loops is applied recursively until a set of nested loops/replacement memory operations is determined/selected/identified/etc. that fit in the cache memory (selecting/determine/identify/etc. the one or more replacement memory operations/nested loops/etc. based, at least in part, on one or more threshold performance metric values/fit inside cache memory/have size that is not larger than cache memory size/etc.).).
As per claim 18, Bikshandi does not explicitly state, however Gao teaches:
wherein the calculating is based, at least in part, on measuring a difference between the two or more candidate replacement memory operations (pars. [0071], [0084]-[0088], [0090], multiple/possible/various/etc. optimization schemes/code transformations/code replacements/candidate replacement memory operations/etc. to optimize source code are determined and analyzed/compared/evaluated/etc. and an optimization scheme having best performance is selected/recommended/determined/etc.. As the possible/various/multiple optimization schemes/candidate replacement memory operations are evaluated/analyzed/compared/etc. and the optimization/replacement operation with the best performance is selected/recommended/etc., it is obvious that the difference between the various/multiple/two or more/etc. optimization schemes/candidate replacement memory operations is measured/determined/analyzed/evaluated/etc. so that the best performing optimization scheme/replacement operation may be selected/determined/recommended/etc..).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add wherein the calculating is based, at least in part, on measuring a difference between the two or more candidate replacement memory operations, as conceptually taught by Gao, into that of Bikshandi because these modifications allow for an effective and efficient method of analyzing/comparing/etc. candidate replacement operations/possible optimizations and determining/selecting/etc. a desired operation/optimization to be used/implemented/etc., thereby helping to ensure that optimization/replacement operation selected is desirable and meets requirements and the code/software operates/performs/etc. as desired.
As per claim 19, Bikshani further teaches: wherein the one or more memory operations are automatically replaced with the replacement memory operations based, at least in part, on a heterogeneous set of replacement memory operations (col. 6 lines 30-37, col. 8 lines 22-25, memory operation/loop/exponential function call/etc. is replaced with optimized code segment/replacement memory operations/etc., and replacement memory operations may be pair of nested loops/outer loop and inner loop, a multiply operation and table lookups, etc.. As the singular loop/exponential function call/memory operation is replaced with outer loop and inner loop/multiply operation and table lookup/etc., the replacement memory operations are heterogeneous as the replacement operations are different/heterogeneous operations/outer loop and inner loop/multiply operation and table lookup/etc.).
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Bikshandi et al. (herein called Bikshandi) (US Patent 9,372,678 B2), Gao et al. (herein called Gao) (US PG Pub. 2020/0293295 A1), and Schuchman et al. (herein called Schuchman) (US PG Pub. 2016/0259628 A1), in further view of Cappello et al. (herein called Cappello) (US PG Pub. 2021/0182039 A1).
As per claim 4, Bikshandi, Gao, and Schuchman do not explicitly state, however Cappello teaches:
wherein the one or more circuits are to store information indicating one or more estimated performance metrics of the one or more memory operations (pars. [0063], instances of source code (source code including code segments/loops/memory operations from Bikshandi) are created/developed/etc. and performance data/performance metric/statistical properties/etc. of the code/memory operations (information indicating performance metrics of the memory operations) is acquired and stored (store information indicating estimated performance metrics of the memory operations) as training data.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add wherein the one or more circuits are to store information indicating one or more estimated performance metrics of the one or more memory operations, as conceptually taught by Cappello, into that of Bikshandi, Gao, and Schuchman because these modifications allow for information/data about performance of memory operations/code/etc. to be stored thereby allowing it to be used when making decisions about the operations/code/etc. so that informed decisions about the code/whether to use the code/whether to change the code/etc. may be made, which is desirable as it helps insure that informed decisions are made increasing the usability of the code and helping to ensure that the code operates correctly/as desired/etc..
As per claim 11, it recites a system having similar limitations as the processor of claim 4, and is therefore rejected for similar reasoning as claim 4, above.
Claims 6, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bikshandi et al. (herein called Bikshandi) (US Patent 9,372,678 B2), Gao et al. (herein called Gao) (US PG Pub. 2020/0293295 A1), and Schuchman et al. (herein called Schuchman) (US PG Pub. 2016/0259628 A1), in further view of Smith et al. (herein called Smith) (US PG Pub. 2020/0097261 A1).
As per claim 6, while Bikshandi teaches replacing memory operation/code segments/code with replacement memory operations/replacement code/etc., it does not explicitly state, however Smith teaches:
wherein the circuitry is further to replace the one or more memory operations with the replacement memory operations based, at least in part, on an indication of priority of the replacement memory operation (pars. [0078], [0081], [0112]-[0114], [0120], relevant code snippets for potential changes (replacement code/memory operation from Bikshandi) to be used to modify/change/complete/etc. (replace) code are identified from code storage based on features/use/performance metrics/etc. and ranked according their usefulness/likeliness of being used/etc. to determine a sequential order of the code snippets for selection to be used in the code/to modify the code/change the code/replace code/etc. (replacement/modification/change/etc. of the one or more memory operations/code/etc. is performed based on an indication of priority/ranking/sequential order/etc. of the replacement memory operations/code snippets to be used to change the code/modify the code/etc.).).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add wherein the circuitry is further to replace the one or more memory operations with the replacement memory operations based, at least in part, on an indication of priority of the replacement memory operation, as conceptually taught by Smith, into that of Bikshandi, Gao, and Schuchman because these modifications allow for replacement memory operations/code snippets/etc. to be selected to be used in the code/replace code/etc. that are believed to be more useful/more likely to be used/etc., thereby increasing the usability of the replacement memory operations/code snippets/etc. and helping to ensure that the code operates as desired/intended by users when they select/determine/etc. code to be used in the software program/code/etc..
As per claim 13, Bikshandi, Gao, and Schuchman do not explicitly state, however Smith teaches:
wherein the one or more circuits are to store two or more replacement memory operations in a priority queue (pars. [0112]-[0114], code snippets (two or more replacement memory operations from Bikshandi) are stored in storage location and ranked in sequential order according to criteria/performance metrics/etc. for selection to be used to change/modify/be used/in/etc. code (store two or more replacement memory operations/code snippets to be used to change code/etc. in a priority queue/ranked sequential order for selection/etc.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add wherein the one or more circuits are to store two or more replacement memory operations in a priority queue, as conceptually taught by Smith, into that of Bikshandi, Gao, and Schuchman because these modifications allow for the replacement memory operations/code snippets used to change code/etc. to be prioritized/ranked/sorted/ordered/etc. so that replacement operations/code snippets believed to be more desirable/have better usability/etc. are indicated as such, which is desirable as it provides more information to be used when selecting operations/snippets to be used so that more informed selections may be made, thereby helping to ensure that code operates as desired/intended/etc. by users.
As per claim 20, Bikshandi and Gao do not explicitly state, however Smith teaches:
wherein the one or more memory operations are automatically replaced with the replacement memory operation based, at least in part, on selecting the replacement memory operation from a priority queue (pars. [0078]-[0082], [0112]-[0114], code snippets (replacement memory operations from Bikshandi) are stored in storage location and ranked in sequential order according to criteria/performance metrics/etc. (priority queue) for selection to be used to change/modify/be used/in/etc. code (selecting the one or more replacement memory operations/code snippets from a priority queue/ranked sequential order of code snippets to change/replace/modify/etc. code).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add wherein the one or more memory operations are automatically replaced with the replacement memory operation based, at least in part, on selecting the replacement memory operation from a priority queue, as conceptually taught by Smith, into that of Bikshandi and Gao because these modifications allow for the replacement memory operations/code snippets to change code/etc. to be prioritized/ranked/sorted/ordered/etc. so that replacement operations/code snippets believed to be more desirable/have better usability/etc. are indicated as such when selection of replacement operations/code snippets occurs, which is desirable as it provides more information to be used when selecting operations/snippets to be used so that more informed selections may be made, thereby helping to ensure that code operates as desired/intended/etc. by users.
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Bikshandi et al. (herein called Bikshandi) (US Patent 9,372,678 B2), Gao et al. (herein called Gao) (US PG Pub. 2020/0293295 A1), and Schuchman et al. (herein called Schuchman) (US PG Pub. 2016/0259628 A1), in further view of Chow (US PG Pub. 2014/0325190 A1).
As per claim 17, Bikshandi further teaches: wherein the replacement memory operation is to reduce register pressure of one or more portions of the software program (col. 5 line 64-col. 6 line 30, loop/input code segment/etc. having size exceeding/larger than/etc. available cache memory is replaced with pair of nested loops (replacement memory operations) that fit in memory to improve performance by reducing memory bandwidth pressure during code execution (reduce pressure/memory bandwidth pressure/etc. for registers/memory/cache memory/etc. of one or more portions of the one or more software programs) when optimizing code/software/program/etc.. As the specification of this application discloses that a register is a type of memory (ex: par. [0048] “…In at least one embodiment, a register is a type of memory…”) with broadest reasonable interpretation, a register may be interpreted to be a memory and as such Bikshandi’s replacing input code segments/loops/memory operation having a size that exceeds/is larger than/etc. available memory with a pair of nested loops/replacement memory operations that fit in available memory to improve performance by reducing memory bandwidth pressure is replacement memory operations/nested loops/etc. are to reduce registers/memory/cache/etc. pressure/memory bandwidth pressure/etc.).
While Bikshandi teaches that optimizing code includes replacing memory operations with replacement memory operations to reduce register pressure/memory bandwidth pressure of portions/segments/loop/etc. of code/software/program/etc., it does not explicitly disclose that this optimization/replacement of operations/etc. occurs prior to/before/etc. a register/memory allocation of compilation, and as such does not explicitly state, however Chow teaches:
wherein the replacement memory operation is to reduce register pressure of one or more portions of the one or more software programs prior to a register allocation phase of compilation (abstract, pars. [0009]-[0010], [0012]-[0014], [0027]-[0028], compiler performs optimization on code which includes converting/replacing instructions/operations in the code into different form/type/etc. of instructions/operations (replacement memory operations during optimization from Bikshandi), and then compiler allocates registers to code. As Chow teaches that optimizations/replacement/etc. of code is performed by compilers before the compilers allocate registers, and Bikshandi teaches that optimization of code includes replacing memory operations with replacement memory operations to reduce register/memory pressure of one or more portions of the one or more software programs, it is obvious that the optimizations/replacement of code/etc. may include replacement memory operations to reduce register/memory pressure of one or more portions of the one or more software programs and that the replacement occurs/is performed by compiler/etc. before/prior to/etc. allocating registers, and as such the one or more replacement memory operations are to reduce register pressure of one or more portions of the one or more software programs prior to a register allocation phase of compilation.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add wherein the one or more replacement memory operations are to reduce register pressure of one or more portions of the one or more software programs prior to a register allocation phase of compilation, as conceptually taught by Chow, into that of Bikshandi, Gao, and Schuchman because these modifications allow for memory/registers/etc. to be allocated/assigned/etc. to the code after the code has been optimized/modified/replacements have occurred/etc., which is desirable as it helps ensure that the code operates/executes/performs/etc. correctly/as intended/as desired/without error/etc. during execution.
Response to Arguments
Applicant's arguments filed 11/20/2025 have been fully considered but they are not persuasive.
As per the 101 arguments on pg. 7 pars. 1-pg. 8 par. 1 that the amended independent claims are allowable under 35 USC 101 because they recite the selection of a replacement memory operation having a lower cost that another candidate replacement memory operation and replacing the memory operation with the selected replacement memory operation, which integrates the abstract idea into a practical application, the examiner, respectfully, disagrees. The examiner would like to point out that the claims do not make clear what the “lower cost” is in reference to, and as such, with broadest reasonable interpretation, the “cost” may be any type of cost/consumption/etc. of/among the candidate replacement memory operations. Further, the claims do not specify further details as to how the cost is determined, how the replacement is performed, benefit/improvement/practical application provided by the selected replacement memory operation over the memory operation being replaced, etc., and as such, as seen above in the rejection of the independent claims under 35 USC 101, with broadest reasonable interpretation, the selection of a replacement memory operation having a lower cost than another candidate replacement memory operation may be performed mentally/with pen and paper by a human via judgement/evaluation/determination/selection/ analysis/etc., and the replacement of the memory operation with the replacement memory operation amounts to an insignificant extra solution activity of updating/changing/replacing/etc. data/memory operation/etc. according to the results of the abstract idea/selection performed mentally by a human/etc., which, at best, amount to the words “apply it”. As such, the examiner finds these arguments unpersuasive and maintains that the rejection under 35 USC 101 is proper.
Applicant’s 103 arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
As per the 103 arguments on pg. 8 par. 2-pg 11 par. 5 of the remarks that Bikshandi et al. (herein called Bikshandi) (US Patent 9,372,678 B2) and Gao et al. (herein called Gao) (US PG Pub. 2020/0293295 A1) do not teach all feature of the amended independent claims and none of the other references cited with respect to the dependent claims correct the deficiencies of Bikshandi and Gao, and therefore the amended independent claims and their respective dependent claims are allowable, the examiner would like to point out that the new reference and Schuchman et al. (herein called Schuchman) (US PG Pub. 2016/0259628 A1) is currently relied upon to correct the deficiencies of Bikshandi and Gao with respect to the amended independent claims and therefore the arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Therefore, the examiner finds these arguments unpersuasive and maintains that the rejection under 35 USC 103 is proper.
Conclusion
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/DOUGLAS M SLACHTA/ Examiner, Art Unit 2193