DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 4-6, 8, 14, and 16-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 4, which depends from claim 1, recites the limitation "the first upper metal line" in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 5, which depends from claim 1, recites the limitation "the first upper metal line" in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 6, because it is dependent on claim 5, inherits the deficiency of claim 5.
Claim 8, which depends directly from claim 1, recites the limitation "the first upper metal line" in line 2 and again in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 14, which depends directly from claim 10, recites the limitation "the first upper metal line" in line 2 and again in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 16, which depends from claim 10, recites the limitation "the first upper metal line" in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 17 recites the limitation "the first upper metal line" on page 35, line 17. There is insufficient antecedent basis for this limitation in the claim.
Claims 18-20, because they are dependent on claim 17, inherit the deficiency of claim 17.
Claim 18, which directly depends from claim 17, recites the limitation "the first upper metal line" in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 20, which directly depends from claim 17, recites the limitation "the first upper metal line" in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination with regard to the prior art, the term “the first upper metal line” will be treated as “the plurality of first upper metal lines” which does have sufficient antecedent basis from independent claims 1, 10, and 17.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Peng et al. (US 20220122971).
Regarding claim 1, Peng teaches, in Figs. 1, 2A, and 2E, a semiconductor device (200A, [0036]), comprising:
first (labelled as 115 in Fig. 1, labelled as 196 of 112 in Fig. 2E, [0029], [0051]) and second active patterns (labelled as 125 in Fig. 1, labelled as 196 of 122 in Fig. 2E, [0029], [0051]) spaced apart from each other in a third direction (z-direction);
a gate electrode (130, [0034]) covering the first and second active patterns (see Fig. 2E, [0033]) and extending in a second direction [[0034], y-direction, Fig. 2A);
a first source/drain region (113/114, [0029]) disposed on opposing sides of the gate electrode (130) and connected to the first active pattern (115) ([0029]);
a second source/drain region (123/124, [0033]) disposed on opposing sides of the gate electrode (130) and connected to the second active pattern (125) ([0033], see Fig. 1);
a plurality of first upper metal lines (144a and 144b; Figs. 2A and 2E; [0039]) extending in a first direction (x-direction) on the second active pattern (125) and spaced apart from each other in the second direction (y-direction) (see Fig. 2A); and
a lower metal line (134b, Figs. 2A and 2E; [0038]) extending in the first direction (x-direction) on the (bottom surface of) first active pattern (115),
wherein the first direction (x-direction), the second direction (y-direction) and the third direction intersect each other (z-direction).
Regarding claim 2, Peng further teaches, in Figs. 1 and 2A, a first active contact (116b, [0031]) electrically connected to the first source/drain region (113/114) and disposed (electrically) between the lower metal line (134b) and the first source/drain region (113/114) (see Fig. 2A).
Regarding claim 3, Peng further teaches, in Figs. 2A and 2E, a first active via (164, [0041]) disposed between the first active contact (116b) and the lower metal line (134b) and configured to electrically connect the first active contact (116b) to the lower metal line (134b) (see Fig. 2A).
Regarding claim 4, Peng further teaches, in Figs. 2A and 2E, a second active via (162, [0041]) disposed between the first active contact (116b) and the first upper metal line (144a) and configured to electrically connect the first active contact (116b) to the first upper metal line (144a) ([0052], see Fig. 2A how 116b is connected to 174b, and Fig. 2E how 174b is connected to 162 through 126).
Regarding claim 5, Peng further teaches a second active contact (126a, Figs. 1 and 2A) electrically connected to the second source/drain region (123/124) and disposed between the first upper metal line (144a) and the second source/drain region (123/124) (see Figs. 1 and 2A).
Regarding claim 6, Peng further teaches, in Fig. 2E, a via contact (174b, Figs. 2A and 2E, [0056]) disposed between the first active contact (116b) and the second active contact (126a) and configured to electrically connect the first active contact to the second active contact (see Fig. 2A).
Claims 1 and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wu et al. (US 20210242205).
Regarding claim 1, Wu teaches, in Fig. 2B, a semiconductor device (206B), comprising:
first (210(1)) and second active patterns (208(1)) ([0042]) spaced apart from each other in a third direction (z-axis);
a gate electrode (gate, 212(1), [0045]) covering the first and second active patterns (Fig. 2F) and extending in a second direction (x-axis);
a first source/drain region (MDP, [0045]) disposed on opposing sides of the gate electrode (212(1)) and connected to the first active pattern (ARP) ([0045], see Fig. 2B);
a second source/drain region (MDN, [0045]) disposed on opposing sides of the gate electrode (212(1)) and connected to the second active pattern (ARN) ([0045], see Fig. 2B);
a plurality of first upper (upper if Fig. 2B is flipped) metal lines (226(1)-226(4), [0049]) extending in a first direction (y-axis) on the second active pattern (MDN) and spaced apart from each other in the second direction (x-axis) (see Fig. 2B); and
a lower (lower if Fig. 2B is flipped) metal line (222(3), [0046]) extending in the first direction (y-axis) on the (bottom surface if Fig. 2B is flipped) first active pattern (MDP),
wherein the first direction (y-axis), the second direction (x-axis) and the third direction (z-axis) intersect each other (orthogonally).
Regarding claim 9, Wu further teaches, in Fig. 2B, a gate contact (VGT, [0050]) configured to electrically connect the gate electrode (gate, 212(1)) to the lower metal line (222(3)) ([0050]) and disposed between the gate electrode and the lower metal line (see Fig. 2B.
Claims 10-11 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chanemougame et al. (US 20220271033).
Regarding claim 10, Chanemougame teaches, in Figs. 6A and 6B, a semiconductor device comprising a standard cell region (600, [0041]), wherein the standard cell region comprises:
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First, second, and third directions of Chanemougame Fig. 6a (left) and Fig. 6b (right)
a first power wiring (top left 622 of Fig. 6b, [0047]) extending in a first direction (see D1 in above figure, hereinafter “D1”) and configured to supply a first power voltage to the standard cell region ([0047]);
a second power wiring (top right 622 of Fig. 6b, [0047]) extending in parallel with the first power wiring (in D1 direction) and configured to supply a second power voltage different from the first power voltage to the standard cell region ([0047]);
a lower metal line (662, lower if Fig. 6b is flipped, [0046]) disposed on a same level as the first and second power wirings (top left 622 and top right 622) and disposed between the first and second power wirings (see Fig. 6b), wherein the lower metal line extends in the first direction (D1);
a plurality of first upper metal lines (661, [0043]) extending in the first direction (D1) on the lower metal line (662) and spaced apart from each other in a second direction (see D2 above, hereinafter “D2”);
a plurality of gate electrodes (G, [0050]) disposed between the lower metal line (662) and the plurality of first upper metal lines (661), and extending in the second direction (D2) (see Fig. 6b), wherein the plurality of gate electrodes are spaced apart from each other in the first direction (D1) (see Fig. 6b);
a first source/drain region (bottom S/D, Fig. 6b) disposed between the plurality of gate electrodes (G) ([0050]);
a second source/drain region (top S/D, Fig. 6b, [0050]) disposed between the plurality of gate electrodes (G) and spaced apart from the first source/drain region (bottom S/D) in a third direction (vertical direction, see D3 in above figure);
a first active pattern (bottom set of CH, [0045]) connected to the first source/drain region (bottom S/D) and disposed in the gate electrode (G) (see Fig. 6b); and
a second active pattern (top set of CH, [0045]) connected to the second source/drain region (top S/D) and disposed in the gate electrode (G), wherein the second active pattern is spaced apart from the first active pattern in the third direction (vertical direction) (see Fig. 6b),
wherein the first direction (D1), the second direction (D2) and the third direction (D3) intersect each other (see above figure).
Regarding claim 11, Chanemougame further teaches that three or four first upper metal lines of the plurality of first upper metal lines (661) are disposed between the first and second power wirings (see Fig. 6a how there are three 661 lines in between the leftmost and rightmost 622).
Regarding claim 15, Chanemougame further teaches a first gate contact (680) configured to electrically connect some of the plurality of gate electrodes (G) to the lower metal line (662) ([0049], [0060], first gate contact 680 connects gate electrodes G to 661, which is connected to 662).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210242205) in view of Zhuang et al. (US 20220384417).
Regarding claim 7, Wu teaches the limitations of claim 1. Wu further teaches, in Fig. 2B, first (222(1)) and second power wirings (222(4)) ([0046]) disposed on a same level as the lower metal line (222(3)) (see Fig. 2B, [0046]), and extending in the first direction (y-axis), wherein the first and second power wirings are spaced part from each other in the second direction (x-axis) (see Fig. 2B).
Wu does not explicitly teach that a width of each of the first and second power wirings in the second direction is greater than a width of the lower metal line in the second direction.
In a similar field of endeavor, Zhuang teaches, in Fig. 1, that a width of each of the first (PR1) and second power wirings (PR4) in the second direction (y-direction) is greater than a width of the lower metal line (PR2) in the second direction ([0042]-[0043]), because increasing the width of the power wirings improves power signal stability, and decreasing the width of the lower metal line decreases the its area on the layout ([0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the widths of the power wirings and lower metal line of Wu with the widths of Zhuang, because increasing the width of the power wirings improves power signal stability, and decreasing the width of the lower metal line decreases the its area on the layout ([0042]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210242205) in view of Song et al. (US 20170032074).
Regarding claim 8, Wu teaches the limitations of claim 1. Wu does not teach a second upper metal line extending in the second direction on the first upper metal line and connected to the first upper metal line.
In a similar field of endeavor, Song teaches, in Fig. 4B, that a second upper metal line (M21) extending in the second direction (D2) on the first upper metal line (M11 that extends in first direction D1) (see Fig. 4B, [0052]) and connected to the first upper metal line (see Fig. 7C), in order to increase the degree of freedom in the routing ([0119]) and because this orthogonal configuration allows M21 to more easily overlap with M11 and thus more easily connect with M11 ([0052]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the upper metal lines of Wu with the second upper metal line of Song, in order to increase the degree of freedom in the routing ([0119]) and more easily connect the first upper metal line to the second upper metal line.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame et al. (US 20220271033) in view of Wu et al. (US 20210242205).
Regarding claim 12, Chanemougame teaches the limitations of claim 10. Chanemougame does not explicitly teach a first active contact electrically connected to the first source/drain region and disposed between the lower metal line and the first source/drain region.
In a similar field of endeavor, Wu teaches, in Fig. 2B, a first active contact (VMDPT, 238(2), [0050]) electrically connected to the first source/drain region (MDP, [0045]) and disposed (physically) between the lower metal line (222(3), [0046]) and the first source/drain region (MDP) (see Fig. 2B), because this has the “benefit of providing an increased routing resource in M0 layer” and “the routing resource in the M0 layer which is consumed for conducting logic according to the other approach is available in the CFET regions of some embodiments because logic signals are conducted by corresponding logic conductors in the MB layer” ([0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the interconnection of Chanemougame with the first active contact configuration of Wu, in order to improve the routing resource in the lower metal line level ([0035]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame et al. (US 20220271033) in view of Zhuang et al. (US 20220384417).
Regarding claim 13, Chanemougame teaches the limitations of claim 10. Chanemougame does not explicitly teach that a width of each of the first and second power wirings in the second direction is greater than a width of the lower metal line in the second direction.
In a similar field of endeavor, Zhuang teaches, in Fig. 1, that a width of each of the first (PR1) and second power wirings (PR4) in the second direction (y-direction) is greater than a width of the lower metal line (PR2) in the second direction ([0042]-[0043]), because increasing the width of the power wirings improves power signal stability, and decreasing the width of the lower metal line decreases the its area on the layout ([0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the widths of the power wirings and lower metal line of Chanemougame with the widths of Zhuang, because increasing the width of the power wirings improves power signal stability, and decreasing the width of the lower metal line decreases the its area on the layout ([0042]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame et al. (US 20220271033) in view of Song et al. (US 20170032074).
Regarding claim 14, Chanemougame teaches the limitations of claim 10. Chanemougame does not teach a second upper metal line extending in the second direction on the first upper metal line and connected to the first upper metal line.
In a similar field of endeavor, Song teaches, in Fig. 4B, that a second upper metal line (M21) extending in the second direction (D2) on the first upper metal line (M11 that extends in first direction D1) (see Fig. 4B, [0052]) and connected to the first upper metal line (see Fig. 7C), in order to increase the degree of freedom in the routing ([0119]) and because this orthogonal configuration allows M21 to more easily overlap with M11 and thus more easily connect with M11 ([0052]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the upper metal lines of Chanemougame with the second upper metal line of Song, in order to increase the degree of freedom in the routing ([0119]) and more easily connect the first upper metal line to the second upper metal line.
Allowable Subject Matter
Claim 16 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 17-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 16, the closest prior art is Chanemougame et al. (US 20220271033) and Chen et al. (US 20230036522). Chanemougame teaches the limitations of claim 15, but does not teach a plurality of second gate contacts configured to electrically connect the plurality of gate electrodes to the first upper metal line and disposed between each of the plurality of gate electrodes and each of the plurality of first upper metal lines. Chen teaches, in Figs. 8A-C and 9A, a plurality of second gate contacts (top VG) configured to electrically connect the plurality of gate electrodes (Fig. 8A, 150n/150p, [0077]; plurality gB1 and gB2 shown in Fig. 9A, [0080]) to the first upper metal line (120F, 140F, [0048]) and disposed between each of the plurality of gate electrodes and each of the plurality of first upper metal lines, but teaches against the claim 10 limitation “a lower metal line disposed on a same level as the first and second power wirings and disposed between the first and second power wirings.”
Regarding claim 17, the closest prior art is Chen et al. (US 20230036522), which teaches a standard cell region, wherein the standard cell region comprises, in Figs. 8A-8C and 9A:
first (50n) and second active (50p) patterns ([0045]) spaced apart from each other in a third direction (z-direction);
a plurality of gate electrodes (Fig. 8A, 150n/150p, [0077]; plurality gB1 and gB2 shown in Fig. 9A, [0080]) covering the first and second active patterns, and extending in a second direction (y-direction), wherein the plurality of gate electrodes are spaced apart from each other in a first direction (x-direction, see Fig. 9A);
a first source/drain region (134n, [0046]) disposed between the plurality of gate electrodes and connected to the first active pattern (50n);
a second source/drain region (134p, [0046]) disposed between the plurality of gate electrodes and connected to the second active pattern (50p);
a plurality of first upper metal lines (120F, 140F, [0048]) extending in the first direction (x-direction) on the second active pattern (50p) and spaced apart from each other in the second direction (y-direction);
a lower metal line (120B, [0048]) extending in the first direction (x-direction) under the first active pattern (50n);
a first power wiring (30B, [0046]) disposed on a same level as the lower metal line (120B), and extending in the first direction (x-direction), wherein the first power wiring is configured to supply a first power voltage (VSS, [0046]) to the first source/drain region (134n);
a second power wiring (30F, [0046]) extending in parallel with the first power wiring and configured to supply a second power voltage (VDD, [0046]) different from the first power voltage to the second source/drain region (134p);
a first gate contact (bottom VG) configured to electrically connect some of the plurality of gate electrodes to the lower metal line (120B) that is under the plurality of gate electrodes;
a plurality of second gate contacts (top VG) electrically configured to connect the plurality of gate electrodes to the first upper metal line (120F) that is disposed on each of the plurality of gate electrodes;
a first active contact (VB) electrically connected to the first source/drain region (134n) that is disposed under the first source/drain region,
and the first direction, the second direction and the third direction intersect each other.
However, Chen does not teach a first active via disposed between the lower metal line and the first active contact and configured to electrically connect the lower metal line to the first active contact, and that when viewed in a plan view, three or four first upper metal lines of the plurality of first upper metal lines are disposed between the first and second power wirings, a width of each of the first and second power wirings in the second direction is greater than a width of the lower metal line in the second direction.
Claims 18-20 depend from independent claim 17.
Conclusion
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893