Prosecution Insights
Last updated: July 17, 2026
Application No. 18/196,015

SEMICONDUCTOR STACK

Non-Final OA §103
Filed
May 11, 2023
Priority
May 11, 2022 — TW 111117590
Examiner
RAHMAN, MOHAMMAD A
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Epistar Corporation
OA Round
2 (Non-Final)
87%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
480 granted / 553 resolved
+18.8% vs TC avg
Moderate +11% lift
Without
With
+11.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
35 currently pending
Career history
580
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
63.0%
+23.0% vs TC avg
§102
17.9%
-22.1% vs TC avg
§112
15.7%
-24.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 553 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/21/2026 has been entered. STATUS OF CLAIMS Applicant’s amendment of claim(s) 1-2, 9 in “Claims - 04/21/2026” with the “Amendment/Req. Reconsideration-After Non-Final Reject - 04/21/2026” is/are acknowledged. This office action considers Claims 1-20 pending for prosecution. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. Claims 1, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20180351039 A1 - hereinafter Kim). Regarding Claim 1, Kim teaches a semiconductor stack (see the entire document; Fig. 11; specifically, [0083]-[0101], and as cited below), comprising: a first-type semiconductor layer (130 – Fig. 11 – [0101]); a second-type semiconductor layer (160 – [0083]); an active region (140 – [0101]) located between the first-type semiconductor layer (130) and the second-type semiconductor layer (160) and having a first thickness (hereinafter first thickness), wherein the active region (140) comprises an upper surface (upper surface of layer B1) and a lower surface (lower surface of Q2) closer to the first-type semiconductor layer (130) than the upper surface (upper surface of layer B1); and one or multiple recesses (recess 150 – [0100]) respectively comprises a bottom (bottom of 150), wherein the bottom (bottom of 150) is disposed in the active region (140). But Kim does not expressly disclose wherein a first distance from the bottom to the lower surface is 0.5-0.9 times the first thickness. The instant application specification contains no disclosure of either the critical nature of the claimed relative thickness i.e., “wherein a first distance from the bottom to the lower surface is 0.5-0.9 times the first thickness” or of any unexpected results arising therefrom. Applicant has not disclosed that having wherein a first distance from the bottom to the lower surface is 0.5-0.9 times the first thickness, solves any stated problem or is for any particular purpose. "Where the issue of criticality is involved, the applicant has the burden of establishing his position by a proper showing of the facts upon which he relies." - In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205 (CCPA 1946), see MPEP 2144.05.III.A. Regarding Claim 8, Kim teaches the semiconductor stack according to claim 1, wherein each of the one or multiple recesses comprises a V-shaped recess (Fig. 11 shows 150 V-shaped. Allowable Subject Matter Claims 2-7, 9-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is the Examiner’s Reasons for Allowance: The prior art fails to disclose and would not have rendered obvious: Regarding claim 2: The semiconductor stack according to claim 1, wherein each of the active region, the recess-induced layer and the first-type semiconductor layer comprises a group IV dopant, wherein the group IV dopant of the active region comprises a first group IV dopant concentration, the group IV dopant of the recess-induced layer comprises a second group IV dopant concentration, and the group IV dopant of the first-type semiconductor layer comprises a third group IV dopant concentration. Claim 3-7, 18-19 depend from claim 2. Regarding claim 9: The semiconductor stack according to claim 1, wherein the recess-induced layer comprises a second thickness, wherein the first distance is 0.3-2.7 times the first thickness. Claims 10-11 depend from claim 9. Regarding claim 12: The semiconductor stack according to claim 1, wherein each of the one or multiple recesses comprises a maximum opening width from50nm to 200 nm. Regarding claim 13: The semiconductor stack according to claim 1, further comprising a recess- filled layer between the second-type semiconductor layer and the active region, wherein the one or the multiple recesses respectively comprises a filled surface in the recess- filled layer and comprises a depth, wherein a second distance between the filled surface and the upper surface is 0.1-3 times the depth. Claims 14-17 depend from claim 13. Regarding claim 20: The semiconductor stack according to claim 1, wherein the active region comprises N pairs of alternately stacked barrier layers and well layers, wherein: when N is even, the bottom of the recess is disposed in or above the N/2 pair stacked sequentially from the lower surface; and when N is odd, the bottom of the recess is disposed in or above (N+1)/2 pair stacked sequentially from the lower surface. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD A RAHMAN/ Primary Examiner, Art Unit 2898
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Prosecution Timeline

May 11, 2023
Application Filed
Sep 04, 2025
Non-Final Rejection mailed — §103
Dec 02, 2025
Response Filed
Apr 21, 2026
Request for Continued Examination
Apr 25, 2026
Response after Non-Final Action
Jun 09, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
87%
Grant Probability
98%
With Interview (+11.1%)
2y 8m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 553 resolved cases by this examiner. Grant probability derived from career allowance rate.

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