Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, claims 1-13 and 15-17 in the reply filed on 05/29/2026 is acknowledged.
Applicant’s election of Species 1, claims 1-9 and 14-17 in the reply filed on 05/29/2026 is acknowledged.
Claims 1-9 and 15-17 are therefore pending, claims 10-14 and 18-20 are withdrawn from consideration.
Status of Claims
Claims 1-20 are pending.
Claims 10-14 and 18-20 are withdrawn from consideration.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(a-d) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 119(a-d), 120, 121, 365(c), or 386(c) as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the priority document. The disclosure of the prior-filed priority document IN202021049700, fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application. The submitted foreign priority document discloses “a monolithic solid state system, comprising a ferroelectric crystal and a semiconductor crystal arranged laterally to define a nanolayer having a heterojunction between said crystals, said nanolayer comprising at most 80 monolayers of said ferroelectric crystal.” See page 3 lines 15-17 of the submitted foreign priority document. Whereas the later-filed application (the instant application) claims “a monolithic solid state system, comprising a ferroelectric crystal and a semiconductor crystal arranged laterally to define a nanolayer having a heterojunction between said crystals, said nanolayer comprising at most 250 monolayers of said ferroelectric crystal.” See independent claim 1. The foreign priority document does not disclose a nanolayer comprising more than 80 monolayers. Therefore, independent claim 1 and its respective dependent claims have not been granted priority to the submitted foreign priority document, and have been treated as having a filing date of 11/11/2021.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-9, 15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Scalable Integration of Coplanar Heterojunction Monolithic Devices on Two Dimensional In2Se3 Mukherjee et al (herein “Mukherjee”).
Regarding Claim 1, Mukherjee discloses:
A monolithic solid state system (see generally pages 17543-17550, Introduction, Results, and Conclusions, and Methods), comprising a ferroelectric crystal (In2Se3) and a semiconductor crystal (In2O3) arranged laterally to define a nanolayer having a heterojunction (g. 17544: “It is also noted that 2D-based planar heterojunctions offer device areas with a 1D-type interface, which facilitates larger depletion regions and an abrupt change in electronic and optical properties, making them ideal candidates for many related applications but extremely challenging to achieve.16−20 Finally, owing to the large lattice mismatch (∼60%) between α/β-In2Se3 and In2O3, their heterostructure growth without interfacial defects is highly challenging.” and “Herein, we demonstrate a highly scalable, direct writing approach of monolithic integrated circuits on a 2D In2Se3 layered semiconductor using a visible light probe. In particular, by selective illumination, we have achieved spatially resolved distinct optical and electrical properties by introducing In2O3 into the In2Se3 host layer.”) between said crystals (In2Se3 and In2O3), said nanolayer comprising at most 250 monolayers of said ferroelectric crystal (pg. 17545: “Wafer-scale, few-layer In2Se3 films were grown by the chemical vapor deposition (CVD) method, and the details of growth parameters and process flow are presented in the Methods section.”, “A cross sectional HRTEM view is presented in Figure 1c, where the yellow dotted lines mark one monolayer thickness, i.e., ∼1 nm.”, and “The pristine region located away from the illuminated spot also consists of a crystalline lattice structure with a spacing of ∼0.20 nm, attributed to the (110) planes of In2Se3 along the [1120] direction (Figure S2a).35 The selected area diffraction pattern (SAED) of the pristine film exhibits six fold rotational symmetric diffraction, showing the high crystalline quality of the sample (Figure S2b). The morphology and thickness of the In2Se3 film after transfer to a SiO2/Si substrate, inspected by atomic force microscopy (AFM), exhibited high spatial homogeneity and a film thickness of ∼7 nm (∼7 individual layers), respectively (Figure 1g,h).”).
Regarding Claim 2, Mukherjee discloses: The system according to claim 1,
Mukherjee further discloses:
wherein said nanolayer comprise at most 200 monolayers of said ferroelectric crystal (pg. 17545: “Wafer-scale, few-layer In2Se3 films were grown by the chemical vapor deposition (CVD) method, and the details of growth parameters and process flow are presented in the Methods section.”, “A cross sectional HRTEM view is presented in Figure 1c, where the yellow dotted lines mark one monolayer thickness, i.e., ∼1 nm.”, and “The pristine region located away from the illuminated spot also consists of a crystalline lattice structure with a spacing of ∼0.20 nm, attributed to the (110) planes of In2Se3 along the [1120] direction (Figure S2a).35 The selected area diffraction pattern (SAED) of the pristine film exhibits six fold rotational symmetric diffraction, showing the high crystalline quality of the sample (Figure S2b). The morphology and thickness of the In2Se3 film after transfer to a SiO2/Si substrate, inspected by atomic force microscopy (AFM), exhibited high spatial homogeneity and a film thickness of ∼7 nm (∼7 individual layers), respectively (Figure 1g,h).”).
Regarding Claim 3, Mukherjee discloses: The system according to claim 1,
Mukherjee further discloses:
wherein said nanolayer comprise at most 120 monolayers of said ferroelectric crystal (pg. 17545: “Wafer-scale, few-layer In2Se3 films were grown by the chemical vapor deposition (CVD) method, and the details of growth parameters and process flow are presented in the Methods section.”, “A cross sectional HRTEM view is presented in Figure 1c, where the yellow dotted lines mark one monolayer thickness, i.e., ∼1 nm.”, and “The pristine region located away from the illuminated spot also consists of a crystalline lattice structure with a spacing of ∼0.20 nm, attributed to the (110) planes of In2Se3 along the [1120] direction (Figure S2a).35 The selected area diffraction pattern (SAED) of the pristine film exhibits six fold rotational symmetric diffraction, showing the high crystalline quality of the sample (Figure S2b). The morphology and thickness of the In2Se3 film after transfer to a SiO2/Si substrate, inspected by atomic force microscopy (AFM), exhibited high spatial homogeneity and a film thickness of ∼7 nm (∼7 individual layers), respectively (Figure 1g,h).”).
Regarding Claim 6, Mukherjee discloses: The system according to claim 1,
Mukherjee further discloses:
wherein said nanolayer is planar (see abstract: “Here we demonstrated a rapid, scalable, and site-specific integration of lateral 2D heterojunction arrays using few-layer indium selenide (In2Se3).” And pg. 17544 “Herein, we demonstrate a highly scalable, direct writing approach of monolithic integrated circuits on a 2D In2Se3 layered semiconductor using a visible light probe.”).
Regarding Claim 7, Mukherjee discloses: The system according to claim 1,
Mukherjee further discloses:
wherein said a semiconductor crystal is an oxide (see abstract “…The presented method enables high-yield, site-specific formation of lateral 2DIn2Se3−In2O3-based hybrid heterojunctions for realizing nanoscale devices with multiple advanced functionalities.”).
Regarding Claim 8, Mukherjee discloses: The system according to claim 7,
Mukherjee further discloses:
wherein said oxide is formed by oxidation of said ferroelectric crystal (see pg. 17546 “…At a particular stage, the local laser heating can break the atomic bonds and destabilize the crystal lattice by knocking out the Se atoms from the In2Se3 structure, leaving behind stable Se vacancies as active nucleation sites. It should be noted that the ToF-SIMS result shows no evidence of selenium oxide, indicating that Se tends to desorb from the surface, leaving behind nucleation sites for O-absorption, as creation of a Se vacancy is energetically favorable (∼20−30 meV) as compared to generating an In vacancy (∼480 meV).36,37 Consequently, oxygen molecules diffuse in and occupy the Se vacancies to form a stabilized In−O bond through oxidation.”).
Regarding Claim 9, Mukherjee discloses: The system according to claim 7,
Mukherjee further discloses:
wherein said ferroelectric crystal comprises In2Se3, and said semiconductor crystal comprises In203 (see abstract).
Regarding Claim 15, Mukherjee discloses:
An integrated circuit (see Abstract, see Conclusions “…The method demonstrated enables the development of versatile in-plane 2D heterojunction devices for wafer scale integrated electronics and optoelectronics applications.”), comprising the system according to claim 1 (see above), and a plurality of contacts (see Fig. 5(b)) in electrical communication with said heterojunction (In2Se3/In2O3).
Regarding Claim 17, Mukherjee discloses:
An appliance system, comprising the integrated circuit according to claim 15 , said appliance system being selected from the group consisting of a diode system, a transistor system, a memory system, an imaging system, a display system, a projector display system, an identification tag system, a sensor, and a photodetector (see abstract, see pg 17549 “The substantial barrier for hole transport from In2Se3 to In2O3 and small barrier for electron transport hinder the photocarrier recombination, which is advantageous for photodetectors or solar cell applications.”, and see Conclusions).
Claim 4 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Photodetector based on heterostructure of two-dimensional WSe2/In2Se3 Liu et al (herein “Liu”).
Regarding Claim 4, Mukherjee discloses:
A monolithic solid state system (see generally Abstract, Results and Discussion, and Conclusions disclosing a photodetector comprising a heterojunction between WSe2/In2Se3), comprising a ferroelectric crystal (In2Se3, see abstract) and a semiconductor crystal (WSe2, see abstract) arranged laterally to define a nanolayer (see Results and Discussion: “Multilayer WSe2 and multilayer In2Se3 were exfoliated from bulk materials and then put onto a Si wafer covered by a 300 nm SiO2 layer to fabricate vdW stacked heterostructure devices.”) having a heterojunction between said crystals, said nanolayer having a thickness of at most 500 nm (see page 2, “…in the particular device shown in figure 1(b), the thicknesses of the WSe2 and In2Se3 are 5nm and 22nm, respectively”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Scalable Integration of Coplanar Heterojunction Monolithic Devices on Two Dimensional In2Se3 Mukherjee et al Optical control of polarization in ferroelectric heterostructures Li et al (herein “Li”).
Regarding Claim 5, Mukherjee discloses: The system according to claim 1,
Mukherjee does not explicitly disclose:
wherein said ferroelectric crystal is polarized such that an internal electric field induced by said polarization comprises a component perpendicular to said heterojunction.
However, in analogous art, Li teaches:
wherein said ferroelectric crystal is polarized such that an internal electric field induced by said polarization comprises a component perpendicular to said heterojunction (see generally Abstract and Introduction, specifically “In this paper, we demonstrate optically induced polarization switching in BaTiO3-based ferroelectric heterostructures utilizing a two-dimensional narrow-gap semiconductor MoS2 as a top electrode. This effect is attributed to the redistribution of the photo-generated carriers and screening charges at the MoS2/BaTiO3 interface. Specifically, a two-step process, which involves formation of intra-layer excitons during light absorption followed by their decay into inter-layer excitons, results in the positive charge accumulation at the interface forcing the polarization reversal from the upward to the downward direction. Theoretical modeling of the MoS2 optical absorption spectra with and without the applied electric field provides quantitative support for the proposed mechanism. It is suggested that the discovered effect is of general nature and should be observable in any heterostructure comprising a ferroelectric and a narrow gap semiconductor.” and “The characteristic feature of the ferroelectric materials is the presence of the reversible spontaneous polarization that can be switched by an electric field1. Switchability of ferroelectric polarization enables control of a number of polarization-dependent electronic, mechanical, optical, and other functional properties, which forms the basis of their device applications2.”).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Lee to the device disclosed by Mukherjee and polarize the ferroelectric crystal such that the electric field is perpendicular to the heterojunction between the ferroelectric crystal and the semiconductor crystal. Mukherjee is silent to the teachings of the polarization, and Li teaches that doing so “enables control of a number of polarization-dependent electronic, mechanical, optical, and other functional properties, which forms the basis of their device applications.” in reference to the polarization of the ferroelectric crystal, therefore, a person of ordinary skill would be motivated to seek the teachings of Lee to form a functional device.
Regarding Claim 16, Mukherjee discloses: The integrated circuit according to claim 15,
Mukherjee does not explicitly disclose:
comprising an electrode positioned to apply an electric field to said ferroelectric crystal so as polarize said ferroelectric crystal along a direction parallel to said nanolayer, wherein said applied electric field has a component perpendicular to said nanolayer.
However, in analogous art, Li teaches:
comprising an electrode positioned to apply an electric field to said ferroelectric crystal so as polarize said ferroelectric crystal along a direction parallel to said nanolayer, wherein said applied electric field has a component perpendicular to said nanolayer (see generally Abstract and Introduction, specifically “In this paper, we demonstrate optically induced polarization switching in BaTiO3-based ferroelectric heterostructures utilizing a two-dimensional narrow-gap semiconductor MoS2 as a top electrode. This effect is attributed to the redistribution of the photo-generated carriers and screening charges at the MoS2/BaTiO3 interface. Specifically, a two-step process, which involves formation of intra-layer excitons during light absorption followed by their decay into inter-layer excitons, results in the positive charge accumulation at the interface forcing the polarization reversal from the upward to the downward direction. Theoretical modeling of the MoS2 optical absorption spectra with and without the applied electric field provides quantitative support for the proposed mechanism. It is suggested that the discovered effect is of general nature and should be observable in any heterostructure comprising a ferroelectric and a narrow gap semiconductor.” and “The characteristic feature of the ferroelectric materials is the presence of the reversible spontaneous polarization that can be switched by an electric field1. Switchability of ferroelectric polarization enables control of a number of polarization-dependent electronic, mechanical, optical, and other functional properties, which forms the basis of their device applications2.” Emphasis added).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Lee to the device disclosed by Mukherjee and polarize the ferroelectric crystal such that the electric field is perpendicular to the heterojunction between the ferroelectric crystal and the semiconductor crystal. Mukherjee is silent to the teachings of the polarization, and Li teaches that doing so “enables control of a number of polarization-dependent electronic, mechanical, optical, and other functional properties, which forms the basis of their device applications.” in reference to the polarization of the ferroelectric crystal, therefore, a person of ordinary skill would be motivated to seek the teachings of Lee to form a functional device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is (571) 272-2686. The examiner can normally be reached M-F 8:00a-4:30p.
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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