DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The indicated allowability of claims 19 and 20 is withdrawn in view of the newly discovered reference to Keeth (U.S. Patent Number 6,111,446). Rejections based on the newly cited reference follow.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Keeth (U.S. Patent Number 6,111,446).
Regarding Claim 19, Keeth discloses a clock converting circuit (Figure 6, item 400) comprising:
a first switch (Figure 6, item 410; i.e., a multiplexer) connected between a first input node (Figure 6, see input to multiplexer 410) and a first node (Figure 6, see output from multiplexer 410), and configured to receive a first input clock signal (Figure 6, item CLK) at the first input node and operate in response to a first logic state of a second input clock signal (Figure 6, item CLK90, Column 6, lines 2-4; i.e., multiplexer 410 is activated in response to the CLK90 being a high state [the claimed “first logic state”]);
a second switch (Figure 6, item 414) connected between a ground node and the first node, and configured to operate in response to a second logic state of the second input clock signal (Column 6, lines 2-4; i.e., although the reference does not explicitly state that the second switch 414 is activated when the second clock CLK90 is in a low state [the claimed “second logic state”], this step is implied because the second switch 414 is activated at the opposite clock timing of the multiplexer 410); and
a third switch (Figure 6, item 412; i.e., another multiplexer) connected between a second input node (Figure 6, see input to multiplexer 412) and a second node (Figure 6, see output from multiplexer 412), and configured to receive the second input clock signal at the second input node and operate in response to a second logic state of the first input clock signal (Column 6, lines 7-10; i.e., the transistor 416 is said to be activated based on a high state of first clock signal CLK; further, the third switch 412, which receives a control input from first clock CLK, is activated at the opposite clock timing of the transistor 416; this would indicate that the third switch 412 is activated when the first clock signal CLK is at a low state [the claimed “second logic state of the first input clock signal”]).
Regarding Claim 20, Keeth discloses a first inverter (Figure 6, see second inverter located at the output of multiplexer 410) connected between the first node and a first output node (Figure 6, item 418) that outputs an output clock signal (Figure 6, item CLK0); and a second inverter (Figure 6, see second inverter located at the output of multiplexer 412) connected between the second node and a second output node that outputs an inverted output clock signal (Figure 6, item CLK1*; i.e., as shown in Figure 7, the output clock CLK1* is inverted at least at certain points in time with respect to the output clock CLK0), wherein a phase of the second input clock signal is delayed by 90 degrees with respect to a phase of the first input clock signal (Column 5, lines 16-18), and wherein the first logic state indicates a logical low level and the second logic state indicates a logical high level (Column 6, lines 2-4; i.e., although the reference appears to state that the first logic state is high and the second logic state is low, it would have been a matter of obvious design choice to reverse these states [it would have been within the level of one of ordinary skill in the art to update the circuitry in Figure 6, e.g., by adding or removing certain inverters to make this change]).
Allowable Subject Matter
Claims 1-14 and 16-18 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 1, the prior art of record does not teach “wherein a voltage level of the power voltage of the power node is higher than a voltage level of a ground node, wherein the first PMOS transistor is configured to generate a voltage waveform at the first node with the first switch in response to the second input clock signal, and wherein a duty of the voltage waveform at the first node is longer than a duty of the first input clock signal.”
Regarding Claim 16, the prior art of record does not teach “a clock converting circuit comprising: a first clock circuit configured to generate a first output clock signal based on a first input clock signal and a second input clock signal; a second clock circuit configured to generate a second output clock signal based on the second input clock signal and a third input clock signal; a third clock circuit configured to generate a third output clock signal based on the third input clock signal and a fourth input clock signal; and a fourth clock circuit configured to generate a fourth output clock signal based on the first input clock signal and the fourth input clock signal”, in conjunction with the other limitations in the claim. Keeth discloses a first and second clock circuit as claimed, but does not disclose a third and fourth clock circuit as claimed.
All claims that are not specifically addressed are allowable due to a dependency.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN, ESQ. whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175