DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on February 3, 2026.
Claims 1-19 are pending. Claims 1 and 17 are amended. Claims 18 and 19 are added. Claims 1 and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Applicant’s Remarks, filed on February 3, 2026, with respect to claims 1-19 have been fully considered and are persuasive. The rejections of claims 1-19 have been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Shikata et al. (US 20170337969) in view of Lei et al. (US 20150371703), Dong et al. (US 20140254283) and Chen et al. (US 20140254262).
Regarding independent claim 1, Shikata et al. disclose a semiconductor memory device [see Fig. 29] comprising:
a plurality of word lines [Fig. 29: WL0 to WL7] each extending in a first direction and a second direction, the word lines being laminated in a third direction, and the first to third directions crossing one another [see Fig. 29, para. 246];
a first select gate line provided above an uppermost one of the word lines in the third direction, the first select gate line extending in the first direction and the second direction [see Fig. 28 and 29, para. 250-251];
a plurality of bit lines provided above the first select gate line in the third direction, each of the bit lines extending in the second direction, and the bit lines including first to fourth bit lines arranged in order along the first direction [see Fig. 28 and 29, para. 247 as well as para. 253];
a plurality of memory pillars connected to the bit lines, respectively, and penetrating the first select gate line and the word lines in the third direction, the memory pillars including first to fourth memory pillars arranged in order along the second direction, and the first to fourth memory pillars being connected to the first to fourth bit lines, respectively [see Fig. 29, para. 253 and 255];
a plurality of memory cells formed at intersections of the word lines and the memory pillars [see Fig. 28 and 29, para. 44 as well as para. 49], and the memory cells including a first group of memory cells gates of which are collectively connected to one of the word lines, the first group of memory cells including first to fourth memory cells connected to the first to fourth bit lines, respectively [see Fig. 28, para. 245-247].
However, Shikata et al. are silent with respect to each of the memory cells being capable of storing data using n levels of threshold voltages, where n is an integer of 8 or more, the n levels of threshold voltages comprising a first level, a second level higher than the first level, a third level higher than the second level, a fourth level higher than the third level, a fifth level higher than the fourth level, a sixth level higher than the fifth level, a seventh level higher than the sixth level, and an eighth level higher than the seventh level; and
a controller configured to perform a first write operation and a second write operation on the first group of memory cells, the first write operation including i program operations and j verify operations, where i and j are natural numbers, the second write operation being performed after the first write operation, and the second write operation including an internal data load operation, k program operations, and I verify operations, where k is a natural number greater than I and I is a natural number greater than j,
wherein:
the first write operation is performed using a first set of write data including two or more pages,
the second write operation to the first to fourth memory cells is performed using a second set of write data including two or more pages, and
one of the two or more pages of the first set of write data is the same as one of the two or more pages of the second set of write data.
Lei et al. teach each of the memory cells being capable of storing data using n levels of threshold voltages, where n is an integer of 8 or more [see Figs. 7A-7E, each memory cell stores data for three different pages: a lower page (L), a middle page (M) and an upper page (U). Eight data states may be depicted by repeating the threshold voltage distributions 700, 702, 704, 706, 708, 710, 712 and 7 from FIG. 7A, para. 69] the n levels of threshold voltages comprising a first level, a second level higher than the first level, a third level higher than the second level, a fourth level higher than the third level, a fifth level higher than the fourth level, a sixth level higher than the fifth level, a seventh level higher than the sixth level, and an eighth level higher than the seventh level [see Fig. 7A, para. 69-70]; and
a controller configured to perform a first write operation [see Fig. 7D, First Fine programming pass, para. 74] and a second write operation on the first group of memory cells [see Fig. 7E, Second Fine programming pass, para. 75], the second write operation being performed after the first write operation [First Fine programming pass is performed on an entire block of memory cells in the first phase, and then the Second Fine programming pass is performed on the same block in the second phase, para. 82],
wherein:
the first write operation is performed using a first set of write data including two or more pages [the LM-Foggy-Double Fine multi-pass programming technique requires data from all three pages as program target data for the Foggy pass, the First Fine pass and the Second Fine pass, para. 82],
the second write operation to the first to fourth memory cells is performed using a second set of write data including two or more pages [the LM-Foggy-Double Fine multi-pass programming technique requires data from all three pages as program target data for the Foggy pass, the First Fine pass and the Second Fine pass, para. 82], and
one of the two or more pages of the first set of write data is the same as one of the two or more pages of the second set of write data [the LM-Foggy-Double Fine multi-pass programming technique requires data from all three pages as program target data for the Foggy pass, the First Fine pass and the Second Fine pass, para. 82].
Dong et al. teach a controller configured to perform a first write operation and a second write operation on the first group of memory cells [see Fig. 5A-5C, Dong et al. describe a two-pass programming operation in which lower and upper pages of data are written in first and second passes, respectively, using two-bit, four-level memory cells, para. 98-100], the first write operation including i program operations and j verify operations, where i and j are natural numbers [see Fig. 12A, para. 138], the second write operation being performed after the first write operation, and the second write operation including k program operations, and I verify operations [see Fig. 13A, para. 146], where k is a natural number greater than I and I is a natural number greater than j [the second pass of a two-pass programming operation has a series of program pulses PP1 to PP14 and verify pulses, while the first pass of a two-pass programming operation has a series of program pulses PP1 to PP8 and verify pulse].
Chen et al. further teach techniques for performing Internal Data Load and preserving lower-page data in data latches [para. 37-38].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Lei et al., Dong et al. and Chen et al. to the teaching of Shikata et al. such that modifying the NAND device of Shikata et al. to incorporate Chen et al.’s Internal Data Load into Lei et al.’s second write operation (Second Fine programming pass) that is performed with more program and verify operations than the first write operation (First Fine programming pass) as taught by Dong et al. to tighten the threshold voltage distribution and reduce program disturb in multi-level NAND flash memory [see Dong et al.’s para. 51-52].
Regarding claim 2, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 1.
Furthermore, Lei et al. disclose wherein:
the first write operation is performed from a state where a threshold voltage of each of the first group of the memory cells is the first level [a memory cell must be programmed from the erased state, para. 31. See Fig. 8B, at step S1 the LM programming pass is performed on WL0. After step S1 is completed, the memory cells on WL0 have been programmed to the LM-state, and memory cells on WL1, WL2, WL3, WL4 remain in the erase Er-state, para. 86], and
the second write operation is performed after the first write operation has been performed [First Fine programming pass is performed on an entire block of memory cells in the first phase, and then the Second Fine programming pass is performed on the same block in the second phase, para. 82].
Regarding claim 3, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 2.
Furthermore, Dong et al. disclose wherein:
the i program operations of the first write operation comprise a first program operation for increasing the threshold voltage of one of the first group of the memory cells to be higher than the first level, while leaving the threshold voltage of another one of the first group of the memory cells to be not increased [see Fig. 5B, para. 99], and
the k program operations of the second write operation comprise a second program operation for increasing the threshold voltage of the one of the first group of the memory cells toward one of the fifth to eighth levels [see Fig. 6D, the program is divided into eight states. A subsequent pass applies program loops that drive the programmed cells upward into E, F or G state, para. 103].
Regarding claim 4, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 3.
Furthermore, Dong et al. disclose wherein the k program operations of the second write operation further comprise a third program for increasing the threshold voltage of the another one of the first group of the memory cells toward one of the second to third levels [see Fig. 6D, the program is divided into eight states. A subsequent pass applies program loops that drive the programmed cells upward into A, B or C state, para. 103].
Regarding claim 5, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 4.
Furthermore, Dong et al. disclose in the second write operation, the second program operation is performed after the third program operation [the second program operation is for increasing the threshold voltage toward one of the fifth to eight levels, the third program operation is for increasing the threshold voltage toward one of the second to third levels so in order to program a memory cell to increase its threshold voltage towards data state “G” like in Figure 6D, the second program operation is performed after the third program operation].
Regarding claim 6, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 1.
Furthermore, Dong et al. disclose wherein the controller is configured to perform, after the second write operation to the first group of memory cells has been performed [each program pulse is followed by a read back (verify) to determine if the memory cell has been programmed to the desired memory state, para. 72]:
a first read operation to the first group of memory cells to read one of the three pages of data [a lower page latch is flipped when a lower page bit is sensed, evidencing a read that returns a single page, para. 74];
a second read operation to the first group of memory cells to read another one of the three pages of data [a middle page latch is used when the middle page bit is stored in an associated memory cell, para. 74]; and
a third read operation to the first group of memory cells to read still another one of the three pages of data [an upper page latch is disclosed, evidencing a separate read that recovers the upper page, para. 74].
Regarding claim 7, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 6.
Furthermore, Dong et al. disclose wherein in the first read operation, one kind of read voltage is applied to the one of the word lines [para. 97].
Regarding claim 8, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 7.
Furthermore, Dong et al. disclose wherein in the second read operation, p kinds of read voltage are applied to the one of the word lines, where p is an integer equal to or greater than 3 [read reference voltages which are between the distributions are used for reading data from the memory cells, para. 97. In Fig. 6C, the middle page has four stages so there are three read reference voltages which are between the distributions are used for reading data from the memory cells, para. 102].
Regarding claim 9, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 8.
Furthermore, Dong et al. disclose wherein in the third read operation, q kinds of read voltage are applied to the one of the word lines, where q satisfies the equation [read reference voltages which are between the distributions are used for reading data from the memory cells, para. 97. In Fig. 6D, the upper page has eight stages so there are seven read reference voltages which are between the distributions are used for reading data from the memory cells, para. 102]:
1+p+q=7.
Regarding claim 10, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 9.
Furthermore, Dong et al. disclose wherein the controller is configured to perform a program operation such that while a program voltage is applied to the word line [each program-verify iteration has a program portion in which a program pulse (PP) is applied to the control gates of the memory cells via a selected word line, para. 129], a first voltage is applied to the bit line connected to the memory cell as a first program target [in fast programming mode, Vbl =0V, para. 142], a second voltage higher than the first voltage is applied to the bit line connected to the memory cell as a second program target [in slow programming mode, Vbl =0.8V, para. 142], and a third voltage higher than the second voltage is applied to the bit line connected to the memory cell as a program-inhibited target [during the program pulse of each program-verify iteration of the program-verify iterations for the set of transistors, a respective drain voltage of the transistor (e.g., Vbl) is set at a lockout level (Vdd), para. 119].
Regarding claim 11, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 10.
Furthermore, Dong et al. disclose wherein the controller is configured to execute the verify operation for the second state in a next program loop [A- and B-state verify pulses (e.g., VPab) at levels of Vva_lo and Vvb_lo, respectively, may be applied after each of PP4 to PP6, para. 130; during PV3 of the second pass, Nlockout (FIG. 13B) for the B-state (curve 1312) transitions above Ns to trigger the step up in Vvb_lo in the following program-verify iterations (PV4), para. 148] in response to a number of the memory cells having a threshold voltage lower than the verify low voltage becoming lower than or equal to a first value in the verify operation for the first state [see Fig. 9B, step 930 sensed Vth, steps 934-936 count how many cells still fall low verify level, para 120-123].
Regarding claim 12, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 11.
Furthermore, Dong et al. disclose wherein in the program loop in which the verify operation for the first state is executed, the controller does not execute the verify operation for the remaining states [Fig. 9B, the controller repeats the loop without performing any verify for higher states until the lock out count condition of step 936 is satisfied, para. 118-124].
Regarding claim 13, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 11.
Furthermore, Dong et al. disclose wherein in the program loop in which the verify operation for the second state is executed, the controller does not execute the verify operation for the remaining states [Fig. 9B, the controller repeats the loop without performing any verify for any other states until the lock out count condition of step 936 is satisfied, para. 118-124].
Regarding claim 14, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 11.
Furthermore, Dong et al. disclose wherein:
the first verify level corresponds to a verify low voltage of the first state [Fig. 11C, Vva_init, para. 133], and
the second verify level corresponds to a verify high voltage of the first state [Fig. 11C, Vva_mx, para. 133].
Regarding claim 15, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 14.
Furthermore, Dong et al. disclose wherein:
the memory cells are each configured to store third data in a case where the threshold voltage is included in a third state higher than the second state [Fig. 11C, curve 1126, para. 135],
the verify low voltage and the verify high voltage are set in the second state [Fig. 11C, Vvb_init and Vvb_mx, para. 134], and
the controller is configured to execute the verify operation for the third state in a next program loop, in response to the number of the memory cells having a threshold voltage lower than the verify low voltage becoming lower than or equal to a second value in the verify operation for the second state [In para. 135, Dong et al. described once the B state loop reaches its count criterion (PV9), the next program-verify iterations begin stepping up and verifying the C state. In Fig. 9B, step 930 sensed Vth, steps 934-936 count how many cells still fall low verify level, para 120-123].
Regarding claim 16, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 15.
Furthermore, Dong et al. disclose wherein:
the first verify level corresponds to the verify low voltage of the first state [Fig. 11C, Vva_init, para. 133],
the second verify level corresponds to the verify high voltage of the first state [Fig. 11C, Vva_mx, para. 133],
the third verify level corresponds to the verify low voltage of the second state [Fig. 11C, Vvb_init, para. 134], and
the fourth verify level corresponds to the verify high voltage of the second state [Fig. 11C, Vvb_mx, para. 134].
Regarding claim 19, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 1.
Furthermore, Shikata et al. discloses further comprising:
a second select gate line provided above the uppermost one of the word lines in the third direction, the second select gate line being arranged with the first select gate line in the second direction, and the second gate line extending in the first direction and the second direction [see Fig. 28 and 29, select gate lines SGS and SGD are above the word line stack (wiring layers 52), para. 250-251].
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Shikata et al. (US 20170337969) in view of Dong et al. (US 20140254283).
Regarding independent claim 17, Shikata et al. disclose a semiconductor memory device [see Fig. 29] comprising:
a plurality of word lines [Fig. 29: WL0 to WL7] each extending in a first direction and a second direction, the word lines being laminated in a third direction, and the first to third directions crossing one another [see Fig. 29, para. 246];
a first select gate line provided above an uppermost one of the word lines in the third direction, the first select gate line extending in the first direction and the second direction [see Fig. 28 and 29, para. 250-251];
a plurality of bit lines provided above the first select gate line in the third direction, the bit lines being arranged along the first direction, and each of the bit lines extending in the second direction [see Fig. 28 and 29, para. 247 as well as para. 253];
a plurality of memory pillars connected to the bit lines, respectively, and penetrating the first select gate line and the word lines in the third direction [see Fig. 29, para. 253 and 255];
a plurality of memory cells formed at intersections of the word lines and the memory pillars [see Fig. 28 and 29, para. 44 as well as para. 49], each of the memory cells being capable of storing data using n levels of threshold voltages, where n is an integer of 8 or more, the n levels of threshold voltages comprising a first level, a second level higher than the first level, a third level higher than the second level, a fourth level higher than the third level, a fifth level higher than the fourth level, a sixth level higher than the fifth level, a seventh level higher than the sixth level, and an eighth level higher than the seventh level [see Fig. 22, para. 197], the memory cells including a first group of memory cells gates of which are collectively connected to one of the word lines, and the first group of memory cells including first to fourth memory cells [see Fig. 28, para. 245-247].
However, Shikata et al. are silent with respect to when performing a write operation including a plurality of program operations and a plurality of verify operations to the first to fourth memory cells from a state where a threshold voltage of each of the first to fourth memory cells is the first level;
the plurality of program operations comprise:
a first program operation for increasing the threshold voltage of the first memory cell toward the second level with a first magnitude;
a second program operation for increasing the threshold voltage of the second memory cell toward the second level with a second magnitude lower than the first magnitude;
a third program operation for increasing the threshold voltage of the third memory cell toward the third level with a third magnitude; and
a fourth program operation for increasing the threshold voltage of the fourth memory cell toward the third level with a fourth magnitude lower than the third magnitude, and
wherein the plurality of verify operations comprise:
a first verify operation for a first verify level lower than the second level;
a second verify operation for a second verify level between the first verify level and the second level;
a third verify operation for a third verify level lower than the third level; and
a fourth verify operation for a fourth verify level between the third verify level and the third level.
Dong et al. teach when performing a write operation including a plurality of program operations and a plurality of verify operations to the first to fourth memory cells from a state where a threshold voltage of each of the first to fourth memory cells is the first level [FIGS. 4A and 4B depict an example one-pass programming operation in which lower and upper pages of data are written concurrently. A programming pass, or programming operation, is generally meant to encompass a sequence of program-verify iterations which are performed until the threshold voltages of a set of selected memory cells reach one or more respective verify levels of respective target data states. Some of the memory cells are not programmed and remain in the erased state while others are programmed to higher target data states, para. 93-94];
the plurality of program operations comprise:
a first program operation for increasing the threshold voltage of the first memory cell toward the second level with a first magnitude; a second program operation for increasing the threshold voltage of the second memory cell toward the second level with a second magnitude lower than the first magnitude [see Fig. 4A-4B, Dong et al. disclose a program option which uses a slow programming mode may be referred to as a "quick pass write" (QPW) technique. When QPW is used, lower verify levels (VvaL, VvbL or VvcL) are defined such that the memory cells enter a slow programming mode (e.g., by raising the associated bit line voltages applied during the program pulse) when their Vth is between the lower verify level and the higher, lockout verify level of a respective target data state. It reduces the per pulse programming increment. Thus, cells on the same pass at the same second level (state A) can proceed at different rates depending on whether they have crossed the lower verify level, para. 95];
a third program operation for increasing the threshold voltage of the third memory cell toward the third level with a third magnitude; and a fourth program operation for increasing the threshold voltage of the fourth memory cell toward the third level with a fourth magnitude lower than the third magnitude [see Fig. 4A-4B, the same slow vs fast programming mode applied for higher target states (state B) so some cells program slower (reduced magnitude) after crossing the lower verify level for that state, while other cells still program faster before that point, para. 95], and
wherein the plurality of verify operations comprise:
a first verify operation for a first verify level [Fig. 4: VvaL] lower than the second level; a second verify operation for a second verify level [Fig. 4: Vva_mx] between the first verify level and the second level [see Fig. 4A-4B, lower verify level (VvaL) is defined such that the memory cells enter a slow programming mode when their Vth is between the lower verify level and the higher, lockout verify level (Vva_mx) of a respective target data state (state A), para. 94-95];
a third verify operation for a third verify level lower than the third level; and a fourth verify operation for a fourth verify level between the third verify level and the third level [see Fig. 4A-4B, lower verify level (VvbL) is defined such that the memory cells enter a slow programming mode when their Vth is between the lower verify level and the higher, lockout verify level (Vvb_mx) of a respective target data state (state B), para. 94-95].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Dong et al. to the teaching of Shikata et al. such that Shikata et al.’s multi-page write sequence is executed with a program option which uses a slow programming mode may be referred to as a "quick pass write" (QPW) technique as taught by Dong et al. to tighten the threshold voltage distribution and reduce program disturb in multi-level NAND flash memory [see Dong et al.’s para. 51-52].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Shikata et al. (US 20170337969) in view of Lei et al. (US 20150371703), Dong et al. (US 20140254283) and Chen et al. (US 20140254262) as applied to claim 1 above, and further in view of Li (US 20120155166).
Regarding claim 18, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. teach the limitations with respect to claim 1.
However, Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. are silent with respect to wherein another one of the two or more pages of the first set of write data is different from another one of the two or more pages of the second set of write data.
Li teaches wherein another one of the two or more pages of the first set of write data is different from another one of the two or more pages of the second set of write data [the top and middle line are for the first two pages written into the word line and are the counterpart of FIGS. 7B-7C and then the third or top page resolves the distributions into full eight states, para. 97].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Li to the teaching of Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. such that modifying the multi-pass programming method of Shikata et al. in combination with Lei et al., Dong et al. and Chen et al. to use lower plus middle page data in an earlier write stage and upper page data in a later write stage as taught by Li to improve programming accuracy and reduce data transfer burden.
Conclusion
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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