DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A (Fig. 2, claims 1-7, 10, and 12-18) in the reply filed on 12/11/2025 is acknowledged.
However, claim 14 below reads on Figure 8 as recited and as discussed in paragraph [0092] of the specification as filed.
14. The image sensor package of claim 13, wherein an outer side wall of the adhesive layer is recessed concavely toward the protrusion.
Accordingly, claim 14 is withdrawn from consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 4-7, 10, 12, 13, 15-18 is/are rejected under 35 U.S.C. 103 as being obvious over U.S. Patent Application Publication No. 2022/0077209 (Kim) or unpatentable over U.S. Patent Application Publication No. 2009/0267170 (Chien), in view of JP Publication No. 01-004031 (Karasawa).
Kim discloses (at least Fig. 4)
1. A semiconductor package comprising:
a package substrate 500;
a semiconductor chip 100 disposed on the package substrate 500;
a transparent substrate 400 disposed on the semiconductor chip 100; and
an adhesive layer 200 that is disposed between the semiconductor chip 100 and the transparent substrate 400, the adhesive layer 200 being configured to block light (polymer [0050]),
wherein the transparent substrate 400 comprises:
a first lower side 401 that faces the semiconductor chip 100,
a second lower side 402 that faces the semiconductor chip 100 and is disposed above the first lower side 401.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Chien discloses (at least Fig. 4B)
1. A semiconductor package comprising:
a package substrate 301 / 315;
a semiconductor chip 302 disposed on the package substrate 301 / 315;
a transparent substrate 340 disposed on the semiconductor chip 302; and
an adhesive layer 408-A that is disposed between the semiconductor chip 302 and the transparent substrate 340, the adhesive layer 408-A being configured to block light (epoxy spacer paste [0013]),
wherein the transparent substrate 340 comprises:
a first lower side 408-B that faces the semiconductor chip 302,
a second lower side 342 that faces the semiconductor chip 302 and is disposed above the first lower side 408-B.
Kim or Chien fail to disclose
a first inner side wall that connects the first lower side and the second lower side, and wherein the adhesive layer is in contact with the second lower side and the first inner side wall.
Karasawa teaches
A semiconductor package comprising:
a transparent substrate 19 comprising:
a first inner side wall (near 16) that connects the first lower side (near 10) and the second lower side (near 7), and wherein the adhesive layer 13 is in contact with the second lower side (near 7) and the first inner side wall (near 16).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a transparent substrate having a first inner side wall, a first lower side, and a second lower side in Kim or Chien. The motivation would be to provide a small-sized solid sate imaging sensing element that can be mass-produced as taught by Karasawa. Further, the configuration of the claimed transparent substrate is a matter of choice or routine experimentation which a person of ordinary skill in the art would have found obvious. See MPEP 2144.04, 2144.05.
Kim discloses [0030] / Chien discloses ([0013]-[0015])
2. The semiconductor package of claim 1, wherein the semiconductor chip 100 or 302 is an image sensor chip that comprises a plurality of microlenses 160 or 307 disposed below the first lower side 401 or 408-B of the transparent substrate 400 or 340.
Kim discloses / Chien discloses
4. The semiconductor package of claim 2, wherein the adhesive layer 200 or 408-A does not overlap the plurality of microlenses 160 or 307.
Kim discloses / Chien discloses
5. The semiconductor package of claim 1, wherein the adhesive layer 200 (polymer) or 408-A (epoxy paste) is configured to have a lower light reflectivity and a higher light absorptivity than the transparent substrate 400 (glass or plastic) or 340 (glass).
Karasawa teaches
6. The semiconductor package of claim 1, wherein the second lower side (near 7) surrounds the first lower side (near 10) from a plan viewpoint.
Karasawa teaches
7. The semiconductor package of claim 1, wherein a side wall of the adhesive layer 13 that in contact with the first inner side (near 16) wall is flat.
Kim discloses / Chien discloses
10. The semiconductor package of claim 1, wherein an upper side of the transparent substrate 400 or 340 is flat.
Karasawa teaches
12. The semiconductor package of claim 1, wherein the adhesive layer 13 is in contact with an upper side of the semiconductor chip 6.
Kim discloses (at least Fig. 4)
13. An image sensor package comprising:
a package substrate 500;
an image sensor chip 100 disposed on the package substrate 500, the image sensor chip 100 comprising a plurality of microlenses 160;
a transparent substrate 400 disposed on the image sensor chip 100; and
an adhesive layer 200 disposed between the image sensor chip 100 and the transparent substrate 400, the adhesive layer 200 configured to block light (polymer).
Chien discloses (at least Fig. 4B)
13. An image sensor package comprising:
a package substrate 301 / 315;
an image sensor chip 302 disposed on the package substrate 301 / 315, the image sensor chip 302 comprising a plurality of microlenses 307;
a transparent substrate 340 disposed on the image sensor chip 302; and
an adhesive layer 408-A disposed between the image sensor chip 302 and the transparent substrate 340, the adhesive layer 408-A configured to block light (epoxy paste).
Kim or Chien fail to disclose
wherein the transparent substrate comprises a protrusion protruding toward the image sensor chip in a central region of the transparent substrate that overlaps the plurality of microlenses, and wherein the adhesive layer is in contact with an upper side of the image sensor chip, and the adhesive layer is in contact with a side surface of the protrusion to surround the protrusion.
Karasawa teaches
A semiconductor package comprising:
wherein the transparent substrate 19 comprises
a protrusion (near 10) protruding toward the image sensor chip 6 in a central region of the transparent substrate 19 that overlaps the plurality of microlenses (not shown), and
wherein the adhesive layer 13 is in contact with an upper side of the image sensor chip 6, and the adhesive layer 13 is in contact with a side surface of the protrusion (near 10) to surround the protrusion (near 10).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a transparent substrate having a protrusion in Kim or Chien. The motivation would be to provide a small-sized solid state imaging sensing element that can be mass-produced as taught by Karasawa. Further, the configuration of the claimed transparent substrate is a matter of choice or routine experimentation which a person of ordinary skill in the art would have found obvious. See MPEP 2144.04, 2144.05.
The combination of references fails to teach
15. The image sensor package of claim 13, wherein a width of the protrusion is greater than or equal to a width of a region in which the plurality of microlenses are disposed.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to determine the optimum width of the protrusion in Kim or Chien. The motivation would be the width of the protrusion of the claimed transparent substrate is a matter of choice or routine experimentation which a person of ordinary skill in the art would have found obvious. See MPEP 2144.04, 2144.05.
Kim discloses
16. The image sensor package of claim 13, further comprising
a molding film 300 that surrounds the image sensor chip 100, the transparent substrate 400, and the adhesive layer 200
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a molding film in Chien. The motivation would be to protect the package as a matter of choice or routine experimentation which a person of ordinary skill in the art would have found obvious. See MPEP 2144.04, 2144.05.
Karasawa teaches
17. The image sensor package of claim 13, wherein the adhesive layer 13 does not overlap a lower side of the protrusion.
Kim or Chien disclose
18. The image sensor package of claim 13, wherein the adhesive layer 200 or 408-A is opaque, and the adhesive layer 200 or 408-A is configured to have a lower light reflectivity and a higher light absorptivity than the transparent substrate 400 or 340.
Allowable Subject Matter
Claim 3 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the cited references discloses or teaches
3. The semiconductor package of claim 2, wherein:
the first inner side wall does not overlap the plurality of microlenses, and a distance between an outermost microlens among the plurality of microlenses and the first inner side wall is 50 m or less.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication Nos. 2004/0043540 (Kinsman), 2004/0251510 (You), 2006/0255253 (Hsiao), 2006/0256222 (Tsai), 2012/0211852 (Iwafuchi), 2016/0181479 (Kim), 2017/0343831 (Bakin), 2018/0136434 (Alasirniö), and JP-2002-009206 (Ando) teach a package substrate having an image sensor chip, an adhesive, and a transparent substrate with a protrusion.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893