DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, claim 2 recites the semiconductor layer. Claim 1, from which claim 2 depends, recites a first semiconductor layer and a second semiconductor layer but not a semiconductor layer. Therefore, the semiconductor layer lacks a proper antecedent basis. Further, as a semiconductor layer has not been recited earlier, it is unclear to which the semiconductor layer refers. Appropriate correction is required to clarify the language and resolve the antecedent issue. For purposes of compact prosecution, the examiner interprets the semiconductor layer to be a first semiconductor layer.
Claim 3 is also rejected as it depends on claim 2.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,2 and 6-8 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kawaguchi et al. (US20170110548A1).
Regarding claim 1, Fig.6 of Kawaguchi teaches a method of fabricating a semiconductor wafer to reduce or counteract defects, the method comprising:
forming a substrate layer S (para.0052);
forming a nucleation layer (para.0059, wherein a nucleation layer, may be provided between the substrate S and the channel layer CH) superjacent the substrate layer S;
forming a first semiconductor layer CH (para.0059), superjacent the nucleation layer, to at least a first thickness;
reducing a thickness of the first semiconductor layer CH (para.0075 wherein in a thickness is reduced at the middle, as shown in Fig.6, from first thickness to second thickness) to at least a second thickness while the substrate layer S remains coupled with the nucleation layer (para.0059);
forming a second semiconductor layer BA (para.0070) superjacent the first semiconductor layer CH; and
forming a heterostructure (para.0070, wherein an AlGaN (Al.sub.xGa.sub.(1-x)N) layer is heteroepitaxially grown over the channel layer CH as the barrier layer) configured to form a two-dimensional electron gas (2DEG) channel.
Regarding claim 2, Kawaguchi further teaches the method of claim 1, wherein reducing the thickness of the semiconductor layer to at least the second thickness includes:
etching away the thickness of the semiconductor layer (para.0075, wherein the middle of the channel CH is etched and thus reduces the middle thickness of the channel CH to second thickness).
Regarding claim 6, Kawaguchi further teaches the method of claim 1, wherein forming the second semiconductor layer BA (para.0075) superjacent the first semiconductor layer CH (para.0075) includes:
forming a gallium nitride layer (para.0075, wherein channel CH is GaN) superjacent an aluminum gallium nitride layer (para.0075, wherein barrier layer BA is AlGaN).
Regarding claim 7, Kawaguchi further teaches the method of claim 1, comprising: forming an electrode GE (para.0085) superjacent the second semiconductor layer BA (para.0075).
Regarding claim 8, Kawaguchi further teaches the method of claim 7, wherein the electrode is a gate electrode GE (para.0085), the method further comprising:
forming a drain electrode DE (para.0085) and a source electrode SE (para.0085).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3,17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kawaguchi et al. (US20170110548A1) in view of Goetz et al. (US20020190259A1).
Regarding claim 3, Kawaguchi does not teach wherein etching away the thickness of the semiconductor layer includes:
performing a hydrogen bake treatment to desorb the semiconductor layer.
Fig.5 of Goetz teaches wherein H.sub.2 and NH.sub.3 ambient etches and roughens surface 40 of layer 38; which results in reduced thickness of layer 38 (para.0058).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the H.sub.2 and NH.sub.3 etch to reduce the thickness of the semiconductor layer, as taught by Goetz, in order to reduce the defect density and increase the comprehensive strain in subsequently grown III-Nitride layers (Goetz, [para.0058]).
Regarding claim 17, Fig.6 of Kawaguchi teaches a method of fabricating a semiconductor wafer to reduce or counteract defects, the method comprising:
forming a substrate layer S (para.0052);
forming a nucleation layer (para.0059, wherein a nucleation layer, may be provided between the substrate S and the channel layer CH) superjacent the substrate layer S;
forming a first semiconductor layer CH (para.0059), superjacent the nucleation layer (para.0059), to at least a first thickness;
wherein the reducing comprises a single reduction of the thickness following continuous formation of the first semiconductor layer to the first thickness CH (para.0075, wherein in a thickness is reduced at the middle, as shown in Fig.6, from first thickness to second thickness), while the substrate layer remains coupled with the nucleation layer; and
forming a second semiconductor layer BA (para.0070) superjacent the first semiconductor layer CH including forming a heterostructure (para.0070, wherein an AlGaN (Al.sub.xGa.sub.(1-x)N) layer is heteroepitaxially grown over the channel layer CH as the barrier layer) configured to form a two-dimensional electron gas (2DEG) channel, wherein the single reduction of the thickness occurs prior to forming the second semiconductor layer.
Kawaguchi does not teach reducing a thickness of the first semiconductor layer to at least a second thickness by performing a hydrogen bake treatment to desorb the first semiconductor layer.
Fig.5 of Goetz teaches wherein H.sub.2 and NH.sub.3 ambient etches and roughens surface 40 of layer 38; which results in reduced thickness of layer 38 (para.0058).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the H.sub.2 and NH.sub.3 etch to reduce the thickness of the semiconductor layer, as taught by Goetz, in order to reduce the defect density and increase the comprehensive strain in subsequently grown III-Nitride layers (Goetz, [para.0058]).
Regarding claim 18, Kawaguchi further teaches the method of claim 17, wherein forming the second semiconductor layer BA (para.0075) superjacent the first semiconductor layer CH (para.0075) includes:
forming a gallium nitride layer (para.0075, wherein channel CH is GaN) superjacent an aluminum gallium nitride layer (para.0075, wherein barrier layer BA is AlGaN).
Claims 9,10 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kawaguchi et al. (US20170110548A1) in view of Piedra et al. (US20210126120A1).
Regarding claim 9, Kawaguchi does not teach wherein forming a substrate layer includes: forming a silicon carbide layer.
Fig.11 of Piedra teaches a substrate 1104 that can include a silicon carbide-containing substrate (para.0139).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Piedra’s silicon carbide-containing substrate in the teachings of Kawaguchi because silicon carbide (SiC) substrate can have a higher thermal conductivity than a GaN channel layer (Piedra, [para.0029]).
Regarding claim 10, Piedra further teaches the method of claim 9, wherein forming a silicon carbide layer 1104 (para.0139) includes:
forming a non-vanadium doped silicon carbide layer.
Regarding claim 12, Kawaguchi does not teach wherein forming the first semiconductor layer, superjacent the nucleation layer, to at least the first thickness includes:
forming the first semiconductor layer, superjacent the nucleation layer, to at least a thickness of 250 nanometers.
Fig.3 of Piedra teaches wherein first compound semiconductor layer 208 can have a thickness from about 250 nm to about 1500 nm, from about 400 nm to about 1200 nm, from about 500 nm to about 1000 nm, from about 100 nm to about 500 nm, from about 100 nm to about 300 nm, or from about 30 nm to about 250 nm. The thickness of the first compound semiconductor layer 208 can be less than the thickness of a compound semiconductor layer of conventional compound semiconductor devices and the first compound semiconductor layer 208 is simply a channel layer (para.0042).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Piedra’s first compound semiconductor layer 208, with reduced thickness, in the teachings of Kawaguchi because it can result in improved control of an electric field produced by the compound semiconductor device due to a closer proximity between the conductive layer 204 and the compound semiconductor device (Piedra, [para.0042]). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05(I).
Regarding claim 13, Kawaguchi does not teach wherein reducing the thickness of the first semiconductor layer to at least the second thickness includes:
reducing the thickness of the first semiconductor layer to at least a thickness of 100 nanometers.
Fig.4 of Piedra teaches wherein first compound semiconductor layer 410 can have a thickness from about 250 nm to about 1500 nm, from about 400 nm to about 1200 nm, from about 500 nm to about 1000 nm, from about 100 nm to about 500 nm, from about 100 nm to about 300 nm, or from about 30 nm to about 250 nm. Wherein the thickness of the first compound semiconductor layer 410 can be less than the thickness of a compound semiconductor layer of conventional compound semiconductor devices. Thus, reducing the thickness of the first compound semiconductor layer 410 can bring a compound semiconductor device into closer proximity with the substrate 402 than conventional compound semiconductor devices (Piedra, [para.0070]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Piedra’s first compound semiconductor layer 410, with decreased thickness, in the teachings of Kawaguchi because it results in improved control of an electric field produced by the compound semiconductor device due to a closer proximity between the first conductive layer 404 and the second conductive layer 406 with respect to the compound semiconductor device (Piedra, [para.0070]). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05(I).
Regarding claim 14, Kawaguchi does not teach wherein reducing the thickness of the first semiconductor layer to at least a second thickness includes:
reducing the thickness of the first semiconductor layer to at least a thickness of 1000 nanometers.
Fig.6 of Piedra teaches wherein first compound semiconductor layer 606 can also include a second portion that is proximate to the second compound semiconductor layer 608 and is configured as a channel portion. The first thickness 610 of the first compound semiconductor material layer 606 can be from about 1000 nanometers to about 3000 nanometers, from about 1000 nanometers to about 2000 nanometers, or from about 1500 nanometers to about 3000 nanometers (Piedra, [para.0084]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Piedra’s first compound semiconductor layer 606, with reduced thickness, in the teachings of Kawaguchi it results in improved control of an electric field produced by the compound semiconductor device due to a closer proximity between the first conductive layer and the second conductive layer with respect to the compound semiconductor device (Piedra, [para.0070]). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05(I).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kawaguchi et al. (US20170110548A1) in view of Piedra et al. (US20210126120A1) and in further view of MUELLER et al. (US20160068994A1).
Regarding claim 11, the combination of Kawaguchi and Piedra does not teach wherein forming a silicon carbide layer includes: forming a vanadium-doped silicon carbide layer.
MUELLER teaches, in para.0019, wherein vanadium atoms incorporated into the SiC volume monocrystal are thus in particular electrically active or effective at least to a large extent or even as a whole and as a result of the high vanadium doping agent concentration incorporated into the crystal lattice a greater number of such flat imperfections can be compensated than in previously known methods.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include MUELLER’s vanadium-doped silicon carbide substrate in the teachings of Kawaguchi, as modified by Piedra, because as a result of high vanadium doping agent concentration incorporated into the crystal lattice a greater number of such flat imperfections can be compensated than in previously known methods, so that SiC volume monocrystals, which previously had to be disposed of because they had too many flat imperfections, in the growth method according to the invention still have the desired the semi-insulating behavior (MUELLER, [para.0019]). It has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). MPEP 2144.07.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kawaguchi et al. (US20170110548A1) in view of Goetz et al. (US20020190259A1) and in further view of Piedra et al. (US20210126120A1).
Regarding claim 19, Kawaguchi does not teach wherein forming the first semiconductor layer, superjacent the nucleation layer, to at least the first thickness includes:
forming the first semiconductor layer, superjacent the nucleation layer, to at least a thickness of 250 nanometers.
Fig.3 of Piedra teaches wherein first compound semiconductor layer 208 can have a thickness from about 250 nm to about 1500 nm, from about 400 nm to about 1200 nm, from about 500 nm to about 1000 nm, from about 100 nm to about 500 nm, from about 100 nm to about 300 nm, or from about 30 nm to about 250 nm. The thickness of the first compound semiconductor layer 208 can be less than the thickness of a compound semiconductor layer of conventional compound semiconductor devices and the first compound semiconductor layer 208 is simply a channel layer (para.0042).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Piedra’s first compound semiconductor layer 208, with reduced thickness, in the teachings of Kawaguchi because it can result in improved control of an electric field produced by the compound semiconductor device due to a closer proximity between the conductive layer 204 and the compound semiconductor device (Piedra, [para.0042]). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05(I).
Regarding claim 20, Kawaguchi does not teach wherein reducing the thickness of the first semiconductor layer to at least the second thickness includes:
reducing the thickness of the semiconductor layer to at least a thickness of 100 nanometers.
Fig.4 of Piedra teaches wherein first compound semiconductor layer 410 can have a thickness from about 250 nm to about 1500 nm, from about 400 nm to about 1200 nm, from about 500 nm to about 1000 nm, from about 100 nm to about 500 nm, from about 100 nm to about 300 nm, or from about 30 nm to about 250 nm. Wherein the thickness of the first compound semiconductor layer 410 can be less than the thickness of a compound semiconductor layer of conventional compound semiconductor devices. Thus, reducing the thickness of the first compound semiconductor layer 410 can bring a compound semiconductor device into closer proximity with the substrate 402 than conventional compound semiconductor devices (Piedra, [para.0070]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Piedra’s first compound semiconductor layer 410, with decreased thickness, in the teachings of Kawaguchi because it results in improved control of an electric field produced by the compound semiconductor device due to a closer proximity between the first conductive layer 404 and the second conductive layer 406 with respect to the compound semiconductor device (Piedra, [para.0070]). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05(I).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights