DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/29/2026 was filed after the mailing date of the non-final rejection on 5/1/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Status
Previous action: claims 1 through 9 and 13 through 16 rejected, claims 17, 18, and 20 non-elected
Present action: claims 1 through 9, 13 through 16 and 21 rejected, claims 17, 18, and 20 non-elected
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 2, 3, 4, 5, 6, 8, 13, 14, 15, 16, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (CN 111834317a) in view of Lin (US 2003/0197289)
Regarding claim 1.
Zhang teaches:
A semiconductor structure, comprising: a substrate (fig 4:301; [para 0058]);
a conductive layer (fig 4:303; [para 0060]), wherein the conductive layer (fig 4:303; [para 0060]) is disposed on the substrate (fig 4:301; [para 0058]);
a dielectric layer (fig 4:302; [para 0056]), wherein the dielectric layer (fig 4:302; [para 0056]) is disposed on the conductive layer (fig 4:303; [para 0060]) and comprises a first opening (fig 4:305; [para 0063]);
and a [pad] layer (fig 4:308,309; [para 0065]), wherein the [pad] layer (fig 4:308,309; [para 0065]) is disposed on the dielectric layer (fig 4:302; [para 0056]) and is connected to the conductive layer (fig 4:303; [para 0060]), the [pad] layer (fig 4:308,309; [para 0065]) comprises a bond pad (fig 4:308; [para 0065]) and a probe pad (fig 4:309; [para 0065]), the bond pad (fig 4:308; [para 0065]) and the probe pad (fig 4:309; [para 0065]) are disposed adjacent to each other (fig 4), at least one recess (fig 4:307 comprising a crater; [para 0065,0098]) is formed in the [pad] layer (fig 4:308,309; [para 0065]) on a side of the [pad] layer (fig 4:308,309; [para 0065]) opposite to the first opening (fig 4:305; [para 0063]), and the at least one recess (fig 4:307 comprising a crater; [para 0065,0098]) is disposed between the bond pad (fig 4:308; [para 0065]) and the probe pad (fig 4:309; [para 0065]) and below a top surface of the [pad] layer (fig 4:308,309; [para 0065]);
and wherein a first orthographic projection of the recess (fig 4:307 comprising a crater; [para 0065,0098]) on the substrate (fig 4:301; [para 0058]) is within a second orthographic projection of the first opening (fig 4:305; [para 0063])on the substrate (fig 4:301; [para 0058]), an air gap (fig 4:306; [para 0058])is formed in the [pad] layer (fig 4:308,309; [para 0065])on a side of the [pad] layer (fig 4:308,309; [para 0065])facing the first opening (fig 4:305; [para 0063]), and the air gap (fig 4:306; [para 0058]) is located below the recess (fig 4:307 comprising a crater; [para 0065,0098]) and above the first opening (fig 4:305; [para 0063]), wherein a portion of the [pad] layer (fig 4:308,309; [para 0065]) fills a portion of the first opening (fig 4:305; [para 0063])such that the at least one recess (fig 4:307 comprising a crater; [para 0065,0098]) is formed on an upper surface of the [pad] layer (fig 4:308,309; [para 0065]) above the first opening (fig 4:305; [para 0063]).
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Zhang does not teach that the pad layer is part of a redistribution layer
Lin teaches:
A semiconductor structure, comprising: a substrate (fig 3b:350,352; [para 0032]);
a dielectric layer (fig 3b:330; [para 0031]),
and a re-distribution layer (fig 3a,3b:312,314,320; [para 0031,0032]), wherein the re-distribution layer (fig 3a,3b:312,314,320; [para 0031,0032]) is disposed on the dielectric layer (fig 3b:330; [para 0031]) the re-distribution layer (fig 3a,3b:312,314,320; [para 0031,0032])comprises a bond pad (fig 3a,3b:312; [para 0003]) and a probe pad (fig 3a,3b:314; [para 0033]), the bond pad (fig 3a,3b:312; [para 0003]) and the probe pad (fig 3a,3b:314; [para 0033]) are disposed adjacent to each other (fig 3a,3b), at least one recess (fig 3a:360; [para 0037]) is formed in the re-distribution layer (fig 3a,3b:312,314,320; [para 0031,0032]) and the at least one recess (fig 3a:360; [para 0037]) is disposed between the bond pad (fig 3a,3b:312; [para 0003]) and the probe pad (fig 3a,3b:314; [para 0033])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the pad layer to be part of a redistribution layer in order that voltage applied to the pad can be conducted to other portions of the substrate.
Regarding claim 2.
Zhang in view of Lin teaches the semiconductor structure according to claim 1, further
Zhang teaches:
the at least one recess consists of one recess (fig 4:307 comprising a crater; [para 0065,0098]),
and the bond pad (fig 4:308; [para 0065]) and the probe pad (fig 4:309; [para 0065]) are respectively disposed on two opposite sides of the recess.
Regarding claim 3.
Zhang in view of Lin teaches the semiconductor structure according to claim 2
Lin teaches:
widths of the recess (fig 3d:368; [para 0038]) sampled along a length direction of the recess are uniform.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the width of the recess to be uniform in order to provide a clear demarcation between the probe and bonding pad.
Regarding claim 4.
Zhang in view of Lin teaches the semiconductor structure according to claim 2
Lin teaches:
widths of the recess (fig 3a:368; [para 0037]) sampled along a length direction of the recess are varied.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the width of the recess to be varied in order to aid in finding the center of the division line.
Regarding claim 5.
Zhang in view of Lin teaches the semiconductor structure according to claim 4, further
Lin teaches:
the widths of the recess (fig 3a:368; [para 0037]) gradually decrease from two opposite edge regions of the recess to a middle region of the recess (fig 3a:368; [para 0037]).
Regarding claim 6.
Zhang in view of Lin teaches the semiconductor structure according to claim 1
Lin teaches:
the at least one recess consists of a plurality of the recesses (fig 3c:362; [para 0038]),
and the bond pad (fig 3c:312; [para 0038]) and the probe pad (fig 3c:314; [para 0038]) are respectively disposed on two opposite sides of a recess region formed by the plurality of the recesses (fig 3c:362; [para 0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for to provide multiple recesses in order to aid in finding the center of the division line.
Regarding claim 8.
Zhang in view of Lin teaches the semiconductor structure according to claim 6, further
Lin teaches:
the recesses (fig 3c:362; [para 0038]) are disposed and spaced apart along a length direction of the recess region,
and the length direction of the recess region is substantially parallel to an edge line between the probe pad (fig 3c:314; [para 0038]) and the recesses (fig 3c:362; [para 0038]).
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Regarding claim 13.
Zhang in view of Lin teaches the semiconductor structure according to claim 1, further
Zhang teaches:
the first opening (fig 4:305; [para 0063]) exposes the conductive layer (fig 4:303; [para 0060]).
Regarding claim 14.
Zhang in view of Lin teaches the semiconductor structure according to claim 1, further
Zhang teaches:
a width of the first opening is not greater than 3 µm (the second through hole is 0.1-0.3 um; [para 0015]).
Given the teaching of the references, it would have been obvious to determine the optimum width of the opening involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) It is not inventive to discover optimum or workable ranges by routine experimentation. Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575,1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 15.
Zhang in view of Lin teaches the semiconductor structure according to claim 1, further
Zhang teaches:
a width of the first opening is not 1um to 3 µm (the second through hole is 0.1-0.3 um; [para 0015]).
Given the teaching of the references, it would have been obvious to determine the optimum width of the opening involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) It is not inventive to discover optimum or workable ranges by routine experimentation. Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575,1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 16.
Zhang in view of Lin teaches the semiconductor structure according to claim 1
Lin teaches:
an optical identification layer (fig 3b,3d:340; [para 0034]),
wherein the optical identification layer (fig 3b,3d:340; [para 0034]) is disposed on the re-distribution layer (fig 3b,3d:312,314; [para 0031]),
and the optical identification layer comprises a second opening to expose the bond pad (fig 3c:312; [para 0038]), the probe pad (fig 3c:314; [para 0038]), and the recess (fig 3c:362; [para 0038]).
Regarding claim 21.
Zhang in view of Lin teaches the semiconductor structure according to claim 1
Lin teaches:
the at least one recess (fig 3a:360; [para 0037]) serves as an optical identification pattern ([para 0037]) between the bond pad (fig 3a,3b:312; [para 0003]) and the probe pad (fig 3a,3b:314; [para 0033])for identifying a location region of the probe pad (fig 3a,3b:314; [para 0033]) during automatic testing ([para 0030]).
The limitation must distinguish from the prior art in terms of structure rather than function, In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); See also In re Swinehart, 439 F.2d210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971). Claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. In re Danly, 263 F. 2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F. 2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Zhang (CN 111834317a) in view of Lin (US 2003/0197289) as applied to claim 6 and further in view of Tanabe (US 2011/0175241).
Regarding claim 7.
Zhang in view of Lin teaches the semiconductor structure according to claim 6, above
Zhang in view of Lin does not teach recesses spaced apart along a width of the recess region.
Tanabe teaches:
the recesses (fig 5:123,121:0031]) are disposed and spaced apart along a width direction of the recess region.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of recesses in at least two rows in order to designate the boundaries of the probe region, the bonding region, and the intimidate area between the two which provides an offset toto ensure that there is no overlap (paragraph 31)
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Zhang (CN 111834317a) in view of Lin (US 2003/0197289) as applied to claim 8 and further in view of Tanabe (US 2011/0175241).
Regarding claim 9.
Zhang in view of Lin teaches the semiconductor structure according to claim 8, above
Zhang in view of Lin does not teach at least two rows in the recess region.
Tanabe teaches:
the plurality of the recesses (fig 5:123,121:0031]) are arranged in at least two rows in the recess region.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of recesses in at least two rows in order to designate the boundaries of the probe region, the bonding region, and the intimidate area between the two which provides an offset toto ensure that there is no overlap (paragraph 31).
Response to Arguments
Applicant's arguments filed 7/27/26 have been fully considered but they are not persuasive.
The applicant argues that the prior art does not teach a recess on an upper surface of a re-distribution layer above the first opening
The applicant is incorrect. As can be noted in Zhang figures 2, 4, and 6, Zhang teaches a recess on an upper surface of the re-distribution layer above the first opening. Further Zhang teaches that the air gap is located below the recess and above the first opening
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The applicant does not claim that no portion of the air gap extends below the top surface of the redistribution layer or the top of the opening. Further, such a limitation would not be supported by the applicant’s specification (see figure 2).
The applicant argues that there is no motivation to combine the references.
The applicant will note the motivation in the rejection above. Further, the applicant will note that a recess is an ordinary consequence of probing.
The fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
In response to applicant's argument that the recess was not used as a visual indicia, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
The applicant argues the references are incompatible.
The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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