DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on July 28, 2022. It is noted, however, that applicant has not filed a certified copy of the KR 10-2022-0094024 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 15, 2023 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: NAND Flash Memory With Improved Reliability and Electronic System Including the Same
Election/Restrictions
Applicant’s election without traverse of device embodiment 1 (fig. 4A, claims 1-5 and 7-20) in the reply filed on September 29, 2025 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “plurality of contact plugs passing through at least some of the plurality of word lines in the vertical direction” of claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-5 and 7-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1, lines: 9-10 recites the limitation “a plurality of contact plugs passing through at least some of the plurality of word lines in the vertical direction…” which is not shown in the figures. The figures show a plurality of plugs (for example 160 in Fig. 5) passing through the support SP, but 160 does not pass through the plurality of wordlines 130. For purposes of examination this will be interpreted as “a plurality of contact plugs passing through the support in the vertical direction…”
Claim 9, lines: 14-15 recites the limitation “a plurality of contact plugs passing through at least some of the plurality of word lines in the vertical direction…” which is not shown in the figures. The figures show a plurality of plugs (for example 340 in Fig. 10) passing through the support SP, but 340 does not pass through the plurality of wordlines 330. For purposes of examination this will be interpreted as “a plurality of contact plugs passing through the support in the vertical direction…”
Claim 19, lines: 14-15 recites the limitation “a plurality of contact plugs passing through at least some of the plurality of word lines in the vertical direction…” which is not shown in the figures. The figures show a plurality of plugs (for example 340 in Fig. 10) passing through the support SP, but 340 does not pass through the plurality of wordlines 330. For purposes of examination this will be interpreted as “a plurality of contact plugs passing through the support in the vertical direction…”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 7-9, 11, 13-14, and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2021/0151460).
Claim 1, Kim discloses (Figs 4 and annotated fig. 7 below) a semiconductor device comprising: a substrate (160, first upper interlayer insulating layer under broadest reasonable interpretation (BRI) considered substrate as it holds other layers 170/180, Para [0100]) including a memory cell region (CAA) and a connection region (EA); a memory stack (SST1, first stack structure, Para [0017]) including a plurality of word lines (EL1/EL2, first/second gate electrodes, Para [0107]) extending in the memory cell region and the connection region (EL1/EL2 extend in CAA and EA) in a horizontal direction (x-direction) that is parallel with an upper surface of the substrate (x-direction is parallel to upper surface of 160), the plurality of word lines overlapping with each other in a vertical direction (EL1/EL2 overlap with each other in z-direction); a support (150, planarized insulating layer, Para [0036]) in the connection region (150 is in EA) and positioned at a side of the memory stack (150 is positioned at a left side of SST1), the support includes a plurality of steps (150 has steps on top surface, hereinafter “steps”); a plurality of pad parts (ELp1, electrode pads, Para [0036]) on a top surface of the support (ELp1 are on top surface on steps); and a plurality of contact plugs (VC, vertical contact, Para [0111]) passing through the support in the vertical direction (VC passes through 150 in z-direction), the plurality of contact plugs directly contacting the plurality of pad parts for electrical connection therewith (VC directly contacts ELp1 for electrical connection, Para [0111]).
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Claim 2, Kim discloses (Figs 4 and annotated fig. 7 above) the semiconductor device of claim 1, wherein each of the plurality of contact plugs (VC) passes through one of the plurality of pad parts (ELp1) respectively in direct contact with the plurality of contact plugs (each VC is in direct contact with ELp1). Claim 7, Kim discloses (Figs 4 and annotated fig. 7 above) the semiconductor device of claim 1, wherein the plurality of pad parts (ELp1) are in direct contact with at least one of the plurality of word lines (as can be seen in Fig. 7 above ELp1 is in contact with ELe1 of the word lines EL1/EL2) .
Claim 8, Kim discloses (Figs 4 and annotated fig. 7 above) the semiconductor device of claim 1, further comprising at least one dummy channel structure (labeled in Fig. 4, DCS, dummy channel structure, Para [0077]) passing through the plurality of word lines in the vertical direction in the connection region (since DCS is in EA it would pass through EL1/EL2 in z-direction). Claim 9, Kim discloses (Figs 4 and 7) a semiconductor device comprising: a first substrate (Fig. 7, 201, base substrate, Para [0081]) including a memory cell region (region in which VCS formed, labeled in Fig. 4 as CAA) and a connection region (region where steps are formed, labeled in Fig. 4 as EA); a peripheral circuit region (PTR, transistors in peripheral region, Para [0082]) above the first substrate (PTR is above 201); a memory stack (SST1, first stack structure, Para [0017]) in the memory cell region and the connection region above the peripheral circuit region (SST1 is in CAA and EA above PTR), the memory stack including a plurality of word lines (EL1/EL2, first/second gate electrodes, Para [0107]) extending in a horizontal direction (EL1/EL2 extend in x-direction) that is parallel with an upper surface of the first substrate (x-direction is parallel with upper surface of 201) and overlapping with each other (EL1 and EL2 overlap with each other in z-direction) in a vertical direction (z-direction) that is orthogonal to the horizontal direction (z-direction is orthogonal to x-direction); a plurality of channel structures (VCS, vertical channel structures, Para [0037]) in the memory cell region (VCS is in CAA), the plurality of channel structures passing through the plurality of word lines in the vertical direction (VCS passes through EL1/EL2 in z-direction); a support (150, planarized insulating layer, Para [0036]) in the connection region (150 is in EA) and positioned at a side of the memory stack (150 is positioned at a right side of SST1), the support includes a plurality of steps (150 includes a plurality steps on its bottom surface, hereinafter “steps”); a plurality of pad parts (ELp1, electrode pads, Para [0036]) on a bottom surface of the support (ELp1 is on a bottom surface of 150 where steps are formed) ; a second substrate (160, first upper interlayer insulating layer under broadest reasonable interpretation (BRI) considered substrate as it holds other layers 170/180, Para [0100]) on the memory stack (160 is on SST1); and a plurality of contact plugs (VC, vertical contact, Para [0111]) passing through the support in the vertical direction (VC passes through 150 in Z-direction), the plurality of contact plugs directly contacting the plurality of pad parts for electrical connection therewith (VC directly contacts ELp1 for electrical connection, Para [0111]). Claim 11, Kim discloses (Figs 4 and 7) the semiconductor device of claim 9, wherein a vertical level of a top surface of each of the plurality of contact plugs (VC) is higher than a top surface of an uppermost word line (EL1/EL2) of the plurality of word lines (top surface of VC is higher than top surface of uppermost EL1/EL2).
Claim 13, Kim discloses (Figs 4 and 7) the semiconductor device of claim 9, further comprising a dummy channel structure (labeled in Fig. 4, DCS, dummy channel structure, Para [0077]) passing through the memory stack in the vertical direction in the connection region (DCS would pass through SST1 in z-direction in EA), wherein the dummy channel structure increases structural stability of the plurality of word lines (DCS provides structural stability for EL1/EL2, Para [0067]).
Claim 14, Kim discloses (Figs 4 and 7) the semiconductor device of claim 9, wherein a thickness of the support (150) in the horizontal direction is greater than about twice a diameter of each of the plurality of contact plugs (as can be seen in Fig. 7 the thickness of 150 in x-direction is greater than twice the diameter of VC in x-direction). Claim 17, Kim discloses (Figs 4 and 7) the semiconductor device of claim 9, wherein: the memory cell region (CAA) includes a bit line bonding area (CAA has the bit lines BL as shown in Fig. 7) having the plurality of channel structures arranged therein (VCS are formed in CAA as shown in Fig. 4); and the connection region (EA) includes an external pad bonding area (EA has area of connection lines CL as shown in Fig. 7) and a word line bonding area having the plurality of contact plugs arranged therein (EA has area where contact plugs VC are formed as shown in Fig. 7). Claim 18, Kim discloses (Figs 4 and 7) the semiconductor device of claim 9, wherein the support (150) includes an insulator (150 is planarizes insulating layer, Para [0082]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0151460) in view of Tei (US Pat. No. 11,521,675). Claim 19, Kim discloses (Figs 4 and annotated fig. 7 below) a semiconductor device includes:
a substrate (160, first upper interlayer insulating layer under broadest reasonable interpretation (BRI) considered substrate as it holds other layers 170/180, Para [0100]) including a memory cell region (CAA) and a connection region (EA); a memory stack (SST1, first stack structure, Para [0017]) including a plurality of word lines (EL1/EL2, first/second gate electrodes, Para [0107]) extending in the memory cell region and the connection region (EL1/EL2 extend in CAA and EA) in a horizontal direction (x-direction) that is parallel with an upper surface of the substrate (x-direction is parallel to upper surface of 160), the plurality of word lines overlapping with each other in a vertical direction (EL1/EL2 overlap with each other in z-direction); a peripheral circuit (PTR, transistors in peripheral circuit, Para [0082]) on the memory stack (PTR is on SST1); a support (150, planarized insulating layer, Para [0036]) in the connection region (150 is in EA) and positioned at a side of the memory stack (150 is positioned at a left side of SST1), the support includes a plurality of steps (150 has steps on top surface, hereinafter “steps”); a plurality of pad parts (ELp1, electrode pads, Para [0036]) on a top surface of the support (ELp1 are on top surface on steps); a plurality of contact plugs (VC, vertical contact, Para [0111]) passing through the support in the vertical direction (VC passes through 150 in z-direction), the plurality of contact plugs directly contacting the plurality of pad parts for electrical connection therewith (VC directly contacts ELp1 for electrical connection, Para [0111]). Kim does not explicitly disclose an electronic system comprising: a main board; a semiconductor device on the main board; and a controller on the main board and electrically connected to the semiconductor device… and an input/output pad electrically connected to the peripheral circuit. However, Tei discloses (Figs. 1-3) an electronic system (100 comprising: a main board (100, storage system, Col. 16, lines: 43-49) would be on PCB not labeled, hereinafter “board”); a semiconductor device (104, storage medium, Col. 16, lines: 43-49) on the main board (104 would be on board); and a controller (102, storage controller, Col. 16, lines: 43-49) on the main board (102 would be on board) and electrically connected to the semiconductor device (102 is connected to 104, Col. 16, lines: 43-49) … and an input/output pad (unlabeled I/O pads connect to 114, Col. 16, lines: 43-49, hereinafter “I/O”) electrically connected to a peripheral circuit (I/O is integrated at the edge or periphery of the package, Col. 16, lines: 43-49). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the system of Tei as it allows the memory device to be organized in a system for controlling the various functions of the structure in an integrated fashion (Tei, Col. 16, lines: 43-49).
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Claim 20, Kim in view of Tei discloses the electronic system of claim 19, wherein the main board (board of Tei) includes wiring patterns electrically connecting the semiconductor device to the controller (board has wiring connecting 104 to 102 as seen in Fig. 2 of Tei). Kim discloses (Figs 4 and annotated fig. 7 above) the semiconductor device further includes: a plurality of channel structures (VCS, vertical channel structure, Para [0098]) in the memory cell region (CAA) and passing through the plurality of word lines in the vertical direction (VCS is in CAA and passes through EL1/EL2 in z-direction); a first substrate (201, substrate, Para [0100]) on the peripheral circuit (201 is on PTR); and the substrate (160) corresponds to a second substrate spaced apart from the first substrate in the vertical direction (160 is spaced apart from 201 in z-direction).
Allowable Subject Matter
Claims 3-5, 10, 12, and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the 112 rejections above and in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Kim (US 2021/0151460), Tei (US Pat. No. 11,521,675), Lee (US 2023/0108322), Xiao (US 2022/0068882), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 3, wherein a vertical level of a bottom surface of each of the plurality of contact plugs is positioned between a bottommost surface of the support and a bottom surface of a lowermost pad part of the plurality of pad parts that is closest to the substrate in the vertical direction.
Regarding Claim 4, wherein each of top and bottom surfaces of a pad part disposed on the support among the plurality of pad parts includes a stepped portion.
Regarding Claim 5, the support surrounds a side wall of a plurality of contact plugs among the plurality of contact plugs arranged in both the first horizontal direction and the second horizontal direction.
Regarding Claim 10, wherein a vertical level of a top surface of each of the plurality of contact plugs is positioned between a vertical level of a top surface of an uppermost pad part of the plurality of pad parts and a vertical level of a top surface of the support.
Regarding Claim 12, wherein the bottom surface of the support directly contacting each of the plurality of pad parts is positioned at a lower vertical level than a bottom surface of a word line electrically connected to each of the plurality of pad parts among the plurality of word lines and includes a stepped portion.
Regarding Claim 15, a thickness of the support in the second horizontal direction is greater than the diameter of each of the plurality of contact plugs and is less than about twice the diameter of each of the plurality of contact plugs.
Regarding Claim 16, wherein a top surface of the support is position at a higher vertical level than a bottommost surface of the second substrate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 2023/0108322) discloses (Fig. 9B) a connection region CON with dummy channels 140D and support structures 137 with stepped portions. Lee does not disclose pad portions directly contacting contact plugs and Lee is commonly owned.
Xiao (US 2022/0068882) discloses (Fig. 1) a substrate 10 with a memory cell array 102 formed on top with a periphery circuit 101 in between and conductive vias 170 connected to word lines. Xiao does not disclose pad structures directly contacting the conductive vias.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.G.R/Examiner, Art Unit 2812