DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) rejected have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Not that applicant’s claim 1 which was amended to recite “a first electrode having a first edge extending in a first direction and at least partially overlapping the first conductive region” changes the scope of the claim from have a first electrode extending in a first direction to now have a first edge extending in a first direction.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Song et al. 20190288118.
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Regarding claim 1, fig. 1 of Song discloses a display apparatus comprising:
a substrate 01;
a first semiconductor layer 05/051 (par [0049] - an oxide semiconductor material) disposed on the substrate and comprising a first conductive region 051 (pa4 [0047]) and a first semiconductor region 05 which are adjacent to each other;
a first gate electrode 02 disposed on the first semiconductor layer and at least partially overlapping the first semiconductor region 05; and
a first electrode having 03 a first edge extending (top surface edge) in a first direction (X-direction) and at least partially overlapping the first conductive region,
wherein a first length (top surface x-dimension), in the first direction, of a first portion (top surface portion) of the first conductive region overlapping the first edge of the first electrode is greater than a first width of the first semiconductor region in the first direction, and
wherein the first electrode is disposed in a floating state (floating gate is in floating state) on the first gate electrode.
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Regarding claim 26, fig. 1 of Song discloses a display apparatus comprising:
a substrate 01;
a first semiconductor layer 05/051 disposed on the substrate and comprising a first conductive region 051 (pa4 [0047]) and a first semiconductor region 05 which are adjacent to each other;
a first gate electrode 03 disposed on the first semiconductor layer and at least partially overlapping the first semiconductor region 05; and
a first electrode 06 having a first edge (top edge) extending in a first direction (X-direction) and at least partially overlapping the first conductive region 051,
wherein a first length (top surface length of 051 in the X – direction), in the first direction, of a first portion (top portion) of the first conductive region 051 overlapping the first edge of the first electrode 03 is greater than a first width (as labeled by examiner above) of the first semiconductor region in the first direction, and
a second electrode 02 interposed between the substrate 01 and the first semiconductor layer 05/051 and at least partially overlapping the first electrode 03.
Claims 2-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by IEDA 20110156023.
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Regarding claim 2, figs. 18 and 3 of IEDA discloses a display apparatus comprising:
a substrate 01:
a first semiconductor layer 22/15/14 disposed on the substrate and comprising a first conductive region 15 and a first semiconductor region 22 which are adjacent to each other, the first semiconductor layer further including a second conductive region 14, such that the first semiconductor region is located between the first conductive region and the second conductive region;
a first gate electrode 26 disposed on the first semiconductor layer and at least partially overlapping the first semiconductor region; and
a first electrode 18 at least partially overlapping the first gate electrode, the first electrode having a first edge (bottom surface edge) extending in a first direction (X) and at least partially overlapping the first conductive region and a second edge (top surface edge) extending in the first direction, and at least partially overlapping the second conductive region,
wherein a first length, in the first direction, of a first portion of the first conductive region overlapping the first edge of the first electrode is greater than a first width of the first semiconductor region in the first direction.
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Regarding claim 3, fig. 3 of IEDA discloses wherein a second length, in the first direction, of a second portion of the second conductive region overlapping the second edge of the first electrode is greater than the first width of the first semiconductor region in the first direction.
Regarding claim 4, fig. 3 of wherein the first conductive region includes a first protrusion (see narrow part protrudes from wider part) extending in the first direction, the second conductive region includes a second protrusion (see narrow part protrudes from wider part) extending in the first direction, the first edge of the first electrode at least partially overlaps the first protrusion of the first conductive region, and the second edge of the first electrode at least partially overlaps the second protrusion of the second conductive region.
Regarding claim 5, fig. 3 of IEDA discloses further comprising: a second electrode 21 interposed between the substrate and the first semiconductor layer and at least partially overlapping the first electrode.
Regarding claim 6, fig. 3 of IEDA discloses wherein the first electrode 18 is in a floating state (floating gate), and the second electrode is in a floating state or a state in which a constant voltage is applied thereto.
Regarding claim 7, fig. 3 of IEDA discloses wherein the second electrode has a third edge (top surface edge) which extends in the first direction and at least partially overlaps at least one of the first conductive region and the second conductive region, and a second length (total X length across the page of 22, in the first direction, of a second portion of the first semiconductor layer overlapping the third edge of the second electrode is greater than the first width of the first semiconductor region in the first direction.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Song.
Regarding claim 8, Song discloses claim 1, but does not discloses further comprising: a second semiconductor layer including a different material from the first semiconductor layer and comprising a second conductive region and a second semiconductor region which are adjacent to each other; a second gate electrode disposed on the second semiconductor layer and at least partially overlapping the second semiconductor region; and a second electrode having a second edge extending in the first direction and at least partially overlapping the second conductive region, wherein a second length, in the first direction, of a second portion of the second conductive region overlapping the second edge of the second electrode is greater than a second width of the second semiconductor region in the first direction.
However, it would have been obvious to form a display apparatus of Song further comprising: a second semiconductor layer including a different material from the first semiconductor layer and comprising a second conductive region and a second semiconductor region which are adjacent to each other; a second gate electrode disposed on the second semiconductor layer and at least partially overlapping the second semiconductor region; and a second electrode having a second edge extending in the first direction and at least partially overlapping the second conductive region, wherein a second length, in the first direction, of a second portion of the second conductive region overlapping the second edge of the second electrode is greater than a second width of the second semiconductor region in the first direction in order to form more than one memory transistor for real world application.
Regarding claim 9, it would have been obvious to form an apparatus comprising wherein the first semiconductor layer includes a silicon semiconductor material, and the second semiconductor layer includes an oxide semiconductor material as these are well known semiconductor material and can be selected to achieve applicant’s design requirement.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Park et al. 10991302.
Regarding claim 10, Song discloses claim 8, but does not discloses further comprising: a pixel circuit disposed on the substrate; and a display element electrically connected to the pixel circuit, wherein the pixel circuit comprises: a driving transistor which controls a current flowing to the display element according to a gate-source voltage; a scan transistor which transmits a data voltage to the driving transistor in response to a scan signal; and a compensating transistor which connects a drain of the driving transistor to a gate of the driving transistor in response to a compensation signal, the scan transistor comprises the first gate electrode to which the scan signal is applied, and the first semiconductor layer, and the compensating transistor comprises the second gate electrode to which the compensation signal is applied, and the second semiconductor layer.
However, park discloses in section (23) In the display device according to the present invention, each pixel circuit may include a first scan transistor configured to receive a first scan signal and apply the first scan signal to a gate electrode of the driving transistor, and a second scan transistor configured to receive a second scan signal and perform a switching operation for compensating for the driving transistor.
As such it would have been obvious to form a display apparatus further comprising: a pixel circuit disposed on the substrate; and a display element electrically connected to the pixel circuit, wherein the pixel circuit comprises: a driving transistor which controls a current flowing to the display element according to a gate-source voltage; a scan transistor which transmits a data voltage to the driving transistor in response to a scan signal; and a compensating transistor which connects a drain of the driving transistor to a gate of the driving transistor in response to a compensation signal, the scan transistor comprises the first gate electrode to which the scan signal is applied, and the first semiconductor layer, and the compensating transistor comprises the second gate electrode to which the compensation signal is applied, and the second semiconductor layer such as taught by Park in order to form a pixel circuit.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
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