Prosecution Insights
Last updated: May 29, 2026
Application No. 18/197,994

SYSTEM IN A PACKAGE (SIP) WITH AIR CAVITY AND EPOXY SEAL

Non-Final OA §103
Filed
May 16, 2023
Priority
Jun 10, 2022 — provisional 63/366,167
Examiner
CHANG, JAY C
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qorvo US Inc.
OA Round
2 (Non-Final)
85%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
548 granted / 647 resolved
+16.7% vs TC avg
Moderate +14% lift
Without
With
+14.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
25 currently pending
Career history
687
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
59.8%
+19.8% vs TC avg
§102
18.4%
-21.6% vs TC avg
§112
19.1%
-20.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 647 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is responsive to the following communications: the Amendment filed 4/15/2026. Claims 1-12 and 18 are pending. Claims 13-17 are cancelled. Claims 1 and 18 are currently amended. Claims 1 and 18 are independent. Response to Arguments Applicants' arguments and amendments, filed 4/15, with respect to independent claims 1 and 18, although substantive and pertinent to expediting the prosecution of the current application, are considered moot and not persuasive, respectfully, in light of new grounds of rejections made using the combined teachings of Nagarajan and Christianson as noted below in the rejections of independent claims 1 and 18. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1, 3-4, 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Nagarajan (US 7,187,077 B1) in view of Christianson et al. (US 2019/0311963 A1, hereinafter “Christianson”). Regarding independent claim 1, Figure 3 of Nagarajan discloses a system in a package (SiP) comprising: a substrate 202 (“substrate”- Col. 3, Lines 24-25) comprising a first surface; a lid 204 (“lid”- Col. 3, Lines 24-25) comprising a generally planar element (i.e., the horizontal top portion of lid 204) and a wall element (i.e., the vertical side portion of lid 204) extending generally perpendicularly from the planar element, the wall element having a lip surface generally parallel to the first surface, the lip surface coupled to the first surface with a first adhesive 310 (“bonding agent”- Col. 3, Line 49), which is comprised of solder (Col. 4, Lines 65-66), and wherein the wall element comprises an exterior surface generally perpendicular to the lip surface; and a second epoxy 206 (“seal… epoxy”- Col. 3, Lines 64-65) coupled to the first adhesive 310 and covering the exterior surface from the lip surface to the generally planar element, since the second epoxy 206 extends along a portion of the side of the horizontal top portion of lid 204. Nagarajan does not expressly disclose wherein the first adhesive is comprised of an epoxy material such that it can interpretated as the claimed first epoxy. Christianson discloses a semiconductor package comprising an adhesive, wherein the adhesive is comprised of solder or an epoxy material (i.e., conductive epoxy) (¶0023). In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nagarajan such that the first adhesive is comprised an epoxy material (i.e., conductive epoxy) as taught by Christianson for the purpose of substituting art recognized equivalents known to be used for the same purpose (MPEP 2144.06), specifically utilizing a suitable adhesive material as known in the art (Christianson ¶0023). Thus, in the combined teachings including Christianson the first adhesive 310 is comprised of an epoxy material such that it can interpretated as the claimed first epoxy. Regarding claim 3, Figure 3 of Nagarajan discloses the SiP further comprising a die 320 (“chip”- Col. 3, Lines 40-41) positioned on the first surface of the substrate 202 in an air cavity 306 (“recess”- Col. 4, Line 10) formed by the lid 204. Regarding claim 4, Figure 3 of Nagarajan discloses the SiP further comprising a chiplet 320 (“chip”- Col. 3, Lines 40-41) positioned on the first surface of the substrate 202 in an air cavity 306 (“recess”- Col. 4, Line 10) formed by the lid 204. Regarding claim 8, Figure 3 of Nagarajan discloses the SiP further comprising a component 320 (“chip”- Col. 3, Lines 40-41) positioned on the first surface of the substrate 202 in an air cavity 306 (“recess”- Col. 4, Line 10) formed by the lid 204. Regarding independent claim 18, Figure 3 of Nagarajan discloses a device comprising: a circuit positioned in a semiconductor package, the semiconductor package comprising: a substrate 202 (“substrate”- Col. 3, Lines 24-25) comprising a first surface; a lid 204 (“lid”- Col. 3, Lines 24-25) comprising a generally planar element (i.e., the horizontal top portion of lid 204) and a wall element (i.e., the vertical side portion of lid 204) extending generally perpendicularly from the planar element, the wall element having a lip surface generally parallel to the first surface, the lip surface coupled to the first surface with a first adhesive 310 (“bonding agent”- Col. 3, Line 49), which is comprised of solder (Col. 4, Lines 65-66), and wherein the wall element comprises an exterior surface generally perpendicular to the lip surface; and a second epoxy 206 (“seal… epoxy”- Col. 3, Lines 64-65) coupled to the first adhesive 310 and covering the exterior surface from the lip surface to the generally planar element, since the second epoxy 206 extends along a portion of the side of the horizontal top portion of lid 204. Nagarajan does not expressly disclose wherein the device is a communication device, the circuit is a communication circuit and wherein the first adhesive is comprised of an epoxy material such that it can interpretated as the claimed first epoxy. Christianson discloses a communication device (i.e., numerous communication devices are listed in ¶0060) comprising a communication circuit positioned in a semiconductor package, the semiconductor package comprising an adhesive, wherein the adhesive is comprised of solder or an epoxy material (i.e., conductive epoxy) (¶0023). In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nagarajan such that the device is a communication device, the circuit is a communication circuit and the first adhesive is comprised an epoxy material (i.e., conductive epoxy) as taught by Christianson for the purpose of utilizing a suitable and well-known type of device and associated circuit for semiconductor packages and substituting art recognized equivalents known to be used for the same purpose (MPEP 2144.06), specifically utilizing a suitable adhesive material as known in the art (Christianson ¶0023). Thus, in the combined teachings including Christianson the first adhesive 310 is comprised of an epoxy material such that it can interpretated as the claimed first epoxy. Claims 2 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over the combined teachings of Nagarajan and Christianson in further view of Higashi et al. (US 2007/0108634 A1, hereinafter “Higashi”). Regarding claim 2, the combined teachings do not expressly disclose the SiP further comprising a sputtered metal layer covering the second epoxy and an exposed portion of the lid. Figure 1 of Higashi discloses a semiconductor package comprising a lid 2 (“cover member”- ¶0065), an epoxy 3 (“adhesive… epoxy resin”- ¶¶0069), and a sputtered metal layer 4 (“coating… of nickel (Ni) and gold (Au)”- ¶¶0069, 0082) covering the epoxy 3 and an exposed portion (i.e., a top surface of 2) of the lid 2. In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings such that the SiP further comprises a sputtered metal layer covering the second epoxy (analogous to the epoxy in Higashi) and an exposed portion (i.e., a top surface) of the lid as taught by Higashi for the purpose of preventing the penetration of moisture into the package, thereby improving the air tightness and further providing high reliability free from pin holes (Higashi ¶0077). Note, regarding the claim limitation “sputtered metal layer” (emphasis added) which is drawn to process steps of a product-by-process claim, such method step(s) are not considered to render an old apparatus patentable where the prior art teaches a product that appears to be the same as, or an obvious variant of, the product set forth in a product-by-process claim although produced by a different process. That is even though product-by-process claims are limited by and defined by the process, the determination of patentability of the claims is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior art product was made by a different process. See MPEP 2113. In this regard, both claimed products and the prior art products would be the same or substantially the same. Regarding claim 11, the combined teachings, particularly Higashi discloses wherein the sputtered metal layer 4 comprises a plurality of metal layers (i.e., nickel and gold layers- ¶¶0069, 0074-0075). Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over the combined teachings of Nagarajan, Christianson and Higashi in further view of Koike et al. (US 2022/0324231 A1, hereinafter “Koike”). Regarding claim 12, the combined teachings, particularly Higashi discloses wherein the plurality of metal layers comprises at least a nickel layer (¶0069), and which is used to protect from moisture (¶0077). Higashi does not expressly disclose wherein the plurality of metal layers comprises at least a stainless steel and a copper layer. Figure 9 of Koike discloses a semiconductor package comprising a metal layer 210 (“moisture-resistant protective film”- ¶0254) comprising a nickel or copper layer, and which is used to protect from moisture (¶0254). In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings such that wherein the plurality of metal layers comprises at least a copper layer as taught by Koike for the purpose of substituting art recognized equivalents known to be used for the same purpose (MPEP 2144.06), specifically utilizing a suitable and well-known type of metal layer used to protect from moisture (Koike ¶0254). Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over the combined teachings of Nagarajan and Christianson in further view of Chengalva et al. (US 2005/0077614 A1, hereinafter “Chengalva”). Regarding claim 9, the combined teachings do not expressly disclose wherein the substrate comprises an FR4 material. Figure 2 of Chengalva disclose a semiconductor package comprising a substrate 18 (“substrate”- ¶0018) which comprises a FR4 material (¶0018). In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combine teachings such that the substrate comprises an FR4 material as taught by Chengalva for the purpose of utilizing a suitable and well-known substrate material (Chengalva ¶0018). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over the combined teachings of Nagarajan and Christianson in further view of Achehboune et al. (US 2020/0304920 A1, hereinafter “Achehboune”). Regarding claim 10, the combined teachings do not expressly disclose wherein the lid comprises an FR4 material. Figure 4 of Achehboune disclose a semiconductor package comprising a lid 410 (“cover”- ¶0057) which comprises a FR4 material (¶0057). In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings such that wherein the lid comprises an FR4 material as taught by Achehboune for the purpose of utilizing a suitable and typical type of composite material for a lid (Achehboune ¶0057). Allowable Subject Matter Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 5 (which claims 6-7 depend from), the prior art of record including Nagarajan and/or Christianson, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the wall element delimits an aperture spaced from the lip surface”. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C CHANG/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

May 16, 2023
Application Filed
Feb 11, 2026
Non-Final Rejection mailed — §103
Apr 15, 2026
Response Filed
May 13, 2026
Final Rejection mailed — §103
May 27, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+14.5%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 647 resolved cases by this examiner. Grant probability derived from career allowance rate.

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