DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/10/2025 has been entered.
Response to Amendment
Applicant’s amendment filed on 11/10/2025 is acknowledged. Claims 1-2 have been amended.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites “a semicondcutor material” in the last line. Please correct the misspelling word.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4, 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites “the fin comprises a bottom fin and a channel layer” in line 6. This is unclear whether this channel layer is the same or different than the channel layer defined in line 9 of claim 1. For the purpose of examination, it is interpreted that the two instances can be different channel layers.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 9431517 B2).
Regarding claim 1, Chen teaches a semiconductor structure (structure in Fig. 10 of Chen, which is formed by method in Figs. 1-10), comprising:
a substrate (101), comprising a device region (region where the first and second devices 1000-1001 are located) and a zero mark region (region of alignment mark 103), wherein the device region is separated from the zero mark region, the device region comprises a first device subregion (region of the device 1000) configured for use in forming a first-type transistor (the language of “configured for use in…” is an intended use or functional property of the region which only requires that a first-type transistor can be formed on this region. Device 1000 is a transistor) and a second device subregion (region of device 1001) configured for use in forming a second-type transistor (this language of “configured for use in forming a second-type transistor” is an intended use or functional property of the region. This is treated similarly to the first device subregion above. Device 1001 is a transistor);
a fin (any of the pillars 901/903 in Fig. 9-10), protruding on the substrate in the device region;
a zero mark trench (trench of alignment mark 103, as shown in Figs. 1 & 10), located inside the substrate in the zero mark region, wherein a top portion of the zero mark trench is flush with a top portion of the substrate (the term “top portion” is interpreted as a three-dimensional part of the trench/substrate, not a two-dimensional surface. This is as shown in Fig. 10 of Chen); and
a dielectric layer (third hard mask 705 in Fig. 7-10), filled in the zero mark trench (see Fig. 10), wherein a channel layer (601-603 in Figs. 7-10) is located between a side wall of the zero mark trench and the dielectric layer (as shown in Figs. 9-10), and between a bottom portion of the zero mark trench and the dielectric layer (as shown in Fig. 8, the hard mask 705 layer has a slanted sidewall, so it is on the semiconductor layer 601-603), and a material of the channel layer is a semicondcutor material (as described in column 7 line 60 to column 8 line 38 of Chen).
Regarding claim 6, Chen teaches all limitations of the semiconductor structure according to claim 1, and also teaches wherein the material of the dielectric layer comprises at least one of silicon nitride (column 8 line 63 of Chen), silicon oxide, silicon oxycarbide, silicon oxynitride, or silicon oxycarbonitride.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, and further in view of Doris et al. (US 2016/0233241 A1).
Regarding claim 2, Chen teaches all limitations of the semiconductor structure according to claim 1, and also teaches wherein: in the first device subregion, the fin comprises a bottom fin layer (portions of pillars 901-903 rising from well 203 and 405, as shown in Fig. 9 of Chen) and a channel layer (607 and 605) located at a top portion of the bottom fin layer, where the material of the channel layer is different from the material of the bottom fin layer (as described in column 6 lines 9-15 of Chen).
But Chen does not teach that wherein channel materials of the first-type transistor and the second-type transistor are different.
Doris teaches a device region comprises a pFET device (101 in Fig. 13 of Doris) and a nFET device (102 in Fig. 13 of Doris), where channel materials of the first-type transistor and the second-type transistor are different (as stated in [0034] of Doris, the channel material for pFET fin 140 is SiGe. Meanwhile, [0032] states that the channel material for nFET fin 110 is Si).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the channel materials of the first-type transistor and second-type transistor different from each other in order to obtain better mobilities for appropriate type of transistors.
Regarding claim 3, Chen in view of Doris teaches all limitations of the semiconductor structure according to claim 2, and also teaches wherein channel conductivity types of the first-type transistor and the second-type transistor are different (as taught in column 5 lines 50-54 of Chen).
Regarding claim 4, Chen in view of Doris teaches all limitations of the semiconductor structure according to claim 2, and also teaches wherein the material of the channel layer comprises silicon, silicon germanium, germanium, or a III-V group semiconductor material (as taught in Doris above).
Regarding claim 7, Chen in view of Doris teaches all limitations of the semiconductor structure according to claim 2, but does not explicitly teach wherein a distance between a bottom portion of the dielectric layer and a top portion of the fin is from 100 Å to 1000 Å (the definition of the bottom portion of the dielectric is arbitrary, thus, it can be defined to be any portion from the bottom surface of layer 103 of Fig. 10 of Chen to almost close to the top surface of the dielectric layer, to be about 10nm from the top surface. Similarly, the top portion of the fin can be arbitrarily defined to be any thickness of the pillars 901/903. For example, the top portion of the fin and the bottom portion of the dielectric layer can be defined so that the distance is more or less the same as the thickness of the channel layer 601/605/607).
Chen teaches that the channel layer has thickness ranging from 15nm to 40nm, which is within the claimed range. Since it has been held that in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, it would be obvious that one of ordinary skill in the art would have made the distance between a bottom portion of the dielectric layer and a top portion of the fin is from 100 Å to 1000 Å (See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997)).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen.
Regarding claim 5, Chen teaches all limitations of the semiconductor structure according to claim 1, but does not explicitly teach wherein a distance between a bottom portion of the zero mark trench and a top portion of the fin is from 600 Å to 1500 Å (the definition of the bottom portion of the dielectric is arbitrary, thus, it can be defined to be any portion from the bottom surface of layer 103 of Fig. 10 of Chen to almost close to the top surface of the dielectric layer, to be about 10nm from the top surface. Similarly, the top portion of the fin can be arbitrarily defined to be any thickness of the pillars 901/903. For example, the top portion of the fin and the bottom portion of the dielectric layer can be defined so that the distance is more or less the same as the thickness of the channel layer 601/605/607).
Chen teaches that the channel layer has thickness ranging from 15nm to 40nm, which is within the claimed range. Since it has been held that in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, it would be obvious that one of ordinary skill in the art would have made the distance between a bottom portion of the dielectric layer and a top portion of the fin is from 100 Å to 1000 Å (See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997)).
Conclusion
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898