DETAILED ACTION
This Office action responds to the Amendment file on December 3, 2025, responding to the Office action mailed on September 3, 2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant cancelled Claim 4. Accordingly, pending in the application are claims 1-3 and 5-20.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
Applicant’s amendment to the paragraph (¶) [0060] of the specification has overcome the objection to the disclosure and one of the Drawing objections, as previously set forth in the Non-Final Office action mailed on September 3, 2025. However, Applicant’s amendment to the ¶ [0059] of the specification to overcome the Drawings objection, has introduced new matter. Hence the amended ¶ [0059] should not be entered. See the objection to the amended ¶ [0059] of the specification, below for detail explanation.
Applicant’s amendment to Figures 1 and 2 have overcome two of the Drawing objections. However, other Drawing objections stand. See the Drawing objection below for detail explanation.
Response to Arguments
Applicant’s arguments with respect to the claims filed on December 3, 2025 have been considered, but are moot in view of the new grounds of rejections.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show “the third through-via 443 protrudes from the second semiconductor substrate 210 into the semiconductor substrate 310” in FIG. 12 as described in the paragraph (¶) [0059] of the specification. It is confusing because the third through-via 443 only in the third semiconductor substrate 310, not in the second semiconductor 210 in FIG. 12. The second through-via 442 is in the second semiconductor 210. Neither the second through-via 442 nor the third through-via 443 protrude from their respective semiconductor substrate as shown in Figures 12 and 13. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The amendment filed December 3, 2025 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: “the third through-via 443 protrudes from the second semiconductor substrate 210 into the semiconductor substrate 310”. There is the second through-via 442 in the second semiconductor substrate 210, underneath the third through-via 443 in the third semiconductor substrate 310. The second semiconductor substrate 210 does NOT have the third through-via 443 that can protrude from the second semiconductor substrate 210 into the third semiconductor substrate 310.
Applicant is required to cancel the new matter in the reply to this Office Action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, 8, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Suh (KR 10-1078721) in view of Tsai et al. (Tsai hereinafter) (US 2022/0359468) and in view of Kang et al. (Kang hereinafter) (US 6,031,2811) and further in view of Lee et al. (Lee hereinafter) (US 8,030,747).
Regarding Claims 1-3, 7, 8, and 17:
Suh (see FIG. 1) teaches
{1} a semiconductor chip stack structure comprising: a first semiconductor chip 110 comprising a first semiconductor substrate, a first redistribution layer 120 on the first semiconductor substrate and comprising a first redistribution pattern, and a first pad 130 on an outermost side of the first redistribution layer, and a first passivation layer 150 on the first redistribution layer and covering at least a portion of the first pad; a second semiconductor chip 210 comprising a second semiconductor substrate, a second redistribution layer 220 on the second semiconductor substrate and comprising a second redistribution pattern, and a second pad 230 on an outermost side of the second redistribution layer, and a second passivation layer 250 on the second redistribution layer and covering at least a portion of the second pad, the second semiconductor chip being stacked on the first semiconductor chip such that the first pad and the second pad are bonded to each other with the first redistribution layer and the second redistribution layer facing each other, and an area of the second semiconductor chip being smaller than an area of the first semiconductor chip; a first metal wire 400 on the first semiconductor chip; a molding member 500 on the first semiconductor chip and at least a portion of each of the second semiconductor chip, the first metal wire and wherein the first pad and the second pad are in direct contact with each other;
{2} the first metal wire comprises a first-first metal wire at least partially inclined in a direction toward the second metal wire, and the second metal wire is at least partially inclined in a direction toward the first-first metal wire; {3} the first metal wire further comprises a first-second metal wire extending substantially vertically, and the second metal wire is closer to the first-first metal wire than the first-second metal wire;
{7} a semiconductor chip stack structure comprising: a first semiconductor chip 110 comprising a first semiconductor substrate, a first redistribution layer 120 on the first semiconductor substrate and comprising a first redistribution pattern, and a first pad 130 on an outermost side of the first redistribution layer, and a first passivation layer 150 on the first redistribution layer and covering at least a portion of the first pad; a second semiconductor chip 210 comprising a second semiconductor substrate, a second redistribution layer 220 on the second semiconductor substrate and comprising a second redistribution pattern, and a second pad 230 on an outermost side of the second redistribution layer, and a second passivation layer 250 on the second redistribution layer and covering at least a portion of the second pad, the second semiconductor chip being stacked on the first semiconductor chip such that the first pad is bonded to the second pad and the first redistribution layer faces the second redistribution layer, and an area of the second semiconductor chip being smaller than an area of the first semiconductor chip; a first metal wire 400 on the first semiconductor chip; and a molding member 500 on the first semiconductor chip and at least a portion of each of the second semiconductor chip and the first metal wires wherein the first pad and the second pad are in direct contact with each other; and
{17} a semiconductor package comprising: a semiconductor chip stack structure on the PCB, wherein the semiconductor chip stack structure comprises: a first semiconductor chip 110 comprising a first semiconductor substrate, a first redistribution layer 120 disposed on the first semiconductor substrate and comprising a first redistribution pattern, and a first pad 130 on an outermost side of the first redistribution layer and a first passivation layer 150 on the first redistribution layer and covering at least a portion of the first pad; a second semiconductor chip 210 including a second semiconductor substrate, a second redistribution layer 220 on the second semiconductor substrate and comprising a second redistribution pattern, and a second pad 230 on an outermost side of the second redistribution layer, and a second passivation layer 250 on the second redistribution layer and covering at least a portion of the second pad, the second semiconductor chip stacked on the first semiconductor chip such that the first pad is bonded to the second pad with the first redistribution layer facing the second redistribution layer, and an area of the second semiconductor chip being smaller than an area of the first semiconductor chip; a first metal wire 400 on the first semiconductor chip; and a molding member 500 on the first semiconductor chip and at least a portion of each of the second semiconductor chip and the first metal wires wherein the first pad and the second pad are in direct contact with each other.
Suh teaches a portion of the conductive wire 400 can be substantially vertically connected to the lower connection pad 310 within the first semiconductor package 100, an insulating layer 150 on the sides and a portion of the top of the first redistribution layer 120 and an insulating layer 250 on the sides and a portion of the top of the second redistribution layer 220, the second bridge member 230 being electrically connected to the first bridge member 130, and the first semiconductor chip being on a substrate 300.
However, Suh does not explicitly teach {1} a second metal wire on the second semiconductor chip; a molding member 500 on at least a portion of the second metal wire; an upper surface of each of the first metal wire and the second metal wire is exposed from an upper surface of the molding member; the first passivation layer and the second passivation layer are in direct contact with each other; {7} the first passivation layer and the second passivation layer are in direct contact with each other; {8} a second metal wire on the second semiconductor chip, wherein the molding member is on at least a portion of the second metal wire, wherein an upper surface of each of the first metal wire and the second metal wire is exposed from an upper surface of the molding member, and wherein at least a portion of each of the first metal wire and the second metal wire is inclined in a direction toward each other; and {17} a printed circuit board (PCB); the first passivation layer and the second passivation layer are in direct contact with each other.
Tsai (see FIG. 9 and ¶ [0027], [0014], [0015]) teaches a die 100 comprising a semiconductor substrate 120, the interconnection 104, the dielectric layer 106, the conductors 108, and the TSVs 110; a die 200 comprising a semiconductor substrate 202, an interconnection structure 204, a dielectric layer 206, and a plurality of conductors 208 and “the conductors 208 of the dies 200 are substantially aligned and in direct contact with some of the conductors 108 of the semiconductor wafer WS”.
Kang (see Abstract and col.8/ll.46-58 and FIGs. 6-16) teaches “a semiconductor IC device is provided with dummy bonding wires to prevent or reduce the wire displacement by blocking the remaining bonding wires from direct exposure to the molding resin flow front in the molding cavity … does not cause a short in the device … the size … is thereby reduced by increasing the allowable length of the bonding wires in the device, resulting in improved yields and lower production costs” and “ the wire 130h (‘exposed wire’) adjacent to the wire 130g is directly exposed to the molding resin flow from 142 and subjected to the most sweep and resulting shorts”, “a dummy bonding wire 136 is provided between the exposed wire 130h and the smaller wire 130g … the dummy bonding wire 136 has the same height ‘h2’ as the exposed wire 130h" and teaches a portion of the dummy bonding wire 136 being substantially vertical connecting to the chip 110 and the chip 110 being on a printed circuit board (PCB) 220 and the bonding wires and dummy bonding wires surrounding the chip.
Lee (see col. 7/ll.6-8 and FIGs. 1-4, 6-22, and 24-29) teaches “at least a portion of the dummy bonding wires 155 are exposed by the first proactive layer 160”, “the second protective layer 260’ has been formed such that portions of the dummy bonding wires 255 are exposed”, “the first chip 135 has a greater area than the second chip 235 … the second chip 1235 may have a greater area than the first chip 135a”, the third chip 435 has smaller area than the second chip 235, and a variety of ways to connect the upper bonding wires with lower bonding wires, such as direct in contact, through contact pad, through connection pad, or through interposer structure.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Suh to (1) include the teaching of Tsai to interconnect two dies through dielectric layer and conductors from each of the dies without gaps being filled by encapsulation as the semiconductor packaging advances with newer techniques; to (2) include the teaching of Kang to form dummy bonding wires in desirable shape/curvature to reduce the wire replacement and to prevent short during the formation of molding members and to specify the first semiconductor package 300 to be on the printed circuit board supporting the stacked chips above in order to withstand physical stress and to lessen the damages from impacts, moisture, and heat; and further to (3) include the teaching of Lee to expose the lower dummy bonding wires from the lower molding member/protective layer when they are required to make additional connection to upper dummy bonding wires within the upper molding member in order to continue its purpose of reducing the wire replacement and improving yields and lowering production costs and to pile the chips with less areas on the top in order to save cost by integrating more chips of different kinds of electronic devices in one semiconductor package.
Claims 5, 9, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Suh (KR 10-1078721) in view of Tsai et al. (Tsai hereinafter) (US 2022/0359468) and in view of Kang et al. (Kang hereinafter) (US 6,031,2811) and further in view of Lee et al. (Lee hereinafter) (US 8,030,747) as applied to claim 1, 8, or 17 above, and further in view of Kim (US 2011/0156233).
Regarding Claims 5, 9, and 18:
Suh in the device of Tsai and Kang in view of Lee teaches the stacked chips package except for {5, 9, 18} a through-via passing through the second semiconductor substrate and protruding from the second semiconductor substrate, wherein the molding member is on at least a portion of the through-via, and an upper surface of the through-via is exposed from an upper surface of the molding member and {18} at least a portion of each of the first metal wire and the second metal wire is inclined in a direction toward each other, wherein a third pad is further disposed on a side of the first semiconductor substrate opposite to a side on which the first redistribution layer is disposed, wherein the semiconductor chip stack structure is disposed on the PCB so that the third pad faces the PCB, and wherein the third pad is connected to the PCB through a connection member.
Kim (see ¶ [0006] and [0042]-[0047] and FIGs. 1 and 5) teaches a plurality of first through-electrodes 114 penetrating the first semiconductor chip 110, a plurality of second through-electrodes 124 formed at positions corresponding to the first through-electrodes 114 and penetrating one or more stacked second semiconductor chips 120, and an encapsulation member 140 and teaches “by using through-electrodes, I/O pads can be bonded with a fine pitch allowing the number of I/O pads to be increased … signal transmission speed among the semiconductor chips can be improved”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Suh in the device of Tsai and Kang and further in view of Lee to further include the teaching of Kim to form through-electrodes between any two chips to make electrical connections for various purposes, such as input/out and to extend the through-electrodes outside of the topmost chips to be enclosed by the encapsulation members and to form bonding pads on the redistribution layer of the first chip to be electrically connected the PCB which is a well-known interconnection technique.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Suh (KR 10-1078721) in view of Tsai et al. (Tsai hereinafter) (US 2022/0359468) and in view of Kang et al. (Kang hereinafter) (US 6,031,2811) and further in view of Lee et al. (Lee hereinafter) (US 8,030,747) as applied to claim 1 above, and further in view of Joo et al. (Joo hereinafter) (US 8,445,927) and in view of Yuan et al. (Yuan hereinafter) (US 2009/0315171).
Regarding Claim 6:
Suh in the device of Tsai and Kang in view of Lee teaches a transparency of the molding member is higher than a transparency of the first semiconductor substrate and a transparency of the second semiconductor substrate.
Joo (see col.2/ll.33-36, col.4/ll.40-45, col.5/ll.10-15, and col.8/ll.5-12) teaches a light emitting diode package and “the substrate is made of light-transmitting material in order to reflect light emitted from the LED chip through the encapsulant including the reflection material”, “the substrate 110 on which the molding material 130 and the encapsulant 140 are separately coated is made of light-transmitting materials with relatively high light-transmissivity”, “when the molding material 130 … in order to improve luminous efficiency when the light emitted from the LED chip 120 is emitted through the fluorescent material of the molding material 130”, and “the molding material has a wave-length conversion feature, the encapsulant has a reflectivity feature, and the substrate has a transparency feature, and the molding material and the encapsulant, having different optical features”.
Yuan (see ¶ [0043]) teaches “a conductive trace 106 … is visible due to the transparency of the molding compound 12”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Suh in the device of Tsai and Kang and further in view of Lee to include the teaching of Joo to specify the function of the stacked chips, such as display device and to form the substrate with transparent material in order to reflect the light emitted from the LEDs and to further include the teaching of Yuan to anticipate the molding member having transparency in order to make the light emitted from the LEDs to external from the package and to select higher transparent material for the molding member than the substrates because the molding member is the topmost structure of the package to transmit the light from the LEDs to external for improved visibility and contrast.
Claims 10-16, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Suh (KR 10-1078721) in view of Tsai et al. (Tsai hereinafter) (US 2022/0359468) and in view of Kang et al. (Kang hereinafter) (US 6,031,2811) and further in view of Lee et al. (Lee hereinafter) (US 8,030,747) as applied to claim 7 or 17 above, and further in view of Liu et al. (Liu hereinafter) (CN 103296014).
Regarding Claims 10-16, 19, and 20:
Suh in the device of Tsai and Kang in view of Lee and Kim teaches the stacked chips package except for a third redistribution layer on the third semiconductor substrate and comprising a third redistribution pattern and how the third semiconductor chip is connected to other semiconductor chips.
Liu (see ¶ [0050] and Figures 1-19) teaches a patch material 103 being sandwiched between a second semiconductor chip 102 and a first semiconductor chip 101 where a through electrodes 115 may be formed within both semiconductor chips or two redistribution layers 10B being sandwiched between both semiconductor chips and teaches “the patch material can be polymer patch material, lead solder or lead-free solder or gold-tin solder or gold-silicon solder.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Suh in the device of Tsai and Kang and further in view of Lee and Kim to further include the teaching of Liu to stack a third semiconductor chip comprising electrodes, the redistribution layer, and pads, above and bonded to the second semiconductor chip in order to integrate more chips within a package and to meet the design configurations of how the chips are stacked up and connected with each other and external components.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
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/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814