Prosecution Insights
Last updated: August 06, 2026
Application No. 18/198,515

EPITAXIAL ScxAl1-xN SEMICONDUCTOR DEVICES

Final Rejection §103
Filed
May 17, 2023
Priority
May 20, 2022 — provisional 63/344,270
Examiner
MCCUTCHEON, COLIN RUSSELL
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Comell University
OA Round
2 (Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
45 granted / 52 resolved
+18.5% vs TC avg
Strong +22% interview lift
Without
With
+21.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
18 currently pending
Career history
71
Total Applications
across all art units

Statute-Specific Performance

§103
65.3%
+25.3% vs TC avg
§102
28.1%
-11.9% vs TC avg
§112
6.6%
-33.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 52 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment & Claims’ Status The Amendment filed on 5/26/2026 has been entered. Claims 1-17 and 21-24 are currently pending and being examined. Claims 1-2, 5-8, 10, and 16 have been amended. Claims 18-20 have been cancelled. Claims 21-24 have been newly added. Claim Objections Claims 1-17 and 21-24 are objected to because of the following informalities: Re Claim 1, the semicolon next to “comprising” in line 1 should be a colon for grammatical correctness. Re Claim 1, lines 2-3 should read, and will be interpreted as, “a not intentionally doped first III N layer, where the first III N includes at least one Group 3 semiconductor element;” for proper antecedent basis and consistent syntax. Lines 4-7 should read, and will be interpreted as, “a second III N barrier layer, where the second III N includes at least one Group 3 semiconductor element different from the Group 3 semiconductor element in the not intentionally doped first III N layer, the second III N barrier layer being disposed on the not intentionally doped first III N layer;” for proper antecedent basis and consistent syntax. Line 8 should read, and will be interpreted as, “a Sc--xAl1-xN layer epitaxially disposed on the second III N barrier layer; and” for proper antecedent basis. Lines 9-10 should read, and will be interpreted as, “a third III N layer, where the third III N includes at least one Group 3 semiconductor element different from Aluminum; the third III N layer disposed on the Sc--xAl1-xN layer,” for proper antecedent basis and consistent syntax. Re Claim 7, in lines 2-3 and lines 4-5, “a location of the 2D electron gas forms” should read, and will be interpreted as, “a location where the 2D electron gas forms” for grammatical correctness. Re Claim 8, lines 5-7 should read, and will be interpreted as, “an electrically conductive gate contact disposed between the first electrically conducting contact and the second electrically conducting contact and disposed on the third III N layer.” for proper antecedent basis. Re Claim 16, lines 5-6 should read, and will be interpreted as, “an electrically conductive gate contact disposed between the first electrically conducting contact and the second electrically conducting contact and disposed on the GaN layer.” for proper antecedent basis. It is also unclear in line 6 of Claim 16 which “GaN layer” in Claim 10 is being referred to, for the purposes of examination, it will be assumed to be referring to the third III N layer. Claims 2-17 and 21-24 inherit the objections to Claim 1. Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Vishwanath et al (US 20210399119 A1, of record, hereafter Vishwanath). Re Claim 1, Vishwanath discloses a semiconductor device (FIG. 1; [0023]-[0029]) comprising; a first III N layer (102; [0025]), III being one or more Group 3 semiconductor element ([0025], Ga); a second III N barrier layer (103; [0026]), where the second III N includes at least one III element different from the III element in the first III N layer ([0026], Al), the second III N barrier layer (103) being disposed on the first III N layer (102; [0026]); a Sc--xAl1-xN layer (105; [0026]) epitaxially disposed on the second III N layer (103; [0028]); and a third III N layer (106; [0025]), where the third III includes at least one III element different from Aluminum ([0025], Ga); the third III N layer (106) disposed on the Sc--xAl1-xN layer (105; [0026]), wherein the second III N barrier layer (103) is disposed between the first III N layer (102) and the Sc--xAl1-xN layer (105; [0026]); wherein the Sc--xAl1-xN layer (105) is disposed between the second III N barrier layer (103) and the third III N layer (106; [0026]). Vishwanath does not explicitly disclose that the first III N layer (102) is not intentionally doped, but in [0003] of Vishwanath it is explained that the narrower bandgap layer (which the first III N layer 102 is, being GaN) is undoped such that there are no donor atoms to cause scattering. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Vishwanath with the limitations taught separately by Vishwanath to have the first III N layer (102) be not intentionally doped to prevent scattering from donor atoms and yield higher mobility as taught by Vishwanath ([0003]). Re Claim 2, Vishwanath teaches the device according to Claim 1, while further disclosing wherein composition and thickness of the second III N barrier layer (103) are selected such that a 2D electron gas forms at a boundary between the second III N barrier layer (103) and the not intentionally doped first III N layer (102; [0003], by nature of accumulated electrons being in the narrower bandgap semiconductor layer). Re Claim 10, Vishwanath teaches the device according to Claim 1, while further disclosing wherein the not intentionally doped first III N layer (102) is a not intentionally doped GaN layer (102; [0025]), the second III N barrier layer (103) is an AlN layer (103; [0026]), and the third III N layer (106) is a GaN layer (106; [0025]). Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Vishwanath, as applied to Claim 1, further in view of Wang et al (US 2025/0169097 A1, of record, hereafter Wang). Re Claim 3, Vishwanath teaches the device according to Claim 1, but does not explicitly disclose wherein the Sc--xAl1-xN layer (105) is a ferroelectric layer. However, Wang teaches a semiconductor device (FIG. 11A) wherein the Sc--xAl1-xN layer (ScAlN; [0103]) is a ferroelectric layer ([0011]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 1 with the limitations taught by Wang to specify the Sc--xAl1-xN layer (Vishwanath: 105) is a ferroelectric layer to maintain an internal electrical polarization to modulate the threshold voltage of the device as taught by Wang ([0011]). Re Claim 4, Vishwanath and Wang teach the device according to Claim 3, while Wang further teaches wherein x is between about 0.1 and 0.36 ([0096]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 3 with the limitations taught by Wang to specify the “x” value in the Sc--xAl1-xN layer (Vishwanath: 105) to be between 0.1 and 0.36 to allow for effective polarization as taught by Wang ([0096]). Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Vishwanath, as applied to Claim 1, further in view of Cetnar et al (US 2023/0327011 A1, of record, hereafter Cetnar). Re Claim 5, Vishwanath teaches the device according to Claim 1, but does not explicitly disclose the device further comprises: an n-doped drain region recessed into or disposed on the not intentionally doped first III N layer (102) and in contact with a first end of the second III N barrier layer (103) and with a first end of the Sc--xAl1-xN layer (105); and an n-doped source region recessed into or disposed on the not intentionally doped first III N layer (102) and in contact with a second end of the second III N barrier layer (103) and with a second end of the Sc--xAl1-xN layer (105). However, Cetnar discloses a semiconductor device (FIG. 2; [0042]-[0044]) comprising: an n-doped drain region (D, with metal contacts thereupon; [0030]) recessed into or disposed on the not intentionally doped first III N layer (220; [0043]) and in contact with a first end of the second III N barrier layer (230; [0043]) and with a first end of the Sc--xAl1-xN layer (240; [0043]); and an n-doped source region (S, with metal contacts thereupon; [0030]) recessed into or disposed on the not intentionally doped first III N layer (220; [0043]) and in contact with a second end of the second III N barrier layer (230; [0043]) and with a second end of the Sc--xAl1-xN layer (240; [0043]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 1 with the limitations taught by Cetnar to utilize n-dope source/drain regions (Cetnar: S, D) in contact with the direct 2DEG generating layers to allow for electrical connection of the 2DEG to the device and to effectively operate the HEMT structure as taught by Cetnar ([0030]). Re Claim 6, Vishwanath and Cetnar teach the device according to Claim 5, while Vishwanath further discloses wherein composition and thickness of the second III N barrier layer (103) are selected such that a 2D electron gas forms at a boundary between the second III N barrier layer (103) and the not intentionally doped first III N layer (102; [0003], by nature of accumulated electrons being in the narrower bandgap semiconductor layer). Re Claim 7, Vishwanath and Cetnar teach the device according to Claim 6, while they do not explicitly disclose in the used embodiments of Cetnar wherein the n-doped drain region (Cetnar: S) is recessed into the not intentionally doped first III N layer (Cetnar: 220) up to or beyond a location of the 2D electron gas forms; and wherein the n-doped source region (Cetnar: S) is recessed into the not intentionally doped first III N layer (Cetnar: 220) up to or beyond a location of the 2D electron gas forms. Cetnar teaches in a separate embodiment (FIG. 1; [0029]-[0031]) wherein the n-doped drain region (D; [0030]) is recessed into the not intentionally doped first III N layer (120; [0030]) up to or beyond a location of the 2D electron gas forms ([0030]); and wherein the n-doped source region (S; [0030]) is recessed into the not intentionally doped first III N layer (120; [0030]) up to or beyond a location of the 2D electron gas forms ([0030]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 6 with the limitations taught by Cetnar to have the source/drain regions (Cetnar: S/D) recessed around the not intentionally doped III N layer (Cetnar: 220) to establish sufficient connection with the 2DEG channel as taught by Cetnar ([0030]). Re Claim 8, Vishwanath and Cetnar teach the device according to Claim 5, while Cetnar further teaches the device comprises: a first electrically conducting contact (Au/Ti; [0030]) disposed on the n-doped source region (S; [0030]); a second electrically conducting contact (Au/Ti; [0030]) disposed on the n-doped drain region (D; [0030]). Vishwanath further teaches an electrically conductive gate contact (114; [0030]) disposed between the electrically conductive contacts (112, metal contacts; [0030]) on the n-doped source and drain region (112 implanted sections, n-doped taught by Cetnar) and disposed on the further III N layer (106; [0051], on the side of). No further modifications made, see rejection of Claim 5 for obviousness statement. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Vishwanath and Cetnar, as applied to Claim 7, further in view of Hickman et al (US 2020/0388701 A1, hereafter Hickman). Re Claim 9, Vishwanath and Cetnar teach the device according to Claim 7, but they do not explicitly disclose wherein a maximum cutoff frequency is at least 150 GHz. However, Hickman teaches a semiconductor device (FIG. 1; [0039]-[0054]) comprising wherein a maximum cutoff frequency is at least 150 GHz ([0052], [0041] for Sc content). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 7 with the limitations taught by Hickman to replace the gate electrode structure (Vishwanath: 114) of Vishwanath with the T-shaped structure (Hickman: 145) of Hickman to yield the predictable result of increasing the maximum cutoff frequency as taught by Hickman ([0052]). Claims 11-12 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Vishwanath, as applied to Claim 10, further in view of Cetnar. Re Claim 11, Vishwanath teaches the device according to Claim 10, but does not explicitly disclose the device further comprises: an n-doped drain region recessed into or disposed on the not intentionally doped GaN layer (102) and in contact with a first end of the AlN barrier layer (103) and with a first end of the Sc--xAl1-xN layer (105); and an n-doped source region recessed into or disposed on the not intentionally doped GaN layer (102) and in contact with a second end of the AlN barrier layer (103) and with a second end of the Sc--xAl1-xN layer (105). However, Cetnar discloses a semiconductor device (FIG. 2; [0042]-[0044]) comprising: an n-doped drain region (D, with metal contacts thereupon; [0030]) recessed into or disposed on the not intentionally doped GaN layer (220; [0043]) and in contact with a first end of the AlN barrier layer (230; [0043]) and with a first end of the Sc--xAl1-xN layer (240; [0043]); and an n-doped source region (S, with metal contacts thereupon; [0030]) recessed into or disposed on the not intentionally doped GaN layer (220; [0043]) and in contact with a second end of the AlN barrier layer (230; [0043]) and with a second end of the Sc--xAl1-xN layer (240; [0043]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 10 with the limitations taught by Cetnar to utilize n-dope source/drain regions (Cetnar: S, D) in contact with the direct 2DEG generating layers to allow for electrical connection of the 2DEG to the device and to effectively operate the HEMT structure as taught by Cetnar ([0030]). Re Claim 12, Vishwanath and Cetnar teach the device according to Claim 11, while Vishwanath further discloses wherein thickness of the AlN layer (103) are selected such that a 2D electron gas forms at a boundary between the AlN barrier layer (103) and the not intentionally doped GaN layer (102; [0003], by nature of accumulated electrons being in the narrower bandgap semiconductor layer). Re Claim 15, Vishwanath and Cetnar teach the device according to Claim 12, while they do not explicitly disclose in the used embodiments of Cetnar wherein the n-doped drain region (Cetnar: S) is recessed into the not intentionally doped GaN layer (Cetnar: 220) up to or beyond a location of the 2D electron gas; and wherein the n-doped source region (Cetnar: S) is recessed into the not intentionally doped GaN layer (Cetnar: 220) up to or beyond a location of the 2D electron gas. Cetnar teaches in a separate embodiment (FIG. 1; [0029]-[0031]) wherein the n-doped drain region (D; [0030]) is recessed into the not intentionally doped GaN layer (120; [0030]) up to or beyond a location of the 2D electron gas ([0030]); and wherein the n-doped source region (S; [0030]) is recessed into the not intentionally doped GaN layer (120; [0030]) up to or beyond a location of the 2D electron gas ([0030]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 12 with the limitations taught by Cetnar to have the source/drain regions (Cetnar: S/D) recessed around the not intentionally doped III N layer (Cetnar: 220) to establish sufficient connection with the 2DEG channel as taught by Cetnar ([0030]). Re Claim 16, Vishwanath and Cetnar teach the device according to Claim 11, while Cetnar further teaches the device comprises: a first electrically conducting contact (Au/Ti; [0030]) disposed on the n-doped source region (S; [0030]); a second electrically conducting contact (Au/Ti; [0030]) disposed on the n-doped drain region (D; [0030]). Vishwanath further teaches an electrically conductive gate contact (114; [0030]) disposed between the electrically conductive contacts (112, metal contacts; [0030]) on the n-doped source and drain region (112 implanted sections, n-doped taught by Cetnar) and disposed on the GaN layer (106; [0051], on the side of). No further modifications made, see rejection of Claim 11 for obviousness statement. Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Vishwanath, as applied to Claim 10, further in view of Wang. Re Claim 13, Vishwanath teaches the device according to Claim 10, but does not explicitly disclose wherein the Sc--xAl1-xN layer (105) is a ferroelectric layer. However, Wang teaches a semiconductor device (FIG. 11A) wherein the Sc--xAl1-xN layer (ScAlN; [0103]) is a ferroelectric layer ([0011]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 10 with the limitations taught by Wang to specify the Sc--xAl1-xN layer (Vishwanath: 105) is a ferroelectric layer to maintain an internal electrical polarization to modulate the threshold voltage of the device as taught by Wang ([0011]). Re Claim 14, Vishwanath and Wang teach the device according to Claim 13, while Wang further teaches wherein x is between about 0.1 and 0.36 ([0096]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 13 with the limitations taught by Wang to specify the “x” value in the Sc--xAl1-xN layer (Vishwanath: 105) to be between 0.1 and 0.36 to allow for effective polarization as taught by Wang ([0096]). Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Vishwanath and Cetnar, as applied to Claim 15, further in view of Hickman. Re Claim 17, Vishwanath and Cetnar teach the device according to Claim 15, but they do not explicitly disclose wherein a maximum cutoff frequency is at least 150 GHz. However, Hickman teaches a semiconductor device (FIG. 1; [0039]-[0054]) comprising wherein a maximum cutoff frequency is at least 150 GHz ([0052], [0041] for Sc content). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 15 with the limitations taught by Hickman to replace the gate electrode structure (Vishwanath: 114) of Vishwanath with the T-shaped structure (Hickman: 145) of Hickman to yield the predictable result of increasing the maximum cutoff frequency as taught by Hickman ([0052]). Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Vishwanath, as applied to Claim 2, further in view of Hickman. Re Claim 21, Vishwanath teaches the device according to Claim 2, but does not explicitly disclose wherein an electron mobility in the 2D electron gas ranges from about 497 cm^2/Vs to about 1131 cm^2/Vs. However, Hickman teaches a semiconductor device (FIG. 1; [0039]-[0054]) comprising wherein an electron mobility in the 2D electron gas ranges from about 497 cm^2/Vs to about 1131 cm^2/Vs ([0047], [0041] for Sc content). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 2 with the limitations taught by Hickman to utilize the gradient barrier layer (Hickman: 115; [0041]) configuration of Hickman to yield the predictable result of an electron mobility in the 2D electron gas that ranges from about 497 cm^2/Vs to about 1131 cm^2/Vs as taught by Hickman ([0047]). Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Vishwanath and Cetnar, as applied to Claim 6, further in view of Hickman. Re Claim 23, Vishwanath and Cetnar teach the device according to Claim 6, but they do not explicitly disclose wherein an electron mobility in the 2D electron gas ranges from about 497 cm^2/Vs to about 1131 cm^2/Vs. However, Hickman teaches a semiconductor device (FIG. 1; [0039]-[0054]) comprising wherein an electron mobility in the 2D electron gas ranges from about 497 cm^2/Vs to about 1131 cm^2/Vs ([0047], [0041] for Sc content). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as discussed for Claim 6 with the limitations taught by Hickman to utilize the gradient barrier layer (Hickman: 115; [0041]) configuration of Hickman to yield the predictable result of an electron mobility in the 2D electron gas that ranges from about 497 cm^2/Vs to about 1131 cm^2/Vs as taught by Hickman ([0047]). Allowable Subject Matter Claims 22 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable (assuming outstanding objections were addressed) if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Re Claim 22, the prior art cannot anticipate, or render obvious, the limitations of: wherein an electron mobility in the 2D electron gas ranges from about 957 cm^2/Vs to about 1131 cm^2/Vs, in combination with the additionally claimed features of Claim 22. Re Claim 24, the prior art cannot anticipate, or render obvious, the limitations of: wherein an electron mobility in the 2D electron gas ranges from about 957 cm^2/Vs to about 1131 cm^2/Vs, in combination with the additionally claimed features of Claim 24. Response to Arguments Applicant’s arguments, see Remarks, filed 5/26/2026, with respect to the rejection(s) of Claim 1 under 35 U.S.C. 103 in view of Cetnar and Shealy have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Vishwanath under 35 U.S.C. 103. Applicant’s arguments have been reconsidered in light of the new rejections, but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892 /NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

May 17, 2023
Application Filed
Jan 26, 2026
Non-Final Rejection mailed — §103
May 26, 2026
Response Filed
Jun 26, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12701703
SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
3y 9m to grant Granted Aug 04, 2026
Patent 12696536
SEMICONDUCTOR DEVICE, INTEGRATED CIRCUIT, AND MULTI-VALUED LOGIC DEVICE INCLUDING THE SAME
3y 3m to grant Granted Jul 28, 2026
Patent 12685027
MRAM STRUCTURE WITH RAISED EDGE OF TUNNEL BARRIER LAYER
3y 11m to grant Granted Jul 14, 2026
Patent 12672457
STRETCHABLE DISPLAY PANEL AND MANUFACTURING METHOD THEREFOR
3y 8m to grant Granted Jun 30, 2026
Patent 12672386
CHIP WET-TRANSFERRING DEVICE
3y 1m to grant Granted Jun 30, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+21.9%)
3y 3m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 52 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month