Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I in the reply filed on 09/11/25 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-7, 11-12, and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sanfilippo et al., US Patent 6,331,470.
Sanfilippo et al. shows the invention as claimed including a method of making a semiconductor structure, the method comprising:
Providing a silicon-on-insulator substrate 30 comprising a first epitaxial layer 31 and a bulk silicon substrate 3 separated by a buried oxide layer 4;
Performing a local oxidation of silicon process in a region 32 of said silicon on insulator substrate to at least partially oxidize said first epitaxial silicon layer in said region (see, for example, figs. 1b, fig. 2a, and col. 4-lines 14-18);
Locally etching the silicon on insulator substrate in said region to create a trench 37 through said buried oxide layer and to said bulk silicon substrate (see, for example, fig. 2d and col. 4-lines 14-24);
Forming a second epitaxial layer 110b on aid bulk silicon substrate in said trench (see fig. 2f and col. 4-lines 42-46); and
Forming one or more semiconductor devices in said first and second epitaxial layer to form circuitry region 26 and a power portion 17 (see figs. 1a-2f, 3, and col. 2-line 41 to col. 5-line 15).
With respect to dependent claim 3, note that in Sanfilippo et al. said step of forming one or more semiconductor devices comprises forming a bipolar junction transistor (BJT) in said second epitaxial layer (see col. 4-lines 42-46 and col. 5-lines 1-15).
Concerning dependent claim 4, note that in Sanfilippo et al. discloses wherein said step of forming one or more semiconductor devices comprises forming one or more CMOS devices in said first epitaxial layer located over said buried oxide layer (see col. 5-lines 1-16).
With respect to dependent claim 5, Sanfilippo et al. discloses performing a second local oxidation 36 of silicon process to fully oxidize said first epitaxial layer in said region (see fig. 2a-2c and col. 4-lines 14-18).
Concerning dependent claim 6, the process of Sanfilippo et al. discloses wherein each local oxidation of silicon process comprises the following steps: depositing a nitride hard mask layer 6 on said substrate; depositing an oxide layer 5 on said substrate; depositing a photoresist 7 on the substrate, and patterning said photoresist to define said region 8 (see fig. 1a and its description).
Regarding dependent claim 7, note that the process of Sanfilippo et al. discloses wherein said local oxidation of silicon process partially oxidizes said first epitaxial layer in said region and thereby forms an oxide layer (32, see fig. 2a) on said first epitaxial layer in said region, the method further comprising etching said region to remove said oxide layer on said first epitaxial layer to expose said first epitaxial layer in said region 35 (see fig. 2b).
Concerning dependent claim 11, note that in Sanfilippo et al. the step of forming a second epitaxial layer 110b comprises forming said second epitaxial layer to have a thickness greater than a combined thickness of said buried oxide layer and said first epitaxial layer (see, for example, fig. 2f).
As to dependent claim 12, Sanfilippo et al. discloses further comprising, after forming said epitaxial layer, performing CMP to level an upper surface of said epitaxial layer (see fig. 2f and col. 4-lines 42-46).
With respect to dependent claim 14, Sanfilippo et al. discloses wherein said step of forming one or more semiconductor devices comprises selectively doping said first and second epitaxial layers (see fig. 3 and col. 5-lines 1-16).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sanfilippo et al., US Patent 6,331,470 in view of Liao et al., U.S. Patent 8,716,750.
Sanfilippo et al. is applied as above but does not expressly disclose forming a SiGe device in said second epitaxial layer. Liao et al. discloses forming an FET in a SiGe epitaxial layer (see. for example, col. 1-lines 10-25). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Sanfilippo et al. so as to utilize SiGe for the second epitaxial layer because it creates a stress in the device region which improves the mobility of the device.
Claim(s) 8-10 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Sanfilippo et al., US Patent 6,331,470.
Sanfilippo et al. is applied as above but does not expressly disclose the claimed post LOCOS processing steps. However, Sanfilippo et al. discloses forming a trench in layers after LOCOS processing (see figs. 2c-2f). Furthermore, official notice is taken that the claimed steps are prima facie steps in the art in order to form trench regions of fine dimensions with minimal contamination and would not lend patentability to the instant application.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sanfilippo et al., US Patent 6,331,470 in view of Pradhan et al., U.S. Patent 9,112,057.
Sanfilippo et al. is applied as above but does not expressly disclose providing shallow trench isolation to provide lateral isolation at least between said first and second epitaxial layers. Pradhan et al. discloses forming shallow trench isolation regions (STI) between epitaxial regions formed from layer 304 (see, for example, fig. 2D and its description). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Sanfilippo et al. so as to separate the epitaxial regions using shallow trench isolation because this is shown by Pradhan et al. to be an effective structure that can be used to isolate devices between different regions.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cheng et al., US 2016/0225768 discloses the formation of different devices in different epitaxial region materials (see abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571) 272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
November 16, 202554