DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
Status of the Application
This Office Action is in response to Applicant’s application 18/198,829 filed on March 31 2026 in which claims 1 to 20 are pending. Claims 10-20 are withdrawn from prosecution.
Drawings
The drawings submitted on May 17 2023 have been reviewed and accepted by the Examiner.
Priority
Receipt is acknowledged of paper submitted under 35 U.S.C. 119(a)-(d) or under 35 U.S.C. 120, 121, 365(c), or 386(c) which has been placed of record in the file.
Notation
References to patents will be in the form of (C: L) where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of (¶ XXXX).
Election/Restrictions
Applicant’s election without traverse of claims 1-9 in the reply filed on December 23 2025 is acknowledged. Claims 10-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 3, 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ho (US 2022/0093686 A1) in view of Liu (US 2021/0111341 A1).
Regarding claim 1, Ho teaches a semiconductor structure (Fig.4A- Fig.7) comprising:
a material layer (310; fig.4C; ¶ 0051);
a plurality of resistive random access memory cells (C00-C31, Fig.4A; ¶ 0051) are arranged on the material layer in an array, wherein the array comprises a first outer ring (outer ring can be memories formed on the right side of BL0; Fig. 4A), and the first outer ring consists of some of the plurality of resistive random access memory cells (i.e. C00, C10, C20 and C30; Fig.4A);
and a peripheral metal layer (M4; Fig.4A and Fig. 4C; ¶ 0044 and 0052), at least connects the plurality of resistive random access memory cells located in the first outer ring in series into a loop (memories C00, C10, C01, and C11 forms a loop; Fig.4A and Fig.4C).
Ho does not explicitly teach the first outer ring is located at the outermost ring of the array.
However, Liu teaches a similar memory device (202; Fig.2A and Fig.2B; ¶0036) a first outer ring is located at the outermost ring of the array (202; Fig.2B, 2C; 202 have an array of memory and the peripheral memory device (first outer ring formed on the farthest right side of 202) is located at the outermost ring of the array (the farthest memory formed on the peripheral memory device of Fig.2B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to have the first outer ring is located at the outermost ring of the array in the device of Ho as taught by Liu to improve the interconnect scheme for a 3D PCM memory device (¶0038).
Regarding claim 2, Ho teaches wherein each resistive memory wherein each resistive random access memory cell (202; Fig.2) comprises a lower electrode (316; Fig.3C; ¶ 0043), a resistive switching layer (322) and a top electrode (314; ¶ 0043) stacked in sequence.
Regarding claim 3, Ho teaches wherein the peripheral metal layer (M4; ¶ 0052) comprises a plurality of short metal line segments (short metal segment line; Fig.4C), wherein each short metal line segment spans the top electrodes of two resistive random access memory cells (M4 can be treated as a top electrode as shown in Fig.4C).
Regarding claim 4, Ho teaches wherein the peripheral metal layer further comprises a long metal line segment (M4; Fig.3), wherein one end of the long metal line segment is electrically connected to a resistive random access memory cell (M4 electrically connected to the C0-C11; Fig.3).
Examiners note: Limitation “short metal line” in claim 3 and “long metal line” in claim 4 do not have a numerical value or a frame feature so any metal line can be treated as short or long. The following limitation is a broad limitation and should be defined in the claim so the office knows exactly what is meant by “ling metal line” and “short metal line”.
Regarding claim 8, Ho teaches a bottom metal layer (M1) electrically connected to the lower electrodes (M3) of each of the plurality of resistive random access memory cells (C10).
Regarding claim 9, Ho teaches wherein the array further comprises a second outer ring (second outer ring for BL1; Fig.4A), which is composed of some of the plurality of resistive random access memory cells (C01-C11; Fig.4A), wherein the second outer ring (BL1) is adjacent to the first outer ring (BL0), and wherein the second outer ring is located inside the first outer ring of the array (the second outer ring is located on the inside of BL0), and the semiconductor structure further comprises a second peripheral metal layer (second M4; Fig.4A), which at least connects the plurality of resistive random access memory cells located in the second outer ring in series into another loop (M4 connects the first outer ring and a second outer ring; Fig.4A).
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Ho (US 2022/0093686 A1) in view of Liu (US 2021/0111341 A1) as applied for claim 1, and further in view of Sugimae (US 2016/0268343 A1).
Regarding claim 5, Ho as modified by Liu does not teach wherein the peripheral metal layer further comprises a contact pad electrically connected to the other end of the long metal line segment.
However, Sugimae teaches the peripheral metal layers (46; Fig.10I; ¶ 0043) further comprises a contact pad (41; ¶ 0066) electrically connected to the other end of the long metal line segment (46; Fig.10I).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to have the peripheral metal layer further comprises a contact pad electrically connected to the other end of the long metal line segment of Ho and Liu as taught by Sugimae to increase the ratio of the wiring area with respect to a memory cell.
Regarding claim 6, Ho and Liu as modified by Sugimae teaches further comprising a plurality of contact posts (44, 45 and 46; Fig.10I) electrically connected to the top electrodes of other resistive random access memory cells in the array (all the layers are electrically connected to the top electrode of the memory; Fig.10I).
Regarding claim 7, Ho and Liu as modified by Sugimae wherein each contact post only contacts the top electrode of one of the resistive random access memory cells (top electrode of each memory contacts 46; Fig.10I).
Response to Arguments
Applicant's arguments filed March 31 2026 have been fully considered but they are not persuasive.
Applicant’s Argument:
The Examiner interprets the metal layer M4 in Ho as a series loop. However, as shown in FIG. 4A and FIG. 4C of Ho, M4 is a continuous common bit line directly covering the top electrodes of multiple memory cells such as COO and C 10. Current from M4 is divided and flows into each cell, which constitutes a standard parallel circuit structure. In the parallel structure of Ho, even if a single memory cell is damaged, current on M4 can still flow to other cells. Ho cannot achieve the open-circuit testing effect of the present invention. Therefore, Ho does not teach or suggest connecting the memory cells in series into a loop.
Examiner’s Response:
Examiner respectfully disagree with applicant’s arguments for the following reasons:
The prior art reference Ho (US 2022/0093686 A1) teaches in Figure 4A, C00 and C10 are connected in series. Therefore, the following limitation is met. Also, C10 and C11 are connected together through M4 through nodes N10 and N11 as shown in Fig 4B.
In the semiconductor art connected two devices in series or parallel is very well known in the art and have a connection that is different in parallel or series is not novel over the prior art. Testing components in a circuit will either result the device connected in series or parallel.
Lastly, a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Since the prior art references Ho (US 2022/0093686 A1) and Liu (US 2021/0111341 A1) teaches all the structural limitations of claim 1 than connecting the memory devices in series or parallel does not differentiate claim from the prior art.
The office recommends the applicant to amend the claim to have structural limitations that different the subject matter of claim 1 from the prior art references.
Hence, the rejection of claim 1 under unpatentable over Ho (US 2022/0093686 A1) in view of Liu (US 2021/0111341 A1) is deemed proper and maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mounir S Amer whose telephone number is (571)270-3683. The examiner can normally be reached Monday-Friday 9:00-5:30.
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/Mounir S Amer/ Primary Examiner, Art Unit 2818
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