DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Applicant
This Office Action is in response to Applicant’s reply filed on 05 August 2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 9 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ke et al. (U.S. Pub. 2021/0350834).
Claim 1: Ke et al. discloses a semiconductor device, in Figs. 1, 10A and 10B, comprising:
a substrate (102; paragraph 38) having active patterns (105; paragraph 38) disposed thereon, each of the active patterns (105) including a central portion (portions of 105 in which 132 overlaps) and edge portions (left and right portions of 105) apart from each other with the central portion (portions of 105 in which 132 overlaps) interposed therebetween;
bit lines (132; paragraph 37) extending in a first direction (horizontal direction in Fig. 1) on the central portions (portions of 105 in which 132 overlaps) of the active patterns (105);
word lines (106 and 110; paragraph 37) intersecting the active patterns (105) in a second direction (vertical direction in Fig. 1) intersecting the first direction (horizontal direction in Fig. 1);
fence patterns (164; paragraph 30) disposed between the bit lines (132) adjacent to each other on the word lines (106 and 110);
a contact trench region (region of 115; paragraph 40) intersecting the active patterns (105) and the word lines (106 and 110) in a third direction (third direction; paragraph 40) intersecting the first and second directions; and
bit line contacts (122; paragraph 39) and filling insulation patterns (154; paragraph 29) alternately arranged in the third direction (third direction) in the contact trench region (region of 115),
wherein the first to third directions (horizontal direction in Fig. 1, vertical direction in Fig. 1, third direction, respectively) are parallel to a bottom surface (bottom surface of 102) of the substrate (102), and
wherein the filling insulation patterns (154) are disposed between the word lines (106 and 110) and the fence patterns (164), respectively,
wherein the active patterns (105) include a first active pattern (first active pattern) and a second active pattern (second active pattern),
wherein the central portion of the first active pattern (central portion of the first active pattern) and an edge portion of the second active pattern (edge portion of the second active pattern) are adjacent to each other in the second direction (vertical direction in Fig. 1), and
wherein a filling insulation pattern (154) between the edge portion of the second active pattern (edge portion of the second active pattern) and a bit line contact (bit line contact) on the central portion of the first active pattern (central portion of the first active pattern) is spaced apart from the edge portion of the second active pattern (edge portion of the second active pattern).
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Claim 2: Ke et al. discloses the semiconductor device as claimed in claim 1, and in the annotated Fig. 1 below, further discloses
wherein the central portions (portions of 105 in which 132 overlaps) of the active patterns (105) include the central portions arranged in a line (line) along the third direction (third direction), and
wherein the contact trench region (region of 115) extends on the central portions (portions of 105 in which 132 overlaps) arranged in the line (line).
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Claim 9: Ke et al. discloses the semiconductor device as claimed in claim 1, and in Fig. 10B, discloses further comprising:
separation patterns (162; paragraph 31) disposed between the bit line contacts (122) and the word lines (106 and 110).
Claim 11: Ke et al. discloses the semiconductor device as claimed in claim 9, and in paragraph 31, further discloses wherein the separation patterns (31) include silicon nitride.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ke et al. as applied to claims 1 and 2 above, and further in view of Yang et al. (U.S. Pub. 2022/0223599).
Claim 3: Ke et al. discloses the semiconductor device as claimed in claim 2, and in Figs. 1, 10A and 10B, further discloses
wherein each of the bit line contacts (122) covers a portion of each of top surfaces of the central portions (portions of 105 in which 132 overlaps) arranged in the line (line).
Ke et al. appears not to explicitly disclose wherein the filling insulation patterns cover other portions of each of the top surfaces of the central portions arranged in the line.
Yang et al., however, in Figs. 7A and 8 and in paragraph 9, discloses the filling insulation patterns (136) cover other portions (surface of 102A overlapped by 136) of each of the top surfaces (top surfaces of 102A overlapped by 134 and 136) of the central portions (portions of 102A overlapped by 134 and 136) arranged in the line (line in D3 arranged along central portions).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Ke et al. with the disclosure of Yang et al to have made the filling insulation patterns cover other portions of each of the top surfaces of the central portions arranged in the line in order to protect the surrounding elements.
Claim 4: Ke et al. in view of Yang et al. discloses the semiconductor device as claimed in claim 3.
Ke et al. in view of Yang et al., as applied to claim 3, appears not to explicitly disclose wherein the top surfaces of the central portions arranged in the line are completely covered by the bit line contacts and the filling insulation patterns.
Yang et al., however, in Figs. 7A and 8 and in paragraph 9, further discloses the top surfaces (top surfaces of 102A overlapped by 134 and 136) of the central portions (portions of 102A overlapped by 134 and 136) arranged in the line (line in D3 arranged along central portions) are completely covered by the bit line contacts (134) and the filling insulation patterns (136).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Ke et al. in view of Yang et al., as applied to claim 3, with the further disclosure of Yang et al to have made the top surfaces of the central portions arranged in the line are completely covered by the bit line contacts and the filling insulation patterns in order to provide adequate electrical connection (paragraph 35).
Claim 5: Ke et al. discloses the semiconductor device as claimed in claim 1.
Ke et al. appears not to explicitly disclose wherein each of the filling insulation patterns intersects a corresponding one of the word lines in the third direction.
Yang et al., however, in Figs. 8 and 9B and in paragraph 9, discloses each of the filling insulation patterns (136) intersects a corresponding one of the word lines (106) in the third direction (D3).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Ke et al. with the disclosure of Yang et al to have made each of the filling insulation patterns intersects a corresponding one of the word lines in the third direction in order to protect the surrounding elements.
Claim 6: Ke et al. discloses the semiconductor device as claimed in claim 1.
Ke et al. appears not to explicitly disclose wherein each of the filling insulation patterns includes a first side being in contact with a corresponding bit line contact of the bit line contacts, a second side opposite to the first side, a third side extending from the first side to the second side, and a fourth side opposite to the third side.
Yang et al., however, in annotated Fig. 8 below, discloses each of the filling insulation patterns (136) includes a first side (first side) being in contact with a corresponding bit line contact (136) of the bit line contacts (136), a second side (second side) opposite to the first side, a third side (third side) extending from the first side to the second side, and a fourth side (fourth side) opposite to the third side.
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It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Ke et al. with the disclosure of Yang et al to have made each of the filling insulation patterns includes a first side being in contact with a corresponding bit line contact of the bit line contacts, a second side opposite to the first side, a third side extending from the first side to the second side, and a fourth side opposite to the third side in order to protect the surrounding elements.
Claim 7: Ke et al. in view of Yang et al. discloses the semiconductor device as claimed in claim 6, and Ke et al., in Fig. 1, further discloses wherein each of the bit line contacts (122) includes a side (left side) extending in the third direction (third direction).
Ke et al. in view of Yang et al., as applied to claim 6, appears not to explicitly disclose wherein the sides of the bit line contacts are aligned with the third sides of the filling insulation patterns.
Yang et al., however, in Fig. 8, discloses the sides (upper sides of 134) of the bit line contacts (134) are aligned with the third sides (third sides) of the filling insulation patterns (136).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Ke et al. in view of Yang et al., as applied to claim 6, with the further disclosure of Yang et al to have made the sides of the bit line contacts are aligned with the third sides of the filling insulation patterns in order to protect the surrounding elements.
Claim 8: Ke et al. discloses the semiconductor device as claimed in claim 1, and in Figs. 1 and 10B and in paragraph 37, further discloses wherein each of the word lines (106 and 110) comprises: a gate electrode (110) extending in the second direction (vertical direction in Fig. 1); and a gate capping (106) pattern on the gate electrode (110).
Ke et al., appears not to explicitly disclose wherein each of the filling insulation patterns is in contact with the gate capping pattern.
Yang et al., however, in Fig. 7B and in paragraph 16, further discloses each of the filling insulation patterns (136) is in contact with the gate capping pattern (108).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Ke et al. with the disclosure of Yang et al to have each of the filling insulation patterns is in contact with the gate capping pattern in order to protect the surrounding elements.
Claim(s) 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ke et al. (U.S. Pub. 2021/0350834) in view of Yang et al. (U.S. Pub. 2022/0223599).
Claim 13: Ke et al. discloses a semiconductor device, in Figs. 1, 10A and 10B, comprising:
a first active pattern (105, first active pattern in annotated Fig. 1 below; paragraph 38) and a second active pattern (105, second active pattern in annotated Fig. 1 below) disposed on a substrate (102; paragraph 38), each of the first and second active patterns including a central portion (portion of 105 in which 132 overlaps) and edge portions (left and right portion of 105) spaced apart from each other with the central portion (portion of 105 in which 132 overlaps) interposed therebetween;
a bit line (132; paragraph 37) extending in a first direction (horizontal direction in Fig. 1) on the central portion (portions of 105 in which 132 overlaps) of the first active pattern (105);
a pair of word lines (110 on either side of the central portion; paragraph 37) intersecting the first active pattern (105) in a second direction (vertical direction in Fig. 1) intersecting the first direction (horizontal direction in Fig. 1) with the central portion (portions of 105 in which 132 overlaps) of the first active pattern (105) interposed therebetween;
a contact trench region (region of 115; paragraph 40) intersecting the first active pattern (105) and the word lines (110) in a third direction (third direction; paragraph 40) intersecting the first and second directions;
a bit line contact (122; paragraph 39) disposed between the central portion (portions of 105 in which 132 overlaps) of the first active pattern (105) and the bit line (132) in the contact trench region (region of 115); and
a pair of filling insulation patterns (154; paragraph 29) disposed on the pair of word lines (110 on either side of the central portion), respectively, in the contact trench region (region of 115),
wherein the first to third directions (horizontal direction in Fig. 1, vertical direction in Fig. 1, third direction, respectively) are parallel to a bottom surface (bottom surface of 102) of the substrate (102), and
wherein the bit line contact (122) covers a portion of a top surface (top surface of portions of 105 in which 132 overlaps) of the central portion (portions of 105 in which 132 overlaps) of the first active pattern (105),
wherein the central portion (portion of 105 in which 132 overlaps) of the first active pattern (105) and an edge portion of the second active pattern (edge portion of the second active pattern) are adjacent to each other in the second direction (vertical direction in Fig. 1), and
wherein one of the pair of filling insulation patterns (154) disposed between the edge portion of the second active pattern (edge portion of the second active pattern) and the bit line contact (122) is spaced apart from the edge portion of the second active pattern (edge portion of the second active pattern).
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Ke et al. appears not to explicitly disclose wherein the pair of filling insulation patterns covers other portions of the top surface of the central portion of the active pattern.
Yang et al., however, in Fig. 7A and paragraph 9, discloses the pair of filling insulation patterns (136) covers other portions (surface of 102A overlapped by 136) of the top surface (top surfaces of 102A overlapped by 134 and 136) of the central portion (portions of 102A overlapped by 134 and 136) of the active pattern (102A).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Ke et al. with the disclosure of Yang et al to have made the pair of filling insulation patterns covers other portions of the top surface of the central portion of the active pattern in order to protect the surrounding elements.
Claim 14: Ke et al. in view of Yang et al. discloses the semiconductor device as claimed in claim 13, and Ke et al., in Figs. 1, 10A and 10B, further discloses wherein the bit line contact (122) and the pair of filling insulation patterns (154) do not cover the edge portions (left and right portions) of the first active pattern (105).
Claim 15: Ke et al. in view of Yang et al. discloses the semiconductor device as claimed in claim 13.
Ke et al. in view of Yang et al., as applied to claim 13, appears not to explicitly disclose wherein the top surface of the central portion of the first active pattern is completely covered by the bit line contact and the pair of filling insulation patterns.
Yang et al., however, in Fig. 7A and in paragraph 9, further discloses the top surface (top surface of 102A overlapped by 134 and 136) of the central portion (portion of 102A overlapped by 134 and 136) of the first active pattern (102A) is completely covered the bit line contact (134) and the filling insulation pattern (136).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Ke et al. in view of Yang et al., as applied to claim 13, with the further disclosure of Yang et al to have made the top surface of the central portion of the first active pattern is completely covered by the bit line contact and the pair of filling insulation patterns in order to provide adequate electrical connection (paragraph 35).
Claim 16: Ke et al. in view of Yang et al. discloses the semiconductor device as claimed in claim 13, and Ke et al., in Fig. 10B, discloses further comprising:
separation patterns (162; paragraph 31) disposed between the bit line contact (122) and the pair of word lines (110).
Claim 17: Ke et al. in view of Yang et al. discloses the semiconductor device as claimed in claim 13, and Ke et al., in Figs. 1, 10A and 10B, further discloses
wherein a bottom surface (bottom surface of 154) of each of the pair of filling insulation patterns (154) is located at a lower height than a top surface (top surface of left and right portion of 105) of each of the edge portions (left and right portion) of the second active pattern (105).
Claim 18: Ke et al. in view of Yang et al. discloses the semiconductor device as claimed in claim 13, and Ke et al., in annotated Fig. 1 below, further discloses comprising:
a third active pattern (105, third active pattern in annotated Fig. 1 below) spaced apart from the first active pattern (first active pattern) in the third direction,
wherein the central portion (portions of 105 in which 132 overlaps) of the first active pattern (first active pattern) and a central portion (portions of 105 in which 132 overlaps) of the third active pattern (third active pattern) are arranged in a line (line) along the third direction (third direction), and
wherein the contact trench region (region of 115) extends on the central portions (portions of 105 in which 132 overlaps) of the first and third active patterns (first and third active patterns) arranged in the line (line).
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Claim 19: Ke et al. discloses a semiconductor device, in Figs. 1, 10A and 10B, comprising:
active patterns (105; paragraph 38) disposed on a substrate (102; paragraph 105), each active pattern including a central portion (portion of 105 in which 132 overlaps) and edge portions (left and right portion of 105) spaced apart from each other with the central portion (portion of 105 in which 132 overlaps) interposed therebetween, respectively;
bit lines (132; paragraph 37) extending in a first direction (horizontal direction in Fig. 1) on the central portions (portions of 105 in which 132 overlaps) of the active patterns (105), respectively;
word lines (110; paragraph 37) intersecting the active patterns (105) in a second direction (vertical direction in Fig. 1) intersecting the first direction (horizontal direction in Fig. 1);
contact trench regions (region of 115; paragraph 40) intersecting the active patterns (105) and the word lines (110) in a third direction (third direction; paragraph 40) intersecting the first and second directions; and
bit line contacts (122; paragraph 39) and filling insulation patterns (154; paragraph 29) alternately arranged in the third direction (third direction) in each of the contact trench regions (regions of 115),
wherein the first to third directions (horizontal direction in Fig. 1, vertical direction in Fig. 1, third direction, respectively) are parallel to a bottom surface (bottom surface of 102) of the substrate (102),
wherein the active patterns (105) include a first active pattern (first active pattern) and a second active pattern (second active pattern),
wherein the central portion of the first active pattern (central portion of the first active pattern) and an edge portion of the second active pattern (edge portion of the second active pattern) are adjacent to each other in the second direction (vertical direction in Fig. 1), and
wherein a filling insulation pattern (154) between the edge portion of the second active pattern (edge portion of the second active pattern) and a bit line contact (bit line contact) on the central portion of the first active pattern (central portion of the first active pattern) is spaced apart from the edge portion of the second active pattern (edge portion of the second active pattern).
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Ke et al. appears not to explicitly disclose wherein each of the filling insulation patterns intersects a corresponding one of the word lines in the third direction.
Yang et al, however, in Figs. 8 and 9B and in paragraph 9, discloses each of the filling insulation patterns (136) intersects a corresponding one of the word lines (106) in the third direction (D3).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Ke et al. with the disclosure of Yang et al to have made each of the filling insulation patterns intersects a corresponding one of the word lines in the third direction in order to protect the surrounding elements.
Claim 20: Ke et al. in view of Yang et al. discloses the semiconductor device as claimed in claim 19.
Ke et al. in view of Yang et al, as applied to claim 19, appears not explicitly disclose wherein each of the filling insulation patterns has a parallelogram shape.
Yang et al., however, in Fig. 8, further discloses each of the filling insulation patterns (136) has a parallelogram shape.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Ke et al. in view of Yang et al., as applied to claim 19, with the further disclosure of Yang et al to have made each of the filling insulation patterns has a parallelogram shape in order to protect the surrounding elements.
Allowable Subject Matter
Claims 10 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record, either singularly or in combination, does not suggest, in combination with the other claim limitations, poly-silicon patterns extending in the first direction between the bit lines and the word lines, wherein the separation patterns are disposed between the bit line contacts and the poly-silicon patterns, as required by claim 10.
The prior art of record, either singularly or in combination, does not suggest, in combination with the other claim limitations, a width of each of the filling insulation patterns in the first direction is equal to or greater than a width of each of the bit line contacts in the first direction, as required by claim 12.
Response to Arguments
Applicant's arguments filed 05 August 2026 have been fully considered but they are not persuasive.
Applicant contends the applied prior art fails to teach or suggest wherein the central portion of the first active pattern and an edge portion of the second active pattern are adjacent to each other in the second direction, and
wherein a filling insulation pattern between the edge portion of the second active pattern and a bit line contact on the central portion of the first active pattern is spaced apart from the edge portion of the second active pattern, as required by claims 1 and 19; and wherein the central portion of the first active pattern and an edge portion of the second active pattern are adjacent to each other in the second direction, and
wherein one of the pair of filling insulation patterns between the edge portion of the second active pattern and a bit line contact on the central portion of the first active pattern is spaced apart from the edge portion of the second active pattern,” as required by claim 13.
Examiner notes Ke et al. discloses wherein the central portion of the first active pattern (central portion of the first active pattern) and an edge portion of the second active pattern (edge portion of the second active pattern) are adjacent to each other in the second direction (vertical direction in Fig. 1), and
wherein a filling insulation pattern (154) between the edge portion of the second active pattern (edge portion of the second active pattern) and a bit line contact (bit line contact) on the central portion of the first active pattern (central portion of the first active pattern) is spaced apart from the edge portion of the second active pattern (edge portion of the second active pattern) (see annotated Figs. 1 and 10A above).
Ke et al. also discloses wherein the central portion (portion of 105 in which 132 overlaps) of the first active pattern (105) and an edge portion of the second active pattern (edge portion of the second active pattern) are adjacent to each other in the second direction (vertical direction in Fig. 1), and
wherein one of the pair of filling insulation patterns (154) disposed between the edge portion of the second active pattern (edge portion of the second active pattern) and the bit line contact (122) is spaced apart from the edge portion of the second active pattern (edge portion of the second active pattern) (see annotated Figs. 1 and 10A above).
Applicant contends the filling insulation pattern (136) of Yang et al. only provides a single spacer within a single trench region or contact hole, while the present disclosure has a plurality of filling insulation patterns 250 in a single contact trench region CTR.
Examiner notes that Yang et al. is relied upon for the filling insulation patterns covering other portions of each of the top surfaces of the central portions arranged in the line, not for a plurality of filling insulation patterns within a single contact trench region.
Applicant contends a person of ordinary skill in the art would have no motivation to combine the technical feature of Yang et al. that utilizes a “contact hole” with Ke et al., which forms filling insulation patterns 152, 154 and a bit line contact 122 within a “bit line contact trench 115.”
Examiner notes that the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference, rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Since Yang et al. discloses the filling insulation patterns (136) cover other portions (surface of 102A overlapped by 136) of each of the top surfaces (top surfaces of 102A overlapped by 134 and 136) of the central portions (portions of 102A overlapped by 134 and 136) arranged in the line (line in D3 arranged along central portions), one of ordinary skill in the art before the time of effective filing of the invention to modify Ke et al. with the disclosure of Yang et al to have made the filling insulation patterns cover other portions of each of the top surfaces of the central portions arranged in the line in order to protect the surrounding elements.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN LIN whose telephone number is (571)270-1274. The examiner can normally be reached Monday-Friday 10am-6pm EST.
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/J.L/ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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