DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 13, 2026 has been entered.
Response to Amendment
Applicant's arguments with respect to claims 1, 3 – 21 and 29 – 32 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 and 29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In regards to claim 1, on lines 10 – 12), and as similarly recited in claim 29, the feature “wherein an upper surface of the first solder resist layer facing away from the insulation layer is positioned at a level equal to, or closer to the insulation layer than, an upper surface of the conductive layer facing away from the first connection pad” is unclear and appears to be an impossibility. It is not clear as to how the upper surface of the solder resist layer can be positioned at a level equal to the insulation layer. If the upper surface of the solder resist layer is positioned at a level equal to the surface of the insulation layer, or is coplanar with the surface of the insulation layer, then the solder resist layer would have zero (“0”) thickness, and would not exist. None of the figures of the instant application show this feature of the upper surface of the solder resist layer being positioned at a level equal to the insulation layer. Examiner suggests removing the limitation “is positioned at a level equal to, or” such that the feature may read “wherein an upper surface of the first solder resist layer facing away from the insulation layer is closer to the insulation layer than, an upper surface of the conductive layer facing away from the first connection pad.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 – 21, and 29 - 32 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (U.S. Patent Publication No. 2008/0314633) in view of Ogawa et al. (U.S. Patent Publication No. 2022/0084930).
Regarding claim 1, in Figure 4A, Kang discloses a printed circuit board, comprising: an insulation layer (2) having a first surface (bottom surface of layer 2) and a second surface (top surface of layer 2) which are opposite to each other; a first connection pad (8) which is embedded in the insulation layer and has a surface recessed from the first surface of the insulation layer; a conductive layer (comprising layers 10, 20) which is located on the first connection pad and has a part embedded in the insulation layer and another part protruding from the first surface of the insulation layer; and a first solder resist layer (12) located on the first surface of the insulation layer, wherein an upper surface of the first solder resist layer facing away from the insulating layer is positioned at a level equal to, or closer to the insulation layer than, an upper surface of the conductive layer facing away from the first connection pad (solder resist layer 12 has an upper surface that is closer to the upper surface of layer 2 than the top surface of layers 10, 20; Figure 4A), wherein the conductive layer further includes a nickel conductive layer (20, paragraph [0060]) located on the first connection pad and a gold (Au) conductive layer (10) located on the nickel conductive layer (layer 10 is on the bottom surface of layer 20) and wherein the nickel conductive layer is in direct contract with the first solder resist layer (Figure 4A). Kang does not specifically disclose bump/via conductor 10 being formed of gold. However, in Figure 5, Ogawa discloses via conductors 41, 42 being formed of gold (paragraph [0028]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the bump/via conductor 10 of Kang to be formed of gold as taught by Ogawa in that forming via conductors of a metal having good electrical conductivity, such as gold, within a printed circuit board is common place and well known in the art, and is merely a design option for a skilled artisan without the exercise of inventive skill.
Regarding claim 3, Kang discloses wherein the conductive layer protrudes from the surface of the first solder resist layer, and a thickness of a part of the conductive layer that protrudes from the surface of the first solder resist layer is larger than a thickness of the first solder resist layer (Figure 4A).
Regarding claim 4, Kang discloses wherein the nickel conductive layer is in contact with the first connection pad at a height lower than the first surface of the insulation layer (Figure 4A).
Regarding claim 5, Kang discloses wherein a thickness of the nickel conductive layer is larger than a thickness of the first solder resist layer (Figure 4A).
Regarding claim 6, Kang discloses wherein the nickel conductive layer protrudes from the surface of the first solder resist layer (Figure 4A).
Regarding claim 7, Kang discloses wherein a width of the conductive layer is equal to a width of the first connection pad in a portion where the conductive layer is in contact with the first connection pad (Figure 4A).
Regarding claim 8, Kang discloses wherein a width of a part of the conductive layer embedded in the first solder resist layer and a width of a part of the conductive layer protruding from the first solder resist layer are equal to each other (Figure 4A).
Regarding claim 9, Kang discloses wherein a width of the gold conductive layer is equal to a width of the nickel conductive layer (Figure 4A).
Regarding claim 10, Kang discloses wherein the conductive layer further includes a palladium (Pd) conductive layer disposed between the nickel conductive layer and the gold conductive layer, and includes another palladium (Pd) conductive layer disposed between the nickel conductive layer and the first connection pad (Figure 4A).
Regarding claim 11, Kang discloses wherein a width of the part of the conductive layer embedded in the insulation layer is smaller than a width of the part of the conductive layer protruding from the first surface of the insulation layer (Figure 4A).
Regarding claim 12, Kang discloses wherein a width of the part of the conductive layer protruding from the first surface of the insulation layer increases from both side surfaces of the part of the conductive layer embedded in the insulation layer (Figure 4A).
Regarding claim 13, Kang discloses wherein a width of the part of the conductive layer protruding from the first surface of the insulation layer increases from one side surface of the part of the conductive layer embedded in the insulation layer, and another side surface opposing the one side surface of the part of the conductive layer embedded in the insulation layer is coplanar with a side surface of the part of the conductive layer protruding from the first surface of the insulation layer (Figure 4A).
Regarding claim 14, Kang discloses wherein the insulation layer includes a groove adjacent to a side surface of the part of the conductive layer embedded in the insulation layer, and a portion of the first solder resist layer fills a space of the groove (Figure 4A).
Regarding claim 15, Kang discloses wherein the insulation layer includes a pair of grooves adjacent to both side surfaces of the part of the conductive layer embedded in the insulation layer, and portions of the first solder resist layer fill spaces of the pair of grooves (Figure 4A).
Regarding claim 16, Kang discloses wherein the conductive layer is formed in plural such that the plurality of conductive layers are disposed on the insulation layer to be adjacent to each other, and a portion of the first solder resist layer is disposed between the plurality of adjacent conductive layers (Figure 4A).
Regarding claim 17, Kang discloses wherein the first connection pad is a bond finger for a wire bonding pad (Figure 4A).
Regarding claim 18, Kang discloses a second connection pad located on the second surface of the insulation layer; and a second solder resist layer which is disposed in the vicinity of the second connection pad on the second surface of the insulation layer (Figure 4A).
Regarding claim 19, Kang discloses wherein the first solder resist layer is thinner than the second solder resist layer (Figure 4A).
Regarding claim 20, Kang discloses wherein the insulation layer includes a plurality of insulation layers and each of the plurality of insulation layers includes a circuit layer (Figure 4A).
Regarding claim 21, Kang discloses a via which is embedded in the insulation layer to be connected to the circuit layer and extends in a thickness direction of the insulation layer (Figure 4A).
Regarding claim 29, in Figure 4A, Kang discloses an insulation layer (2) having a first surface (top surface of layer 2) and a second surface (bottom surface of layer 2) which are opposite to each other; a first solder resist layer (12) disposed on the first surface of the insulation layer; a first connection pad (8) embedded in the insulation layer; and a conductive layer including a nickel (Ni) conductive layer (20, paragraph [0060]) disposed on the first connection pad and a gold (Au) conductive layer (10) disposed on the nickel (Ni) conductive layer (layer 10 is disposed on the bottom surface of layer 20), wherein at least portions of the nickel (Ni) conductive layer and the gold (Au) conductive layer protrude, in a direction away from the insulation layer, from an upper surface of the first solder resist layer (portions of layers 10, 20 protrude from an upper surface of solder resist layer 12, Figure 4A) facing away from the insulating layer, the upper surface of the first solder resist layer being positioned at a level equal to, or closer to the insulation layer than, an upper surface of the conductive layer facing away from the first connection pad (solder resist layer 12 has an upper surface that is closer to the upper surface of layer 2 than the top surface of layers 10, 20; Figure 4A), and wherein the nickel conductive layer is in direct contact with the first solder resist layer (Figure 4A). Kang does not specifically disclose bump/via conductor 10 being formed of gold. However, in Figure 5, Ogawa discloses via conductors 41, 42 being formed of gold (paragraph [0028]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the bump/via conductor 10 of Kang to be formed of gold as taught by Ogawa in that forming via conductors of a metal having good electrical conductivity, such as gold, within a printed circuit board is common place and well known in the art, and is merely a design option for a skilled artisan without the exercise of inventive skill.
Regarding claim 30, Kang discloses wherein an upper surface of the first connection pad is recessed from the first surface of the insulation layer (Figure 4A).
Regarding claim 31, Kang discloses wherein at least a portion of the first solder resist layer is disposed between an inner surface of a recess of the insulation layer and a side surface of the nickel (Ni) conductive layer (Figure 4A).
Regarding claim 32, Kang discloses wherein the nickel (Ni) conductive layer includes a first portion embedded in the insulation layer and a second portion protruding from the first surface of the insulation layer, and a width of the first portion of the nickel (Ni) conductive layer is less than or equal to a width of the second portion of the nickel (Ni) conductive layer, where each width is measured in a direction orthogonal to a stacking direction (Figure 4A).
Allowable Subject Matter
Claims 33 – 38 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847