DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 2, and 6 have been amended.
Claims 12-16 have been added.
Claims 1-16 have been examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 2 recites, “the bandwidth of the at least one memory unit is increased by alternately driving….” “Increased” is a relative term, but the claim does not specify what the increase is relative to. Therefore, the term renders the scope of the claims indefinite. For purposes of examination, this limitation is interpreted as, “ the at least one memory unit is alternately driven….”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 6-8, 11-13, 15, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication No. 2022/0284274 by Jang et al. (hereinafter referred to as “Jang”).
Regarding claim 1, Jang discloses:
a neural processing unit comprising: an artificial intelligence (AI) calculation unit configured to process artificial neural network calculation of at least one artificial neural network model (Jang discloses, at Figure 3 and related description, a neural processing device, which discloses a neural processing unit comprising: an artificial intelligence (AI) calculation unit configured to process artificial neural network calculation of at least one artificial neural network model.); and
an internal memory comprising at least one memory unit configured to store data of at least one domain among first to third domain data of the at least one artificial neural network model, wherein the at least one memory unit includes a plurality of sub-memory units configured to perform time-division operation (Jang discloses, at Figures 3-5 and related description, internal memory comprising first and second memories that comprise SRAM banks, i.e., sub-memory units, configured to store data, including input data, weight data, and output data, which discloses first to third domains of data and performing time-division operation.); and
selecting circuitry electrically connected to the Al calculation unit and the plurality of sub-memory units and configured to control read and write operations of the plurality of sub-memory units in a time division manner (Jang discloses, at Figure 3 and related description, controlling which data is read to/from memory using, e.g., bandwidth control module 350 etc. This discloses selecting circuitry controlling read and write operations in a time division manner.).
Regarding claims 2 and 11, taking claim 2 as representative, Jang discloses the elements of claim 1, as discussed above. Jang also discloses:
a bandwidth of the at least one memory unit is based on a number of the plurality of sub-memory units (Jang discloses, at Figure 3 and related description, primary and secondary memories. It is evident that the more SRAM banks are included, the greater the bandwidth.), and
wherein the bandwidth of the at least one memory unit is increased by alternately driving the plurality of sub-memory units (Jang discloses, at ¶ [0065], accessing the memory banks in sequential order, which discloses alternately driving the sub-memory units.).
Regarding claim 6, Jang, as modified, discloses the elements of claim 1, as discussed above. Jang also discloses:
the data of the at least one domain is time-divided and supplied to the plurality of sub-memory units (Jang discloses, at Figure 3 and related description, primary and secondary memories, which discloses the data stored in the plurality of sub-memory units is time-divided and supplied to the corresponding sub-memory units.).
Regarding claim 7, Jang, as modified, discloses the elements of claim 1, as discussed above. Jang also discloses:
the internal memory further comprises: a first domain data selector configured to output data of the first domain stored in a specific memory unit among the plurality of memory units to the AI calculation unit (Jang discloses, at Figure 3 and related description, a multiplexor to retrieve input data.);
a second domain data selector configured to output data of the second domain stored in a specific memory unit among the plurality of memory units to the AI calculation unit (Jang discloses, at Figure 3 and related description, a multiplexor to retrieve weight data.); and
a third domain data selector configured to output data of the third domain output from the AI calculation unit to a specific memory unit among the plurality of memory units (Jang discloses, at Figure 3 and related description, a multiplexor to store output data.).
Regarding claim 8, Jang, as modified, discloses the elements of claim 1, as discussed above. Jang also discloses:
wherein the internal memory includes first to third domain data selectors configured to control input and output of data of the first to third domains (Jang discloses, at Figure 3 and related description, multiplexors to control input, weight, and output data.),
wherein an operation of the first domain data selector is configured to be controlled by a first data control signal (Jang discloses, at Figure 3 and related description, multiplexors to control input, weight, and output data, the multiplexers controlled by respective control signals.),
wherein an operation of the second domain data selector is configured to be controlled by a second data control signal(Jang discloses, at Figure 3 and related description, multiplexors to control input, weight, and output data, the multiplexers controlled by respective control signals.), and
wherein an operation of the third domain data selector is configured to be controlled by a third data control signal (Jang discloses, at Figure 3 and related description, multiplexors to control input, weight, and output data, the multiplexers controlled by respective control signals.).
Regarding claim 12, Jang, as modified, discloses the elements of claim 1, as discussed above. Jang also discloses:
the plurality of sub-memory units includes an odd-numbered sub-memory unit and an even-numbered sub-memory unit (Jang discloses, at Figures 3-5 and related description, internal memory comprising first and second memories, which discloses odd and even numbered.), and
wherein the selecting circuitry is configured, according to a first address control signal, to: input data of at least one of the first and second domains to the odd-numbered sub-memory unit at a first clock timing, and input data of at least one of the first and second domains to the even-numbered sub-memory unit at a second clock timing different from the first clock timing (Jang discloses, at Figures 3-5 and related description, sequentially providing data, e.g., in a round-robin manner, to the banks, which discloses selecting, according to a first address control signal, input to the first and second units at different clock timings.) .
Regarding claim 13, Jang, as modified, discloses the elements of claim 1, as discussed above. Jang also discloses:
the selecting circuitry includes: a first address selector configured to select one of the plurality of sub-memory units and to input data of a first domain or a second domain to the selected sub-memory unit according to a first address control signal (Jang discloses, at Figures 3-5 and related description, fetching input data, which discloses inputting data of a first or second domain to a selected memory bank, which discloses selecting the address of the memory bank.);
a second address selector configured to select one of the plurality of sub-memory units and to input data of a third domain to the selected sub-memory unit according to a second address control signal different from the first address control signal (Jang discloses, at Figures 3-5 and related description, fetching input data, which discloses inputting data of a third domain to a selected memory bank, which discloses selecting the address of the memory bank.);
a first data selector configured to select and output data of at least one of the first and second domains stored in the plurality of sub-memory units according to a first data control signal (Jang discloses, at Figures 3-5 and related description, writing output data, which discloses outputting data of a first or second domain, which discloses according to a data control signal.); and
a second data selector configured to select and output third domain data stored in the plurality of sub-memory units according to a second data control signal different from the first data control signal (Jang discloses, at Figures 3-5 and related description, writing output data, which discloses outputting data of a third domain, which discloses according to a different data control signal.).
Regarding claim 15, Jang discloses:
a neural processing unit comprising: an artificial intelligence (AI) calculation unit configured to process artificial neural network calculation of at least one artificial neural network model (Jang discloses, at Figure 3 and related description, a neural processing device, which discloses a neural processing unit comprising: an artificial intelligence (AI) calculation unit configured to process artificial neural network calculation of at least one artificial neural network model.); and
an internal memory comprising at least one memory unit configured to store data of at least one domain among first to third domain data of the at least one artificial neural network model, wherein the at least one memory unit includes a plurality of sub-memory units configured to perform time-division operation (Jang discloses, at Figures 3-5 and related description, internal memory comprising first and second memories that comprise SRAM banks, i.e., sub-memory units, configured to store data, including input data, weight data, and output data, which discloses first to third domains of data and performing time-division operation.);, and
wherein the data of the at least one domain is time-divided and supplied to the plurality of sub-memory units (Jang discloses, at Figures 3-5 and related description, sequentially providing data, e.g., in a round-robin manner, to the banks.).
Regarding claim 16, Jang, as modified, discloses the elements of claim 15, as discussed above. Jang also discloses:
the internal memory further comprises: a first address selector having a plurality of output units connected to the plurality of sub-memory units and configured to select one of the plurality of sub-memory units and input data of a first domain or a second domain to the selected sub-memory unit according to a first address control signal (Jang discloses, at Figures 3-5 and related description, fetching input data, which discloses inputting data of a first or second domain to a selected memory bank, which discloses selecting the address of the memory bank.); and
a second address selector having a plurality of output units connected to theplurality of sub-memory units and configured to select one of the plurality of sub-memory units and input data of a third domain to the selected sub-memory unit according to a second address control signal (Jang discloses, at Figures 3-5 and related description, fetching input data, which discloses inputting data of a third domain to a selected memory bank, which discloses selecting the address of the memory bank.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of US Publication No. 2021/0278873 by Sajja et al. (hereinafter referred to as “Sajja”).
Regarding claim 3, Jang, as modified, discloses the elements of claim 1, as discussed above. Jang does not explicitly disclose a driving clock frequency of the Al calculation unit is different from a driving clock frequency of the sub-memory units.
However, in the same field of endeavor (e.g., processors) Sajja discloses:
independently selecting clock frequencies for different components (Sajja discloses, at ¶ [0016], independently setting the clock frequencies for different components.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Jang to include using different clock frequencies for different components, as disclosed by Sajja, in order to improve performance. See, e.g., ¶ [0002].
Regarding claim 4, Jang, as modified, discloses the elements of claim 1, as discussed above. Jang does not explicitly disclose a driving clock frequency of the internal memory is greater than or equal to a driving clock frequency of the Al calculation unit.
However, in the same field of endeavor (e.g., processors) Sajja discloses:
independently selecting clock frequencies for different components (Sajja discloses, at ¶ [0016], independently setting the clock frequencies for different components, which discloses a first component having a greater clock frequency than a second component.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Jang to include using different clock frequencies for different components, as disclosed by Sajja, in order to improve performance. See, e.g., ¶ [0002].
Regarding claim 5, Jang, as modified, discloses the elements of claim 1, as discussed above. Jang does not explicitly disclose a driving clock frequency of the AI calculation unit is greater than a driving clock frequency of one sub-memory unit among the plurality of sub-memory units.
However, in the same field of endeavor (e.g., processors) Sajja discloses:
independently selecting clock frequencies for different components (Sajja discloses, at ¶ [0016], independently setting the clock frequencies for different components, which discloses a first component having a slower clock frequency than a second component.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Jang to include using different clock frequencies for different components, as disclosed by Sajja, in order to improve performance. See, e.g., ¶ [0002].
Claims 9, 10, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of US Publication No. 2021/0019600 by Huang et al. (as cited by Applicant and hereinafter referred to as “Huang”).
Regarding claim 9, Jang, as modified, discloses the elements of claim 1, as discussed above. Jang also discloses:
…an address information unit generating address information of a specific sub-memory unit in which data of any one of the first to third domains is to be stored (Jang discloses, at Figure 3 and related description, storing data in memory, which implicitly discloses generating addresses.).
Jang does not explicitly disclose using direct memory access (DMA).
However, in the same field of endeavor (e.g., processors) Huang discloses:
obtaining input data using DMA (Huang discloses, at ¶ [0086], using DMA.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Jang to include using DMA, as disclosed by Huang, in order to improve memory access performance, which is the object of DMA.
Regarding claim 10, Jang, as modified, discloses the elements of claim 1, as discussed above. Jang also discloses:
… provide address information of the plurality of sub-memory units corresponding to each domain for each operation step of the at least one artificial neural network model (Jang discloses, at Figure 3 and related description, storing data in memory, which implicitly discloses providing addresses.).
Jang does not explicitly disclose using direct memory access (DMA).
However, in the same field of endeavor (e.g., processors) Huang discloses:
obtaining input data using DMA (Huang discloses, at ¶ [0086], using DMA.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Jang to include using DMA, as disclosed by Huang, in order to improve memory access performance, which is the object of DMA.
Regarding claim 14, Jang, as modified, discloses the elements of claim 1, as discussed above. Jang also discloses:
…wherein the selecting circuitry is electrically connected to …the plurality of sub-memory units and is configured to provide data of a specific domain stored in the main memory to the plurality of sub-memory units, and provide data of a specific domain stored in the plurality of sub-memory units to the main memory… Jang discloses, at Figures 3-5 and related description, fetching input data and writing output data.
Jang does not explicitly disclose using direct memory access (DMA).
However, in the same field of endeavor (e.g., processors) Huang discloses:
obtaining data using DMA (Huang discloses, at ¶ [0086], using DMA.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Jang to include using DMA, as disclosed by Huang, in order to improve memory access performance, which is the object of DMA.
Response to Arguments
On pages 10-11 of the response filed April 21, 2026 (“response”), the Applicant argues, “Claim 11 as originally filed is an independent method claim. Yet the outstanding Action states, "Regarding claims 2 and 11, taking claim 2 as representative ...." Applicant respectfully submits that such treatment does not actually address claim 11 on its own terms. Notably, claim 2 is a dependent apparatus claim. Claim 11, by contrast, recites a method of operating a neural processing unit, including processing artificial neural network calculation and storing, in an internal memory of the neural processing unit, data of at least one domain among first to third domain data, wherein the internal memory comprises a memory unit including a plurality of sub-memory units configured to perform time-division operation. Applicant does not contend that the Office is forbidden in all instances from discussing multiple claims together. Applicant does contend, however, that where an independent claim is materially different in class and scope, a statement that another claim is "representative" does not by itself satisfy such requirements as 35 U.S.C. §132(a), 37 C.F.R. §1.104(c)(2), and MPEP §§707.07(f) and 707.07(i).Applicant holds that the deficiency is not merely procedural. The cited Jang disclosure concerns bandwidth reconfiguration among memory clients and, in one instance (e.g., claim 12), sequential provision of a select signal to a 4-to-1 multiplexer through a round-robin method. Such round-robin selection is an arbitration or client-selection technique, which is inconsistent with the recited time-division operation of the plurality of sub-memory units within a memory unit. Nor do Jang's own method claims cure the deficiency. Here, Jang (claims 14-19) is directed to calculating a target capacity, determining a target memory, and generating a control signal to reconfigure memory bandwidth - which is a fundamentally different method from that of claim 11. Accordingly, Applicant respectfully requests separate consideration of claim 11 on its own merits and identification of where Jang allegedly discloses each limitation of claim 11, including the recited time-division operation of the plurality of sub-memory units.”
Though fully considered, the Examiner respectfully disagrees. In arguing that claim 2 and claim 11 are not properly grouped, the Applicant argues that claim 11 is fundamentally different from the cited art. However, this is not dispositive in determining whether claim 2 and claim 11 are properly grouped. The issue is whether claim 2 and claim 11 are fundamentally different.
Claim 2, which includes all the limitations of claim 1, is essentially identical to claim 11. The only difference between claim 2 and claim 11 is that claim 2 an apparatus claim and claim 11 is a method claim. However, claim 2 recites an apparatus configured to perform a method, i.e., the method of claim 11. And claim 11 recites a method performed using an apparatus, i.e., the apparatus of claim 2. Therefore, the Examiner maintains that is it proper to consider claim 2 as representative of claims 2 and 11. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 12 of the response the Applicant argues, “Examiner points generally to Jang FIGS. 3-5 and equates Jang's first and second memories and their SRAM banks with the claimed memory unit and sub-memory units. But the cited Jang disclosure is organized around memory clients, bank-arbitration logic, and a bandwidth-control path that reallocates bandwidth among clients associated with input feature maps, weight, and PSUM/OFM data. In other words, Jang is concerned with routing and bandwidth allocation among memory clients, not with the recited within-one-memory-unit architecture now made explicit in claim 1. Nor does the multiplexing behavior of Jang teach the recited time-division operation. In Jang, the round-robin feature concerns sequential provision of a select signal for a 4-to-1 mux when bandwidth of the first memory for one client is limited. This is a client-selection or arbitration technique, which is not equivalent to the recited at least one memory unit #K. Applicant therefore submits that the Office Action overgeneralizes Jang. Generic SRAM banks, bank-arbitration logic, and client-side multiplexers do not disclose the presently claimed structure, namely, one memory unit including the plurality of sub-memory units and the selecting circuitry that carries out read-side and write-side control of those sub-memory units in a time division manner. In other words, Jang fails to disclose the memory-unit-level selector structure of claim 1 as amended, and Jang's round-robin client selection cannot be treated as its equivalent.”
Though fully considered, the Examiner respectfully disagrees. The Applicant argues that Jang is concerned “not with the recited within-one-memory-unit architecture now made explicit in claim 1.” The Examiner submits that it is undeniable that Jang discloses a memory unit. Jang discloses, e.g., at Figure 3, primary and secondary memory, a bandwidth control module, and control logic. These are a memory unit.
The Applicant also argues that Jang does not teach the claimed time-division operation. The Examiner notes that this limitation is extremely broad, reading on all manner of sequential data transfer. Jang explicitly discloses, e.g., at ¶ [0065], sequentially providing data. Jang also discloses, e.g., at ¶ [0084], round robin data access. Both sequential data access and round-robin disclose the claimed time-division operation.
Finally, the Applicant argues that the Examiner overgeneralizes Jang. The Examiner respectfully submits that the claims are overly broad. For example, reading data necessarily involves selecting the data and an determining an address of the data, as well as circuitry to perform these operations. So the Applicant’s addition to the claims of selection circuitry to control read and write operations does not add much. Essentially all memory includes circuitry to control read and write operations. Memory wouldn’t be very useful without such circuitry. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On pages 14-15 of the response the Applicant argues, “claim 6 is directed not merely to the existence of a plurality of sub-memory units, but to a particular treatment of the domain data. The specification explains that data of at least one domain among the first and second domains may be time-divided and supplied to the plurality of sub-memory units; see para. 00293. The specification further explains that data of the third domain may likewise be time-divided and supplied to the plurality of sub-memory units; see para. 00298. Thus, claim 6 is directed to time-divided supply of domain data at the sub-memory-unit level. Examiner does not actually identify where Jang discloses that limitation. With respect to claim 6, the outstanding Action instead points generally to Jang at FIG. 3 and "related description" and states that Jang's primary and secondary memories disclose that "the data stored in the plurality of sub-memory units is time-divided and supplied to the corresponding sub-memory units." Applicant respectfully submits that this is conclusory, as no portion of Jang is identified that discloses these limitations. Jang (0088-0092) describes a memory architecture organized around first and second memories, SRAM banks, bank-arbitration logic, a bandwidth-control path, and memory clients associated with input feature maps, weight data, and PSUM/OFM data. Such disclosure concerns routing and bandwidth allocation among clients and memories. Nor is the deficiency cured by Jang's sequential or round-robin behavior. To the extent Examiner may rely on Jang regarding sequential bank access or round-robin provision of a select signal to a multiplexer, such teachings still concern arbitration or client selection rather than the feature of claim 6 as filed or as amended. In other words, even if Jang may disclose selecting among clients or limiting bandwidth for one client while increasing bandwidth for another, that disclosure fundamentally differs from time-dividing the data of the at least one domain and supplying that data to the plurality of sub-memory units. This distinction is also directly relevant to newly added claim 15, which recites the same time-divided-supply concept in independent form. Examiner's analysis of claim 6 therefore necessarily informs the evaluation of claim 15.”
Though fully considered, the Examiner respectfully disagrees. The Applicant argues that claim 6 is directed “to a particular treatment of the domain data.” The claimed treatment is the data “is time-divided and supplied to the plurality of sub-memory units.” The Examiner maintains that this limitation is extremely broad, reading on essentially every memory write operation in existence. That is, unless all data to be written to memory is written in a single write, the data is time-divided. It is all but inherent that memory is written using a sequence of writes. Again, memory that could only be written once would not be very useful. Hence, time-division, or a sequence of writes, is the standard. Jang explicitly discloses, e.g., at ¶ [0065], sequentially writing to the memory banks. The Examiner maintains that this discloses time-dividing data and supplying it to the plurality of sub-memory units. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
Prosecution Insights