DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The foreign document (REPUBLIC OF KOREA 10-2022-0098124) was not translated into English, thus the priority date (08/05/2022) of the foreign document is not prioritized.
Applicant’s election of Species 1 (claims 1-3, 5-6) in the reply filed on 12/29/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claim 4 recites “a connection terminal between the chip pad of the second semiconductor chip and the redistribution upper surface pad” which belongs to Species 2 (Fig. 2), not elected Species 1 (Fig. 1). Accordingly, claims 1-3 and 5-6 are pending in this application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, and 5-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (U.S 2022/0262783 A1).
As to claim 1, Yu et al. disclose in Fig. 15B a semiconductor package comprising: a redistribution layer (“redistribution structure” 506, Fig. 15B) comprising a plurality of redistribution patterns (see all redistribution patterns in structure/layer 506, Fig. 15B) (Fig. 15B, para. [0134]); a sub-semiconductor package (“HBM device” 100) comprising a sub-semiconductor package substrate (as indicated at 10L, included in 100, in Fig. 12) (Figs. 12 & 15B, para. [0049], [0140]-[0143]) and a first semiconductor chip (as indicated at “memory cube” 50, included in 100, in Fig. 12) that is on the sub-semiconductor package substrate (as indicated at 10L in Fig. 12) (Figs. 12 &15B, para. [0027]-[0029]), wherein the sub-semiconductor package substrate (as indicated at 10L in Fig. 12) is on the redistribution layer (“redistribution structure” 506) and comprises a plurality of first lower surface pads (“conductive connectors” 114) (Figs. 12 & 15B, para. [0056]); and a second semiconductor chip (“processor device” 10P, Fig. 15B) on the redistribution layer (“redistribution structure” 506) and spaced apart from the sub- semiconductor package (“HBM device” 100) in a horizontal direction (Fig. 15B, para. [0121]), wherein the second semiconductor chip (“processor device” 10P, Fig. 15B) comprises a chip pad (comprising “interconnect structure” 14P, “die connectors” 22P and “conductive connectors” 26P) (Fig. 15B, para. [0121]), wherein at least some of the plurality of redistribution patterns (see top redistribution patterns in structure/layer 506, Fig. 15B) of the redistribution layer (“redistribution structure” 506) are in direct contact with and electrically connected to the plurality of first lower surface pads (“conductive connectors” 114) of the sub-semiconductor package (“HBM device” 100), respectively (Fig. 15B, para. [0056], [0070] [0121]-[0122]).
As to claim 2, as applied to claim 1 above, Yu et al. disclose in Fig. 15B all claimed limitations including the limitation: wherein the sub-semiconductor package substrate (as indicated at 10L, included in 100, in Figs. 12, 14) comprises a land grid array (LGA) substrate (Fig. 15B).
As to claim 3, as applied to claim 1 above, Yu et al. disclose in Fig. 15B all claimed limitations including the limitation: wherein the chip pad (comprising “interconnect structure” 14P, “die connectors” 22P and “conductive connectors” 26P) of the second semiconductor chip (“processor device” 10P, Fig. 15B) is in direct contact with and electrically connected to at least some of the plurality of redistribution patterns (see top redistribution patterns in structure/layer 506, Fig. 15B) of the redistribution layer (“redistribution structure” 506) (Fig. 15B, para. [0120]-[0121]).
As to claim 5, as applied to claim 1 above, Yu et al. disclose in Fig. 15B all claimed limitations including the limitation: wherein a thickness of the sub- semiconductor package (100) in a vertical direction is substantially the same as a thickness of the second semiconductor chip (10P) in the vertical direction (Fig. 15B).
As to claim 6, as applied to claim 1 above, Yu et al. disclose in Fig. 15B all claimed limitations including the limitation: wherein the first semiconductor chip (as indicated at “memory cube” 50, included in 100, in Fig. 12) comprises a memory semiconductor chip (Figs. 12, 14, para. [0027]-[0029]), and the second semiconductor chip (“processor device” 10P, Fig. 15B) comprises a logic semiconductor chip (10P is a “processor device” such as CPU which is a logic semiconductor chip, para. [0121]) (Fig. 15B, para. [0121]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: LIAO (U.S 2024/0128196 A1), Yu et al. (U.S 2023/0352367 A1), Wu et al. (U.S 2023/0062146 A1), and Chen et al. (U.S 2022/0328467 A1).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 April 3, 2026
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