DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pagaila et al. (U.S 2012/0056312 A1).
As to claim 1, Pagaila et al. disclose in Fig. 11 a semiconductor package comprising: a redistribution layer (“build-up interconnect structure” 170) comprising a plurality of redistribution patterns (see all patterns in structure/layer 170) (Fig. 11, para. [0060]-[0062]); a sub-semiconductor package (comprising elements 124c, 152 & 124d) comprising a sub-semiconductor package substrate (“semiconductor die” 124c serves as a substrate) and a first semiconductor chip (“semiconductor die” 124d) that is on the sub-semiconductor package substrate (“semiconductor die” 124c) (Fig. 11, para. [0050]), wherein the sub- semiconductor package substrate (“semiconductor die” 124) is on the redistribution layer (“build-up interconnect structure” 170) and comprises a plurality of first lower surface pads (“contact pads” 132) (Fig. 11, para. [0063]-[0065]); and a second semiconductor chip (comprising “semiconductor dies” 124a & 124b) on the redistribution layer (“build-up interconnect structure” 170) and spaced apart from the sub-semiconductor package (comprising elements 124c, 152 & 124d) in a horizontal direction (see Fig. 11, para. [0063]-[0065]), wherein the second semiconductor chip (comprising “semiconductor dies” 124a & 124b) comprises a chip pad (“contact pads” 132) (Fig. 11, para. [0063]-[0065]), wherein at least some of the plurality of redistribution patterns (see the patterns in structure/layer 170) of the redistribution layer (“build-up interconnect structure” 170) are in direct contact with and electrically connected to the plurality of first lower surface pads (“contact pads” 132) of the sub-semiconductor package (comprising elements 124c, 152 & 124d) (see Fig. 11, para. [0058]), wherein the plurality of redistribution patterns (see all patterns in structure/layer 170) comprises a plurality of redistribution line patterns (see “plurality of redistribution line patterns” as annotated in Fig. 11 below) and a plurality of conductive vias (see “plurality of conductive vias” as annotated in Fig. 11 below) passing through a redistribution insulating layer (162) of the redistribution layer (“build-up interconnect structure” 170) (see annotated Fig. 11 below), and wherein at least some of the plurality of conductive vias (see some of “plurality of conductive vias” as annotated in Fig. 11 below) are in direct contact with and electrically connected to the plurality of first lower surface pads (“contact pads” 132) of the sub-semiconductor package (comprising elements 124c, 152 & 124d), respectively (see annotated Fig. 11 below, para. [0058]).
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As to claim 2, as applied to claim 1 above, Pagaila et al. disclose in Fig. 11 all claimed limitations including the limitation: wherein the sub-semiconductor package substrate (“semiconductor die”124c serves as a substrate) comprises a land grid array (LGA) substrate (see Fig. 11).
As to claim 3, as applied to claim 1 above, Pagaila et al. disclose in Fig. 11 all claimed limitations including the limitation: wherein the chip pad (“contact pads” 132) of the second semiconductor chip (comprising “semiconductor dies” 124a & 124b) is in direct contact with and electrically connected to at least some of the plurality of redistribution patterns (see the patterns in structure/layer 170) of the redistribution layer (“build-up interconnect structure” 170) (Fig. 11, para. [0058]).
As to claim 5, as applied to claim 1 above, Pagaila et al. disclose in Fig. 11 all claimed limitations including the limitation: wherein a thickness of the sub- semiconductor package (comprising elements 124c, 152 & 124d) in a vertical direction is substantially the same as a thickness of the second semiconductor chip (comprising “semiconductor dies” 124a & 124b) in the vertical direction (Fig. 11).
As to claim 6, as applied to claim 1 above, Pagaila et al. disclose in Fig. 11 all claimed limitations including the limitation: wherein the first semiconductor chip (“semiconductor die” 124d) comprises a memory semiconductor chip (chip 124 can be a “memory”, para. [0042]), and the second semiconductor chip (comprising “semiconductor dies” 124a & 124b) comprises a logic semiconductor chip {chip 124 can be also a logic semiconductor chip (“digital signal processor”]), para. [0042]} (Fig. 11, para. [0042]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3 and 5-6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Tsai et al. (U.S 2021/0305226 A1) disclose in Fig. 6 a package comprising: a redistribution layer (122) comprising a plurality of redistribution patterns; a sub-semiconductor package (comprising 112 and 150) comprising a sub-semiconductor package substrate (112) and a first semiconductor chip (150); and a second semiconductor chip (200); wherein a plurality of conductive vias of the redistribution layer (122) are in direct contact with the plurality of first lower surface pads of the sub-semiconductor package (comprising 112 and 150), respectively.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 September 14, 2026
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