DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 10 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Jing et al. (US12014058B2) in view of Lee et al. (US20220083254A1) and in further view of Xu et al. (US20160124873A1).
Regarding claim 1, Figs. 5 and 7 of Jing teach a memory stack comprising:
a first memory IC die 52 (col.7, line 2) comprising memory:
a second memory IC die 51 (annotated Fig.5, col.6, line 67) stacked on the first memory IC die 52,
a controller die 53 (col.7, line 7) stacked below and in contact with the first memory IC die 52.
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Jing does not teach wherein the second memory IC die comprising memory circuitry requiring refresh rates more frequent than that of the first memory IC die.
Fig. 1 of Lee teaches a first die (first memory die 112) which can have a first set of characteristics which include a response time, a refresh rate, a refresh duration; and a second die (second memory die 114). The second die can have a second set of characteristics that correspond to the first set of characteristics. In comparison to the second die, the first die can be configured to provide faster response. Also, in comparison to the first die and/or as a tradeoff for the response speed, the second die can be configured to have higher memory density (e.g., same storage capacity for smaller physical footprint), lower power consumption, less frequent refreshes, etc.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Lee’s first die and second die in the teachings of Jing because they have the first and second sets of characteristics that can be complementary to each other. The first die can be configured to provide faster response than the second die while the second die can be configured to have higher memory density (e.g., same storage capacity for smaller physical footprint), lower power consumption, less frequent refreshes (Lee, [para.0058]).
However, Jing, as modified by Lee does not expressly disclose wherein a processor die stacked below and in contact with the controller die, the processor die includes processor circuitry that communicates with memory circuitries of the first and second memory IC dies throuqh controller circuitry of the controller die.
Fig.2 of Xu teaches a stack-die processing system 200 includes a plurality of dies such as dies 202, 204,206, 208, 210 and 212 and wherein the die 202 implements the processing components of the processor 101 and is thus referred to as processor die 202. The memory controller 102 implements hardwired logic for accessing the memory circuitry of stacked die 206-212 as well as interfacing to the die 202 to service read and write memory access requests.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the processor die stack below and in contact with the memory controller as taught by Xu in order to enable the formation of a vertical stacked die implementation which leads to space efficiency.
Regarding claim 2, Jing further teaches the memory stack of claim 1, wherein the memory circuitry of the first memory IC die 52 (col.7, line 2) is non-volatile memory circuitry.
Regarding claim 3, Jung further teaches the memory stack of claim 2, wherein the non-volatile memory circuitry is ferro-electric random-access memory (FeRAM) or static random-access memory (SRAM) circuitry. It is disclosed in column 5, lines 15-18, wherein the non-volatile memory refers to a rewritable memory, including a flash memory, a ferroelectric random access memory (FeRAM).
Regarding claim 4, Jing further teaches the memory stack of claim 3, wherein the memory circuitry of the second memory IC die 51 (annotated Fig.5, col.6, line 67) is volatile memory circuitry
Regarding claim 5, Jing further teaches the memory stack of claim 4, wherein the volatile memory circuitry is dynamic random-access memory (DRAM) circuitry. It is disclosed in column 5, lines 6-8, wherein volatile memory can include: a dynamic random access memory (DRAM).
Regarding claim 10, Jing further teaches the memory stack of claim 1, further comprising: a third memory IC die (annotated Fig.5) stacked on the second memory IC die 51 (annotated Fig.5, col.6, line 67), the third memory IC die comprising dynamic random-access memory (DRAM) circuitry. It is disclosed in column 5, lines 6-8, wherein volatile memory can include: a dynamic random access memory (DRAM).
Regarding claim 14, the combination of Jing, Lee and Xu teaches the memory stack of claim 1, further
comprising:
a third memory IC die (see annotated Fig.5) stacked on and above the second memory IC die 51 (annotated Fig.5, col.6, line 67), the third memory IC die comprising volatile memory circuitry requirinq refresh rates more frequent than that of the first memory IC die (Fig.1 of Lee teaches wherein the first die (third memory IC die) can be configured to provide faster response than the second die (first memory IC die)); and
a first buffer IC die (see annotated Fig.7) disposed between the second memory IC die (see annotated Fig.7) and the third memory IC die (see annotated Fig.7).
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Regarding claim 15, Jing further teaches the memory stack of claim 14, further comprising:
a fourth memory IC die (see annotated Fig.5) stacked on and above the third memory IC die (see annotated Fig.5), the third memory IC die comprising dynamic random-access memory (DRAM) circuitry; and
a second buffer IC die (see annotated Fig.5) disposed between the third memory IC die and the fourth memory IC die.
Regarding claim 16, Jing further teaches the memory stack of claim 1, further comprising: a first buffer IC die (see annotated Fig.7) disposed between the first memory IC die 52 (annotated fig.7, col.7, line 2) and the second memory IC die (see annotated Fig.7).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Jing et al. (US12014058B2) in view of Lee et al. (US20220083254A1) and Xu et al. (US20160124873A1) and in further view of Smittle et al. (US20220164254A1).
Regarding claim 11, Jing does not teach wherein the third memory IC die has a greater latency than the second memory IC die, and second memory IC die has a greater latency than the first memory IC die.
Smittle discloses, in para.0027, wherein a first memory circuit is at a higher level of memory relative to a second memory circuit which leads to the first memory circuit having a greater latency than the second memory circuit. As the memory level increases, response times are slower, capacity increases, and memory typically becomes less expensive.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Smittle’s first memory circuit, with a greater latency than the second memory circuit, in the teachings of Jing, as modified by Lee and Xu, because as the memory level increases, response times are slower, capacity increases, and memory typically becomes less expensive (Smittle, [para.0024]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Jing et al. (US12014058B2) in view of Lee et al. (US20220083254A1) and Xu et al. (US20160124873A1) and in further view of Malladi et al. (US20190079678A1).
Regarding claim 12, Jing does not teach wherein the memory stack of claim 10 further comprising: first processing in memory (PIM) circuitry disposed in the second memory IC die; and second PIM circuitry disposed in the third memory IC die.
Fig.1 of Malladi teaches HBM+ memory device 105 may be divided into two channels in which there may be 16 banks per channel; wherein one or more of the HBM+ memory devices 105a-105d may also include PIM functionality and regular data storage functionality, such as conventional read and write operations (para.0025).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Malladi’s memory device, with PIM functionality, in the teachings of Jing, as modified by Lee and Xu, because first PIM command provides a deterministic latency for completion and the second PIM command provides a non-deterministic latency for completion (Malladi, [abstract]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891