DETAILED ACTION
This correspondence is in response to the communications received December 23, 2025. Claims 1-9 and 11-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant has made no claim to the benefit of an earlier filing date.
Election/Restrictions
Applicant’s election without traverse of Species II and Sub-Species iv (which are directed to Figs. 10-12), in the reply filed on December 23, 2025 is acknowledged.
Claim Objections
Claim 1 is objected to because of the following informalities: The recitation, “a substrate having a plurality of n-well”, should read as, “a substrate having a plurality of n-wells”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1 and the claims that depend therefrom are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The recitation, “said diffusion regions are separated from each other by one or more non-active regions of the substrate”, lacks sufficient written description to understand what this aspect of the claim intends to set forth. As these “non-active regions” are located between diffusion regions, it is unclear as to what a basic understanding of what these features are (for example, a shallow trench isolation region, or if they are some type of semiconductor material, like for example intrinsic semiconductor). This feature is understood to not be the channel region, which is identified on at least on pg. 8/28, “In a second N-well (220) on the p-type substrate, M2 transistor (260) has active drain and source regions (i.e., P-type doped regions) and a gate region defining a channel interposed between the drain and source regions.”
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Figs. 10-12, a non-volatile memory device comprising:
a substrate having a plurality of n-well (M1 and M2, formed in n-wells, pg. 11/28), said n-well including a plurality of diffusion regions (transistors formed in M1 and M2 will require source and drain regions, however not depicted in the figures), said diffusion regions are separated from each other by one or more non-active regions of the substrate (unclear what “non-active region” means, the disclosure has only two references to this, and those recitations lack any detail. This first limitation after the preamble is understood to mean that the overall device includes a substrate with plural n-wells which have diffusion regions therein, which will be further limited by the subsequent claim limitations. However, this limitation is not a separate aspect from the subsequent limitations.);
a first unit cell (entirety of the device construct shown in Fig. 6 or 7, for example) extending along a longitudinal axis (vertical direction of the page of Fig. 6 or 7), said first unit cell comprising:
a first memory unit (M1. It is noted that each “memory unit” is understood to have at least a support function to the overall memory function of the overall device construction, but not necessarily including memory sites themselves, unless explicitly stated/claimed.) having a first P-MOS transistor formed on disposed on a first n-well on the substrate (transistor in the n-well, where the n-well has been established to be in the substrate);
a second memory unit (M2) having a second P-MOS transistor disposed in a second n-well on the substrate (transistor formed in M2, which is a n-well region),
a third memory unit (M3) having three N-MOS transistors (transistors formed in a p-well) disposed on the substrate and connected in series and arranged parallel to a length of a longitudinal axis of the first unit cell (); and,
at least one connection lines (711) coupling a gate of one of the three N-MOS transistors to gates of the first and second P-MOS transistors (711 connects transistors in M3 to M1 and M2), wherein the three N-MOS transistors in series consist of a first N-MOS transistor sharing a first active region with a second N-MOS transistor, and the second N-MOS transistor sharing a second active region with a third N-MOS transistor (unclear which are which in the drawings, as the drawings are not labeled in a way to understand this. This limitation will be understood by the claim limitation.); and
a second unit cell disposed laterally adjacent to the first unit cell, comprising three memory units including a third P-MOS transistor and a fourth P-MOS transistor, wherein the third and fourth P-MOS transistors are substantially identical to the first and second P-MOS transistors, respectively, and laterally overlap at least a portion of the first and second P-MOS transistors along a direction perpendicular to the longitudinal axis (the second unit cell is laterally oriented to the first unit cell and has similarly oriented plural P-MOS transistors.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 7, 8, 9 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2023/0118978) in view of Mikalo et al. (US 9,087,587).
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Regarding claim 1, the prior art of Park discloses in Figs. 1-3, 5, a non-volatile memory device (¶ 0002, “Various embodiments of the disclosed technology generally relate to a semiconductor memory device, more particularly, to a non-volatile memory device.”) comprising:
a substrate (“substrate 100”, ¶ 0041, “FIG. 1, a unit cell 10 of a semiconductor memory device in accordance example embodiments may include a first doped region NW1 as a first well, a second doped region PW1 as a second well, a third doped region NW2 as a third well and a fourth doped region PW2 as a fourth well, all supported by a semiconductor substrate”, ¶ 0025) having a plurality of n-well[s] (NW1, NW2, ¶ 0025), said n-well including a plurality of diffusion regions (“region 110”, ¶ 0037, “region 120 … region 122”, ¶ 0039, “region 130 … region 140”, ¶ 0041), said diffusion regions (110, 120, 122, 130 and 140) are separated from each other by one or more non-active regions (“isolation layer ISO”, ¶ 0041) of the substrate (shown in cross section view of Figs. 2A-2C);
a first unit cell (“unit cell 10”, ¶ 0041, hereinafter referred to as ‘1UC’) extending along a longitudinal axis (D2), said first unit cell comprising:
a first memory unit (section of 10 in NW1 with cross section A-A’, hereinafter referred to as ‘1MU’) having a first P-MOS transistor (transistor present with FG gate as can be seen in Fig. 2A) formed on disposed on a first n-well (NW1) on the substrate (100);
a second memory unit (section of 10 in NW2 with cross section C-C’, hereinafter referred to as ‘2MU’) having a second P-MOS transistor (transistor present with FG gate as can be seen in Fig. 2C) disposed in a second n-well (NW2) on the substrate (100),
a third memory unit (section of 10 in PW1 with cross section B-B’, hereinafter referred to as ‘3MU’) having transistors (two shown, with each having one of gates represented by FG and SG, see cross sectional view of Fig. 2B) disposed on the substrate (100) and arranged parallel to a length of a longitudinal axis of the first unit cell (the gates FG and SG of the two transistors extend in parallel to D2); and,
at least one connection lines coupling a gate of one of the three N-MOS transistors to gates of the first and second P-MOS transistors (extensions of gate FG of the transistors in 3MU electrically connect to the gates of the transistors in 1MU and 2MU, see Fig. 1 or 3); and
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a second unit cell (16 unit cells are shown in Fig. 5, so selecting one, for instance as the upper left most unit cell, the “second unit cell” could be the immediate unit cell to the right along the D1 direction, hereinafter referred to as ‘2UC’), disposed laterally adjacent to the first unit cell (as described just previously), comprising three memory units including a third P-MOS transistor (transistor with FG in NW1 of 2UC) and a fourth P-MOS transistor (transistor with FG in NW2 of 2UC), wherein the third and fourth P-MOS transistors are substantially identical to the first and second P-MOS transistors (the identified third and fourth P-MOS transistors are a mirror image of the respective transistors in 1UC), respectively. and laterally overlap at least a portion of the first and second P-MOS transistors along a direction perpendicular to the longitudinal axis (the third and fourth P-MOS transistors in 2UC, laterally overlap with the first and second P-MOS transistors in 1UC, in the D1 direction which is perpendicular to the longitudinal axis D2).
Park (already discloses the N-MOS in the third memory unit, just not three MOS devices in the third memory unit) does not disclose,
“a third memory unit having three N-MOS transistors … connected in series,
…
wherein the three N-MOS transistors in series consist of a first N-MOS transistor sharing a first active region with a second N-MOS transistor, and the second N-MOS transistor sharing a second active region with a third N-MOS transistor”. Park discloses only one N-MOS transistor used as the floating gate transistor.
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Mikalo et al. (US 9,087,587) Figs. 1 and 2, a memory unit having three MOS transistors (in section 16, one transistor is formed from dopant regions 126/127 and corresponding floating gate 131, the second transistor is formed from dopant regions 127/128 and corresponding floating gate 131, and the third transistor is formed from dopant regions 128/129 and corresponding floating gate 131) … connected in series (series connection by diffusion region sharing),
…
wherein the three MOS transistors in series consist of a first MOS transistor sharing a first active region with a second MOS transistor, and the second MOS transistor sharing a second active region with a third MOS transistor (series connection by diffusion region sharing).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“a third memory unit having three N-MOS transistors … connected in series,
…
wherein the three N-MOS transistors in series consist of a first N-MOS transistor sharing a first active region with a second N-MOS transistor, and the second N-MOS transistor sharing a second active region with a third N-MOS transistor”, as disclosed by Mikalo in the system of Park, for the purpose of increasing the charge collection capacity to improve data retention for each memory unit cell. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Park et al. disclose the non-volatile memory device according to claim 1, wherein metal layers or polysilicon layers are used for the connection line (since FG connects the memory units 1MU, 2MU and 3MU, and since FG is gate 103, “The first gate conductive layer 103 may include a polysilicon material.”, ¶ 0037).
Regarding claim 7, the prior art of Park et al. disclose the non-volatile memory device according to claim 1, wherein each of the N-MOS and P-MOS transistors of the first unit cell has a gate region that is connected to a polysilicon layer (all transistors in Park’s 10, have gates 103 or 106, that are connected to the FG extension which are polysilicon or are polysilicon themselves, 103 is polysilicon, ¶ 0037, where 106 is the same material as 103, ¶ 0040).
Regarding claim 8, the prior art of Park et al. disclose the non-volatile memory device according to claim 7, wherein one of the N-MOS transistors has a gate region with polysilicon layer connected through a metal line or a polysilicon layer to the gate region of the first P-MOS transistor and the gate region of the second P-MOS transistor (all transistors in Park’s 10, have gates 103 or 106, that are connected to the FG extensions which are polysilicon or are polysilicon themselves, 103 is polysilicon, ¶ 0037, where 106 is the same material as 103, ¶ 0040).
Regarding claim 9, the prior art of Park et al. disclose the non-volatile memory device according to claim 1, wherein the first unit cell (10) has a space between the first memory unit (1MU) and the second memory unit (2MU), which is long enough to accommodate either (1) a memory unit of the second unit cell laterally adjacent to the first unit cell or (2) the third memory unit of the first unit cell (3MU is shown in a space between 1MU and 2MU).
Regarding claim 11, the prior art of Park et al. disclose the non-volatile memory device according to claim 1, and Park discloses in Fig. 5,
wherein a distance between the third and fourth P-MOS transistors in the second unit cell is equal to the distance between the first and second P-MOS transistors in the first unit cell such that common active regions are formed when active regions of the first and second PMOS transistors in the first unit cell, which are adjacent to the second unit cell, are combined with active regions of first and second PMOS transistors in the second unit cell, which are adjacent to the first unit cell (the 2UC is a mirror image of 1UC, so the cells satisfy this limitation).
Regarding claim 12, the prior art of Park et al. disclose the non-volatile memory device according to claim 11, and Park Fig. 5, and the secondary reference combination rejection of claim 1, discloses,
wherein the second unit cell (2UC) includes a third memory unit (the equivalent 3MU in 2UC), which comprises three N-MOS transistors having a similar structure as the first unit cell (the three MOS transistors comprising the floating gate section are combined as well in the 2UC configuration, as they are mirror cells of the 1UC construction rationale provided in the combination rejection of claim 1, are now applied here in the rejection of the same limitation for the second unit cell for claim 12).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the second unit cell includes a third memory unit, which comprises three N-MOS transistors having a similar structure as the first unit cell”, as disclosed by Mikalo in the system of Park, for the purpose of increasing the charge collection capacity to improve data retention for each memory unit cell. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 13, the prior art of Park et al. disclose the non-volatile memory device according to claim 12, and the combination rejections of claims 1 and 12 disclose, wherein the third memory unit (equivalent 3MU in 2UC) in the second unit cell (2UC) has a same size with the third memory unit of the first unit cell (as the 2UC is a mirror of 1UC in Park, the modified 3MU will have the same 3MU configuration for the 2UC portion).
Allowable Subject Matter
Claims 3-6 and 14-20 are (potentially objected to, provided the 112 rejection is overcome) objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art of Park et al. disclose the non-volatile memory device according to claim 1, however Park shows only the schematic connections of the word lines (see Fig. 3), but not the actual word lines in the actual structure disclosed, and so therefore does not show,
“wherein, in the first unit cell, the first P-MOS transistor has source and drain regions connected to a first word line parallel to a width of the first unit cell,
whereas the second P-MOS transistor has source and drain regions connected to a second word line parallel to the width of the first unit cell, and
each of the first and second word lines is either a program word line or a write word line.”
“4. (Currently Amended) The non-volatile memory device according to claim 1, wherein the third memory unit of the first unit cell further comprises (1) a group of first metal lines arranged parallel to the length of the first unit cell and (2) a group of second metal lines arranged parallel to the width of the first unit cell.”
Claims 5 and 6 are objected to due to their dependence upon claim 4.
“5. (Original) The non-volatile memory device according to claim 4, wherein one of the group of first metal lines is connected to an active region at one end of the three transistors in series, while the other is connected to an active region at the opposite end of the three transistors.”
“6. (Original) The non-volatile memory device according to claim 4, wherein the group of second metal lines include three parallel metal lines, which are separated at regular intervals, extending along a width of the first unit cell such that at least a portion of the three N-MOS transistors is positioned between a first and second one of the group of second metal lines, whereas a third unit cell has three N-MOS transistors positioned in an interval between the second and third one of the group of second metal lines.”
Claim 14 and the claims 15-20 which depend on claim 14, are objected to for the reason that they all depend on claim 6, which has been objected for the reason that claim 6 depends from claim 4, which has been objected to.
“14. (Currently Amended) The non-volatile memory device according to The non-volatile memory device according to claim 6, wherein the third memory unit of the first unit cell is combined to a third memory unit of the third unit cell, wherein the third unit cell overlaps at least partially with the second unit cell and a fourth unit cell laterally adjacent to the third unit cell on an opposite side from where the second unit cell is located.”
“15. (Original) The non-volatile memory device according to claim 14, wherein the third unit cell includes three memory units, including first and second memory units that are identical to the first and second memory units of the first unit cell and a third memory unit with a mirrored arrangement of the N-MOS transistors in the first unit cell.”
“16. (Original) The non-volatile memory device according to claim 15, wherein the third unit cell further includes (1) a group of first metal lines arranged parallel to the length of the unit cell with the same structure as the group of first metal lines of the first unit cell and (2) a group of second metal lines arranged parallel to the width of the unit cell with intervals identical to the intervals of the group of second metal lines of the first unit cell.”
“17. (Original) The non-volatile memory device according to claim 15, wherein a distance between the first and second memory units in the third unit cell is equal to the distance between the first and second memory units of the first unit cell.”
“18. (Original) The non-volatile memory device according to claim 14, wherein the fourth unit cell includes first and second memory units identical to the first and second memory units in the second unit cell.”
“19. (Original) The non-volatile memory device according to claim 18, wherein the third memory unit includes (1) a group of first metal lines arranged parallel to the length of the unit cell with the same structure as the group of first metal lines of the second unit cell and (2) a group of second metal lines arranged parallel to the width of the unit cell with intervals identical to the intervals of the group of second metal lines of the second unit cell.”
“20. (Original) The non-volatile memory device according to claim 18, wherein the third memory unit is configured with a mirrored arrangement of the N-MOS transistors in the second unit cell, wherein the third memory unit of the second unit cell is combined to a third memory unit of the fourth unit cell.”
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893