DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/23/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 7, 9 – 11, 13 – 15, 18 – 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over FURUTANI (US 20250254795 A1, “FURUTANI”).
Regarding claim 1, FURUTANI discloses (Fig. 1) a printed circuit board (1), comprising: a first board unit (11) including a first insulating layer (111) having a first via hole (113a), a first wiring layer (112) disposed on or in the first insulating layer, and a first via including a first metal layer disposed on a wall surface of the first via hole, and a second metal layer disposed on the first metal layer, the first and second metal layers together substantially filling the first via hole, wherein the first metal layer is an electroless plating layer and the second metal layer is an electrolytic plating layer; and a second board unit (12) including a second insulating layer (211) having a second via hole (213a), a second wiring layer (212) disposed on or in the second insulating layer, and a second via including a third metal layer (213) substantially filling the second via hole, wherein the third metal layer is an electroless plating layer, wherein the second board unit is disposed on the first board unit, the second wiring layer has a higher wiring density than that of the first wiring layer (See Fig. 1), and the second via has a plating structure different from that of the first via (The second metal layer diameter is smaller than the first metal layer).
FURUTANI (in the embodiment of Fig. 1) is silent on a first via including a first metal layer disposed on a wall surface of the first via hole, and a second metal layer disposed on the first metal layer, the first and second metal layers together substantially filling the first via hole, wherein the first metal layer is an electroless plating layer and the second metal layer is an electrolytic plating layer
However, FURUTANI discloses ( Fig. 2) a first via including a first metal layer disposed on a wall surface of the first via hole, and a second metal layer disposed on the first metal layer, the first and second metal layers together substantially filling the first via hole (See annotated figure below), wherein the first metal layer is an electroless plating layer and the second metal layer is an electrolytic plating layer (See para 37).
PNG
media_image1.png
325
774
media_image1.png
Greyscale
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified FURUTANI (in the embodiment of Fig. 1) to incorporate the teachings of FURUTANI (in the embodiment of Fig. 2) and provide a first via including a first metal layer disposed on a wall surface of the first via hole, and a second metal layer disposed on the first metal layer, the first and second metal layers together substantially filling the first via hole (See annotated figure above), wherein the first metal layer is an electroless plating layer and the second metal layer is an electrolytic plating layer (See para 37). Doing so would provide a better adhesion with the surface of the insulating layer (para [0045] and [0061]).
In accordance to MPEP 2113, the method of forming the device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight. Please note that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product, i.e printed circuit board (plating layer), does not depend on its method of production, i.e. electroless. In re Thorpe, 227 USPQ 964, 966 (Federal Circuit 1985).
Regarding claim 4, FURUTANI discloses the printed circuit board of claim 1, wherein the second metal layer is spaced apart from a wall surface of the first via hole by the first metal layer (See para [0037] and Fig. 2), and FURUTANI further discloses (See Fig. 1) the third metal layer (213) is in direct contact with a wall surface of the second via hole.
Regarding claim 7, FURUTANI discloses the printed circuit board of claim 1, wherein based on a cross section of the printed circuit board, an average width of the second via hole is smaller than an average width of the first via hole, and a depth of the second via hole is smaller than a depth of the first via hole (See annotated figure below).
PNG
media_image2.png
758
1004
media_image2.png
Greyscale
Regarding claim 9, FURUTANI discloses the printed circuit board of claim 1, wherein the first and second insulating layers each include inorganic filler particles, and based on a cross section of the printed circuit board, an average diameter of the inorganic filler particles included in the second insulating layer is smaller than an average diameter of the inorganic filler particles included in the first insulating layer (See Fig. 2 and para [0035]).
Regarding claim 10, FURUTANI discloses the printed circuit board of claim 1, wherein the third metal layer (213) is thinner than the first metal layer (113), and the second wiring layer includes the second metal layer (See para [0037] and Fig. 1, 2).
Regarding claim 11, FURUTANI discloses the printed circuit board of claim 10, wherein the second wiring layer does not include a metal layer other than the second metal layer (Fig. 1)
Regarding claim 13, FURUTANI discloses the printed circuit board of claim 1, wherein the first board unit includes a core insulating layer (101, para [0027]), first and second core wiring layers (102) respectively disposed on upper and lower surfaces of the core insulating layer, a through via layer (103) passing through the core insulating layer and connecting the first and second core wiring layers to each other, a plurality of first build-up insulating layers (111) disposed on the upper surface of the core insulating layer, a plurality of first build-up wiring layers (112) respectively disposed on or in the plurality of first build-up insulating layers, a plurality of first connection via layers (113) each passing through at least one of the plurality of first build- up insulating layers and each connected to at least one of the plurality of first build-up wiring layers, a plurality of second build-up insulating layers (111) disposed on the lower surface of the core insulating layer, a plurality of second build-up wiring layers (112) respectively disposed on or in the plurality of second build-up insulating layers, and a plurality of second connection via layers (113) each passing through at least one of the plurality of second build-up insulating layers and each connected to at least one of the plurality of second build-up wiring layers; the first insulating layer is included in at least one of the plurality of first build-up insulating layers and the plurality of second build-up insulating layers; the first wiring layer is included in at least one of the plurality of first build-up wiring layers and the plurality of second build-up wiring layers; and the first via is included in at least one of the plurality of first connection via layers and the plurality of second connection via layers (See Fig. 1).
Regarding claim 14, FURUTANI discloses the printed circuit board of claim 13, wherein the second board unit includes a plurality of third build-up insulating layers (211), a plurality of third build-up wiring layers (212) respectively disposed on or in the plurality of third build-up insulating layers, and a plurality of third connection via layers (213) each passing through at least one of the plurality of third build-up insulating layers and each connected to at least one of the plurality of third build- up wiring layers; the plurality of third build-up insulating layers include the second insulating layer; the plurality of third build-up wiring layers include the second wiring layer; and the plurality of third connection via layers include the second via (See Fig. 1).
Regarding claim 15, FURUTANI discloses the printed circuit board of claim 14, further comprising: a plurality of first outer pads (12MP) disposed on the second board unit; a first resist layer (12SRA) disposed on the second board unit and having a first opening exposing the plurality of first outer pads; a plurality of second outer pads (112pB) disposed under the first board unit; a second resist layer (11SRB) disposed under the first board unit and having a plurality of second openings each exposing at least a portion of each of the plurality of second outer pads; a first semiconductor chip (E1) disposed on the second board unit and connected to some of the plurality of first outer pads through a plurality of first connection members; a second semiconductor chip (E2) disposed on the second board unit and connected to another some of the plurality of first outer pads through a plurality of second connection members; and a plurality of third connection members disposed under the first board unit and respectively connected to the plurality of second outer pads (See Fig. 1).
Regarding claim 18, FURUTANI discloses (Fig. 1) a printed circuit board (1), comprising: a first insulating layer (111) having a first via hole (113a); a first wiring layer (112) disposed on or in the first insulating layer; a first via (113) disposed in the first via hole to connect to the first wiring layer, the first via comprising a first metal layer and a second metal layer each disposed within the first via hole; a second insulating layer (211) having a second via hole (213a); a second wiring layer (212) disposed on or in the second insulating layer; and a second via disposed in the second via hole to connect to the second wiring layer, the second via comprising a third metal layer (213) disposed within the second via hole, wherein the second insulating layer is thinner than the first insulating layer (See Fig. 1), and the number of metal layers constituting the first via is greater than the number of metal layers constituting the second via (See Fig. 1).
FURUTANI (in the embodiment of Fig. 1) is silent on the first via comprising a first metal layer and a second metal layer each disposed within the first via hole, and the number of metal layers constituting the first via is greater than the number of metal layers constituting the second via
However, FURUTANI discloses ( Fig. 2) the first via comprising a first metal layer and a second metal layer each disposed within the first via hole (See annotated figure below)
PNG
media_image1.png
325
774
media_image1.png
Greyscale
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified FURUTANI (in the embodiment of Fig. 1) to incorporate the teachings of FURUTANI (in the embodiment of Fig. 2) and provide the first via comprising a first metal layer and a second metal layer each disposed within the first via hole (See annotated figure above). Doing so would provide a better adhesion with the surface of the insulating layer (para [0045] and [0061]).
Incorporating the teachings of FURUTANI (in the embodiment of Fig. 2) into FURUTANI (in the embodiment of Fig. 1) would provide the number of metal layers constituting the first via is greater than the number of metal layers constituting the second via
Regarding claim 19, FURUTANI discloses the printed circuit board of claim 18, wherein based on a cross section of the printed circuit board, an average width of the second via hole is smaller than an average width of the first via hole (See Fig. 1).
Regarding claim 20, FURUTANI discloses the printed circuit board of claim 18, wherein the first and second insulating layers each include inorganic filler particles, and based on a cross section of the printed circuit board, an average diameter of the inorganic filler particles included in the second insulating layer is smaller than an average diameter of the inorganic filler particles included in the first insulating layer (See para [0059] and Fig. 2).
Regarding claim 21, FURUTANI discloses the printed circuit board of claim 18, further comprising: a core insulating layer (101) thicker than the first insulating layer (111) and the second insulating layer (211); and first and second core wiring layers (102) respectively disposed on upper and lower surfaces of the core insulating layer, wherein the first insulating layer is disposed between the core insulating layer and the second insulating layer (See Fig. 1).
Regarding claim 22, FURUTANI discloses the printed circuit board of claim 18, further comprising: an outer pad (12MP) disposed on the second insulating layer and connected to the second via; a resist layer (12SRA) disposed on the second insulating layer and having an opening exposing the outer pad; and a semiconductor chip (E1, E2) disposed on the second insulating layer and connected to the outer pad through a connection member (BL).
Regarding claim 23, FURUTANI discloses the printed circuit board of claim 18, wherein the first via and the second via are tapered in a same direction (See Fig. 1).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over FURUTANI (US 20250254795 A1, “FURUTANI”) in view of Zierath et al. (US 20200013673 A1, “Zierath”)
Regarding claim 2, FURUTANI discloses the printed circuit board of claim 1, wherein based on a cross section of the printed circuit board,
FURUTANI is silent on an average size of grains of a metal included in the second metal layer is smaller than an average size of grains of a metal included in the first metal layer.
However, Zierath discloses (Fig. 26) an average size of grains of a metal included in the second metal layer (198) is smaller than an average size of grains of a metal included in the first metal layer (136) (see Fig. 26).
FURUTANI and Zierath are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified FURUTANI to incorporate the teachings of Zierath and provide an average size of grains of a metal included in the second metal layer (198) is smaller than an average size of grains of a metal included in the first metal layer (136) (see Fig. 26). Doing so would enhance manufacturing reliability and controlled electrical properties
Allowable Subject Matter
Claim 8 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDI MOHAMED MAIGA whose telephone number is (703)756-1870. The examiner can normally be reached Monday - Friday 8 am 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached on 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SIDI M MAIGA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
Prosecution Insights