DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/15/2025 have been fully considered but they are not persuasive. Applicant argued that Furutani does not disclose the second metal layer has a plating structure different from that of the first metal layer. Examiner respectfully disagreed: in PCB plating structures include plated through-holes, surface finishes, and edge plating. Changing any of these will change the structure. Hence, having different diameter constitute different structures. Regarding claim 18 as it can be seen from Furutani Fig. 1 there are more layers of via 1 (113) than layers of via 2 (213)
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 7, 9 – 10, 13 – 15, 18 – 23 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by FURUTANI (US 20250254795 A1, “FURUTANI”).
Regarding claim 1, FURUTANI discloses (Fig. 1) a printed circuit board (1), comprising: a first board unit (11) including a first insulating layer (111) having a first via hole (113a), a first wiring layer (112) disposed on or in the first insulating layer, and a first via including a first metal layer (113) substantially filling the first via hole; and a second board unit (12) including a second insulating layer (211) having a second via hole (213a), a second wiring layer (212) disposed on or in the second insulating layer, and a second via including a second metal layer (213) substantially filling the second via hole, wherein the second board unit is disposed on the first board unit, the second wiring layer has a higher wiring density than that of the first wiring layer (See Fig. 1), and the second metal layer has a plating structure different from that of the first metal layer (The second metal layer diameter is smaller than the first metal layer).
Regarding claim 3, FURUTANI discloses the printed circuit board of claim 1, wherein the first metal layer includes an electrolytic plating layer, and the second metal layer includes an electroless plating layer (See para [0037]).
Regarding claim 7, FURUTANI discloses the printed circuit board of claim 1, wherein based on a cross section of the printed circuit board, an average width of the second via hole is smaller than an average width of the first via hole, and a depth of the second via hole is smaller than a depth of the first via hole (See annotated figure below).
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Regarding claim 9, FURUTANI discloses the printed circuit board of claim 1, wherein the first and second insulating layers each include inorganic filler particles, and based on a cross section of the printed circuit board, an average diameter of the inorganic filler particles included in the second insulating layer is smaller than an average diameter of the inorganic filler particles included in the first insulating layer (See Fig. 2 and para [0035]).
Regarding claim 10, FURUTANI discloses the printed circuit board of claim 1, wherein the first wiring layer (112) includes the first metal layer (112ep) and a third metal layer (112np) disposed under the first metal layer and thinner than the first metal layer, and the second wiring layer includes the second metal layer (See para [0037] and Fig. 1).
Regarding claim 13, FURUTANI discloses the printed circuit board of claim 1, wherein the first board unit includes a core insulating layer (101, para [0027]), first and second core wiring layers (102) respectively disposed on upper and lower surfaces of the core insulating layer, a through via layer (103) passing through the core insulating layer and connecting the first and second core wiring layers to each other, a plurality of first build-up insulating layers (111) disposed on the upper surface of the core insulating layer, a plurality of first build-up wiring layers (112) respectively disposed on or in the plurality of first build-up insulating layers, a plurality of first connection via layers (113) each passing through at least one of the plurality of first build- up insulating layers and each connected to at least one of the plurality of first build-up wiring layers, a plurality of second build-up insulating layers (111) disposed on the lower surface of the core insulating layer, a plurality of second build-up wiring layers (112) respectively disposed on or in the plurality of second build-up insulating layers, and a plurality of second connection via layers (113) each passing through at least one of the plurality of second build-up insulating layers and each connected to at least one of the plurality of second build-up wiring layers; the first insulating layer is included in at least one of the plurality of first build-up insulating layers and the plurality of second build-up insulating layers; the first wiring layer is included in at least one of the plurality of first build-up wiring layers and the plurality of second build-up wiring layers; and the first via is included in at least one of the plurality of first connection via layers and the plurality of second connection via layers (See Fig. 1).
Regarding claim 14, FURUTANI discloses the printed circuit board of claim 13, wherein the second board unit includes a plurality of third build-up insulating layers (211), a plurality of third build-up wiring layers (212) respectively disposed on or in the plurality of third build-up insulating layers, and a plurality of third connection via layers (213) each passing through at least one of the plurality of third build-up insulating layers and each connected to at least one of the plurality of third build- up wiring layers; the plurality of third build-up insulating layers include the second insulating layer; the plurality of third build-up wiring layers include the second wiring layer; and the plurality of third connection via layers include the second via (See Fig. 1).
Regarding claim 15, FURUTANI discloses the printed circuit board of claim 14, further comprising: a plurality of first outer pads (12MP) disposed on the second board unit; a first resist layer (12SRA) disposed on the second board unit and having a first opening exposing the plurality of first outer pads; a plurality of second outer pads (112pB) disposed under the first board unit; a second resist layer (11SRB) disposed under the first board unit and having a plurality of second openings each exposing at least a portion of each of the plurality of second outer pads; a first semiconductor chip (E1) disposed on the second board unit and connected to some of the plurality of first outer pads through a plurality of first connection members; a second semiconductor chip (E2) disposed on the second board unit and connected to another some of the plurality of first outer pads through a plurality of second connection members; and a plurality of third connection members disposed under the first board unit and respectively connected to the plurality of second outer pads (See Fig. 1).
Regarding claim 18, FURUTANI discloses (Fig. 1) a printed circuit board (1), comprising: a first insulating layer (111) having a first via hole (113a); a first wiring layer (112) disposed on or in the first insulating layer; a first via (113) disposed in the first via hole to connect to the first wiring layer; a second insulating layer (211) having a second via hole (213a); a second wiring layer (212) disposed on or in the second insulating layer; and a second via (213) disposed in the second via hole to connect to the second wiring layer, wherein the second insulating layer is thinner than the first insulating layer, and the number of layers of the first via is greater than that of the second via (See Fig. 1).
Regarding claim 19, FURUTANI discloses the printed circuit board of claim 18, wherein based on a cross section of the printed circuit board, an average width of the second via hole is smaller than an average width of the first via hole (See Fig. 1).
Regarding claim 20, FURUTANI discloses the printed circuit board of claim 18, wherein the first and second insulating layers each include inorganic filler particles, and based on a cross section of the printed circuit board, an average diameter of the inorganic filler particles included in the second insulating layer is smaller than an average diameter of the inorganic filler particles included in the first insulating layer (See para [0059] and Fig. 2).
Regarding claim 21, FURUTANI discloses the printed circuit board of claim 18, further comprising: a core insulating layer (101) thicker than the first insulating layer (111) and the second insulating layer (211); and first and second core wiring layers (102) respectively disposed on upper and lower surfaces of the core insulating layer, wherein the first insulating layer is disposed between the core insulating layer and the second insulating layer (See Fig. 1).
Regarding claim 22, FURUTANI discloses the printed circuit board of claim 18, further comprising: an outer pad (12MP) disposed on the second insulating layer and connected to the second via; a resist layer (12SRA) disposed on the second insulating layer and having an opening exposing the outer pad; and a semiconductor chip (E1, E2) disposed on the second insulating layer and connected to the outer pad through a connection member (BL).
Regarding claim 23, FURUTANI discloses the printed circuit board of claim 18, wherein the first via and the second via are tapered in a same direction (See Fig. 1).
Claim(s) 1, 8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by FURUTANI (US 20230144361 A1, “FURUTANI ‘361”).
Regarding claim 1, FURUTANI ‘361 discloses (Fig. 1 & 2A) printed circuit board, comprising: a first board unit (10, 100, 20) including a first insulating layer (11) having a first via hole (13a), a first wiring layer (12) disposed on or in the first insulating layer, and a first via including a first metal layer (13) substantially filling the first via hole; and a second board unit (WS) including a second insulating layer (31) having a second via hole (33a), a second wiring layer (320, 32) disposed on or in the second insulating layer, and a second via including a second metal layer (33) substantially filling the second via hole, wherein the second board unit is disposed on the first board unit, the second wiring layer has a higher wiring density than that of the first wiring layer (See Fig. 1), and the second metal layer has a plating structure different from that of the first metal layer (The second metal layer diameter is smaller than the first metal layer).
Regarding claim 8, FURUTANI ‘361 discloses the printed circuit board of claim 1, wherein the first and second metal layers each include copper (Cu) (para [0032] and [0044]), the first metal layer does not include nickel (Ni),and the second metal layer further includes nickel (Ni) (see para [0044]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over FURUTANI (US 20250254795 A1, “FURUTANI”) in view of Zierath et al. (US 20200013673 A1, “Zierath”)
Regarding claim 2, FURUTANI discloses the printed circuit board of claim 1, wherein based on a cross section of the printed circuit board,
FURUTANI is silent on an average size of grains of a metal included in the second metal layer is smaller than an average size of grains of a metal included in the first metal layer.
However, Zierath discloses (Fig. 26) an average size of grains of a metal included in the second metal layer (198) is smaller than an average size of grains of a metal included in the first metal layer (136) (see Fig. 26).
FURUTANI and Zierath are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified FURUTANI to incorporate the teachings of Zierath and provide an average size of grains of a metal included in the second metal layer (198) is smaller than an average size of grains of a metal included in the first metal layer (136) (see Fig. 26). Doing so would enhance manufacturing reliability and controlled electrical properties
Claim(s) 4 – 6, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over FURUTANI (US 20250254795 A1, “FURUTANI”).
Regarding claim 4, FURUTANI discloses the printed circuit board of claim 1, wherein the first metal layer is spaced apart from a wall surface of the first via hole (See para [0037] and Fig. 2), and FURUTANI further discloses (See Fig. 1) the second metal layer is in direct contact with a wall surface of the second via hole. (In para [0037], FURUTANI discloses that both via 1 and 2 can have single metal layer in them or can also have two or more layers. One of ordinary skill in the art can modified the embodiment of Fig. 1 to include a seed layer in via 1 so that the seed layer will be between the first metal layer and the wall surface of the via hole. Doing so would enable to create a complex, reliable, and high-density circuit board)
Regarding claim 5, FURUTANI discloses the printed circuit board of claim 4, wherein the first via further includes a third metal layer disposed on the wall surface of the first via hole and having a plating structure different from that of the first metal layer, and the first metal layer is disposed on the third metal layer (see para [0037] and Fig. 2).
Regarding claim 6, FURUTANI discloses the printed circuit board of claim 5, wherein the first metal layer includes an electrolytic plating layer, and the second and third metal layers each include an electroless plating layer (para [0037]).
Regarding claim 11, FURUTANI discloses the printed circuit board of claim 10, wherein the second wiring layer does not include a metal layer other than the second metal layer (Fig. 1), FURUTANI also discloses (Fig. 2) that the first metal layer includes an electrolytic plating layer, and the second and third metal layers each include an electroless plating layer (In para [0037], FURUTANI discloses that both via 1 and 2 can have single metal layer in them or can also have two or more layers and both electroless or electrolytic method can be used. One of ordinary skill in the art can modified the embodiment of Fig. 1 to include a seed layer in via 1 so that the first metal layer includes electrolytic plating and the second and third metal layers include electroless plating layer. Doing so would enable to create a complex, reliable, and high-density circuit board)
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDI MOHAMED MAIGA whose telephone number is (703)756-1870. The examiner can normally be reached Monday - Friday 8 am 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached on 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SIDI M MAIGA/
Examiner, Art Unit 2847
/STANLEY TSO/Primary Examiner, Art Unit 2847