DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 1 in the reply filed on 9/30/25 is acknowledged. The traversal is on the ground(s) that the species should be distinguished by requiring a separate classification/field of search/and status in the art. This is not found persuasive because a second and burdensome search would be required to address the myriad of species found within the claims. Claims 2, 8-11 are hereby rejoined and rejected as recited below due to the nature of the Camacho reference including such elements without requiring multiple burdensome searched to address the myriad of species. The remaining claims are withdrawn; however Applicant is reminded that should future prosecution determine allowable subject matter and such allowable subject matter be properly incorporated into the claims, rejoinder may be possible.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) s 1-4, 6, 8-10 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Camacho et al (US 2009/0243064).
1. (original): A multi-die quad-flat no-lead (QFN) hybrid package, comprising:
a carrier (Fig. 12 (280- leadframe acts as a carrier) and [0051]) comprising a plurality of flip-chip leads (Fig. 12 (284/286) and [0004/0051]) and a plurality of wire-bonding leads (Fig.12 (leads are 284/286 for the wires 304/306/315/316) and [0051]);
a first integrated circuit die (Fig.12 (292) and [0051]) a second integrated circuit die (Fig.12 (298) and [0051]) mounted on the plurality of flip-chip leads (Fig. 12 (284/286) and [0004/0051]), respectively, in a flip-chip manner (Fig.12 and [0004]), wherein the first integrated circuit die (Fig.12 (292) and [0051]) is spaced apart from the second integrated circuit die (Fig.12 (298) and [0051]);
a third integrated circuit die (Fig.12 (308) and [0051]) stacked over the first integrated circuit die (Fig.12 (292) and [0051]) and the second integrated circuit die (Fig.12 (298) and [0051]), wherein the third integrated circuit die (Fig.12 (308) and [0051]) is electrically connected to the plurality of wire-bonding leads (Fig.12 (leads 284/286 are connected to 315/316 wires) and [0051]) around the first integrated circuit die (Fig.12 (292) and [0051]) and the second integrated circuit die (Fig.12 (298) and [0051]) through a plurality of bond wires (Fig.12 (315/316) and [0051]); and
a mold cap (Fig.12 (318) and [0051]) encapsulating the first integrated circuit die (Fig.12 (292) and [0051]), the second integrated circuit die (Fig.12 (298) and [0051]), the third integrated circuit die (Fig.12 (308) and [0051]), the plurality of bond wires (Fig.12 (304/306/315/316) and [0051]), and partially encapsulating the carrier (Fig. 12 (280- leadframe acts as a carrier) and [0051]), wherein the mold cap (Fig.12 (318) and [0051]) comprises a bottom mold cap surface (Fig.12 (318- bottom shown) and [0051]), and wherein the plurality of flip-chip leads (Fig. 12 (284/286) and [0004/0051]) and the plurality of wire-bonding leads (Fig.12 (leads are 284/286 for the wires 304/306/315/316) and [0051]) are exposed from the bottom mold cap surface (Fig.12 (318- bottom shown) and [0051]).
2. (original): The multi-die QFN hybrid package according to claim 1, wherein the carrier is a copper leadframe carrier (Fig. 12 (280) and [0051]).
3. (original): The multi-die QFN hybrid package according to claim 1, wherein the first integrated circuit die (Fig.12 (292) and [0051]) is coplanar with the second integrated circuit die (Fig.12 (298) and [0051]).
4. (original): The multi-die QFN hybrid package according to claim 1, wherein the first integrated circuit die (Fig.12 (292) and [0051]) and the second integrated circuit die (Fig.12 (298) and [0051]) have the same die height (Fig.12- die height is shown as equal).
6. (original): The multi-die QFN hybrid package according to claim 1, wherein the first integrated circuit die (Fig.12 (292) and [0051]) and the second integrated circuit die (Fig.12 (298) and [0051]) have the same die thickness.
8. (original): The multi-die QFN hybrid package according to claim 1, wherein the plurality of flip-chip leads is partially exposed from the bottom mold cap surface for further connection with an external circuit such as a main board or a printed circuit board (Fig.1 (16) and [0030-substrate/leadframe is mounted to PCB]).
9. (original): The multi-die QFN hybrid package according to claim 1, wherein the first integrated circuit die (Fig.12 (292) and [0051]) and the second integrated circuit die (Fig.12 (298) and [0051]) are electrically connected to the plurality of flip-chip leads (Fig. 12 (284/286) and [0004/0051]) through a plurality of connecting elements ((Fig.12 (304/306) and [0051]), respectively.
10. (original): The multi-die QFN hybrid package according to claim 9, wherein the plurality of connecting elements comprises a copper bump or a solder bump [0033- teaching wire bonding may be replaced with solder bumps].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 7, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Camacho et al (US 2009/0243064) in further view of Yu et al (US 2015/0187743).
Camacho teaches the limitations of claims (1 and 4) and (1 and 6) as cited above, however fails to explicitly teach the ranges of die thicknesses and heights as recited in claims 5 and 7 below:
5. (original): The multi-die QFN hybrid package according to claim 4, wherein the die height ranges between 100 micrometers and 300 micrometers.
7. (original): The multi-die QFN hybrid package according to claim 6, wherein the die thickness ranges between 100 micrometers and 250 micrometers.
Yu teaches die height/ thickness of 100-300 micrometers [0027].
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Camacho’s teachings to include the die thickness ranges as taught by Yu because such dimensions are typical die sizing of stacked dies in the semiconductor arts and are considered well known and conventional. Moreover, such ranges do not appear to be a critical aspect of the Applicant’s specification.
In regards to claim 11, Camacho teaches the limitations of claims 1 and 9 as cited above, however fails to explicitly teach the limitation of claim 11 as recited below:
11. (original): The multi-die QFN hybrid package according to claim 9, wherein each of the plurality of connecting elements comprises a copper pillar and a solder cap.
Yu teaches wherein each of the plurality of connecting elements comprises a copper pillar and a solder cap [0017].
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Camacho’s teachings to form a pillar and solder cap structure as taught by Yu, in place of the solder bump because as Yu teaches, solder capped pillars are a design alternative to the bump connector [Yu-0017]. Moreover, one of ordinary skill in the art understands that bumps; ball pillars; pads leads; pins are all well-known electrical connectors within the semiconductor arts and are suitable design alternatives.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hebert et al (US 20130043940); (US 9524957) and Lee et al (US 20050082645) teach similar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
12/28/25