DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 12-18 and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0074622 A1 to Koo et al. (hereinafter “Koo” – previously cited reference).
Regarding claim 1, Koo discloses a chip on film (COF) package comprising:
a film substrate comprising a base film having a chip mounting region (COF package 100 having a film substrate and comprising base film 110 having region for mounting chips; Figs. 1-2E; paragraphs [0023], [0038]), a main line pattern extending on the base film, and a branch line pattern extending on the base film and electrically connected to the main line pattern (conductive interconnection 120 having first portion disposed on base film 110 and having second portion extending from the first portion on base film 110; Figs. 1-2E; paragraphs [0023], [0038], [0044]);
a semiconductor chip mounted on the film substrate so as to overlap the chip mounting region (gate driver chip 200 mounted on film substrate in region for mounting chips; Figs. 1-2E; paragraphs [0023], [0038], [0049]-[0050]);
a first bump structure disposed between the semiconductor chip and the film substrate and electrically connected to the main line pattern (bonding pad 132 structure in the z-direction disposed between chip 200 and film 110 and connected to first portion of conductive interconnection 120; Figs. 1-2E; paragraphs [0023], [0038], [0045]); and
a second bump structure disposed between the semiconductor chip and the film substrate and electrically connected to the branch line pattern (bonding pad 140 structure in the z-direction disposed between chip 200 and film 110 and connected to second portion of conductive interconnection 120; Figs. 1-2E; paragraphs [0023], [0038], [0045]), the second bump structure spaced apart from the first bump structure in a first direction parallel to a first edge of the chip mounting region (pad 132, 140 structures separated in direction parallel to edge of region for mounting chips; Figs. 1-2E), wherein the branch line pattern extends so as not to overlap a first edge of the first bump structure facing the first edge of the chip mounting region and a first edge of the second bump structure facing the first edge of the chip mounting region (second portion of conductive interconnection 120 does not overlap an edge of each of pad 132, 140 structures facing edges of region for mounting chips; Figs. 1-2E).
Koo fails to disclose the first and second bump structures vertically overlapping the semiconductor chip.
However, Koo already discloses the two pads 132, 140 disposed below the chips 200, 301, 302 in the vertical Z-direction but offset therefrom in the Y-direction and so it would only require routine skill in the art to make the design choice to arrange the two pads 132, 140 to not be offset from the chips 200, 301, 302 in the Y-direction.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Koo in this manner in order to potentially provide shorter interconnect length, improved signal integrity, and reduced package footprint.
Regarding claim 2, Koo discloses the COF package of claim 1, wherein the chip mounting region has a rectangular shape in a plan view, and a length of the first edge of the chip mounting region is smaller than a length of a second edge of the chip mounting region extending in a second direction perpendicular to the first direction (region for mounting chips defined as having edges with different lengths; Figs. 1-2E).
Regarding claim 3, Koo discloses the COF package of claim 1, wherein the main line pattern and the branch line pattern are configured to transmit the same power signal (gate driver chip 200 providing power signals along conductive interconnection 120; Figs. 1-2E; paragraphs [0023], [0026], [0038], [0049]).
Regarding claim 4, Koo discloses the COF package of claim 1, wherein the main line pattern includes a first pad electrically coupled to the first bump structure and a first extension pattern extending from one side of the first pad (first portion of conductive interconnection 120 comprises bonding pad 132 structure including a pad and conductive line extending therefrom; Figs. 1-2E; paragraphs [0045], [0047]), the film substrate further includes a second pad electrically coupled to the second bump structure (film substrate comprises bonding pad 132 structure including a pad and trace extending therefrom; Figs. 1-2E; paragraphs [0045], [0047]), the first pad extends from one edge of the first bump structure to an opposite edge of the first bump structure in a second direction perpendicular to the first direction in a plan view (pad 132 extending across bonding structure from one edge to the other in direction perpendicular to pad 132, 140 structure separation direction; Figs. 1-2E; paragraphs [0045], [0047]), and the second pad extends from one edge of the second bump structure to an opposite edge of the second bump structure in the second direction in the plan view (pad 132 extending across bonding structure from one edge to the other in direction perpendicular to pad 132, 140 structure separation direction; Figs. 1-2E; paragraphs [0045], [0047]).
Regarding claim 5, Koo discloses the COF package of claim 4, wherein one end of the branch line pattern contacts the first extension pattern and the other end of the branch line pattern contacts one side surface of the second pad (second portion of conductive interconnection 120 contacts conductive line extending from first portion of conductive interconnection 120 at one end and the pad 140 at the other end; Figs. 1-2E; paragraphs [0045], [0047]).
Regarding claim 6, Koo discloses the COF package of claim 4, wherein the branch line pattern extends from one side surface of the first pad to one side surface of the second pad, and wherein the one side surface of the first pad and the one side surface of the second pad face each other in the first direction (second portion of conductive interconnection 120 disposed in part between pads 132, 140 facing one another; Figs. 1-2E; paragraphs [0045], [0047]).
Regarding claim 7, Koo discloses the COF package of claim 4, wherein the branch line pattern passes through an outer region of the base film outside the chip mounting region and extends from the main line pattern to the second pad (second portion of conductive interconnection 120 passes through edge of region for mounting chips from first portion of conductive interconnection to pad 140; Figs. 1-2E; paragraphs [0045], [0047]).
Regarding claim 8, Koo discloses the COF package of claim 7, wherein the film substrate further includes a third pad, the COF package further comprising a third bump structure disposed between the third pad and the semiconductor chip (bonding pad 131 structures disposed between pad and chip 200 in z-direction; Figs. 1-2E; paragraphs [0045], [0047]). Koo fails to explicitly disclose a third pad between the first pad and the second pad in the first direction, the COF package further comprising a third bump structure disposed between the third pad and the semiconductor chip.
However, Koo already discloses two pads 132, 140 aligned along the first direction and so it would only require routine skill in the art to make the design choice to place the already disclosed third pad 131 in alignment with the pads 132, 140 along the first direction.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Koo in this manner in order to potentially provide enhanced alignment accuracy and bonding reliability, reduced risk of short circuits and improved electrical integrity, and balanced wiring density and simplified routing.
Regarding claim 9, Koo discloses the COF package of claim 1, further comprising a heat dissipation resin layer covering the semiconductor chip on the film substrate (resin layer may be utilized to seal chip 200 on film substrate; paragraph [0054]), wherein each of the main line pattern and the branch line pattern includes copper (conductive interconnection 120 may utilize copper; paragraph [0044]), and wherein each of the first bump structure and the second bump structure includes gold (conductive pad CP includes pads 132, 140 which may be plated with gold; paragraph [0048]).
Regarding claim 10, Koo discloses the COF package of claim 1, further comprising an underfill resin layer between the film substrate and the semiconductor chip, the underfill resin layer surrounding a sidewall of the first bump structure and a sidewall of the second bump structure (resin layer may be utilized as underfill disposed under chip 200 and above film substrate comprising bonding pad 132, 140 structures; Figs. 1-2E; paragraph [0054]).
Regarding claim 13, Koo discloses a chip on film (COF) package comprising:
a film substrate (COF package 100 having a film substrate and comprising base film 110 having region for mounting chips; Figs. 1-2E; paragraphs [0023], [0038]);
a semiconductor chip mounted on the film substrate (gate driver chip 200 mounted on film substrate in region for mounting chips; Figs. 1-2E; paragraphs [0023], [0038], [0049]-[0050]);
a plurality of bump structures between the film substrate and the semiconductor chip, the plurality of bump structures comprising a first bump structure and a second bump structure (bonding pad 132, 140 structures in the z-direction disposed between chip 200 and film 110; Figs. 1-2E; paragraphs [0023], [0038], [0045]);
an underfill material layer filling a gap between the semiconductor chip and the film substrate (resin layer may be utilized as underfill disposed under chip 200 and above film substrate comprising bonding pad 132, 140 structures; Figs. 1-2E; paragraph [0054]); and
a heat dissipation resin layer covering the semiconductor chip on the film substrate (resin layer may be utilized to seal chip 200 on film substrate; paragraph [0054]), wherein the film substrate comprises:
a base film having a chip mounting region and an outer region outside the chip mounting region, the chip mounting region vertically overlapping the semiconductor chip (base film 110 having region for mounting gate driver chip 200 and region outside of that; Figs. 1-2E);
a main line pattern extending on the chip mounting region of the base film (conductive interconnection 120 having first portion disposed on base film 110; Figs. 1-2E; paragraphs [0023], [0038], [0044]), the main line pattern comprising a first pad electrically coupled to the first bump structure and a first extension pattern electrically connected to the first pad (first portion of conductive interconnection 120 comprises bonding pad 132 structure including a pad and conductive line extending therefrom; Figs. 1-2E; paragraphs [0045], [0047]);
a second pad electrically coupled to the second bump structure and spaced apart from the first pad in a first direction parallel to a first boundary of the chip mounting region (pad 132, 140 structures separated in direction parallel to edge of region for mounting chips; Figs. 1-2E); and
a branch line pattern extending between the main line pattern and the second pad and electrically connecting the first bump structure to the second bump structure (second portion of conductive interconnection 120 extends between first portion of conductive interconnection 120 and pad 140 which electrically connects it to bonding pad 132 structure; Figs. 1-2E; paragraphs [0023], [0038], [0045]), wherein the first pad extends from one edge of the first bump structure to an opposite edge of the first bump structure in a second direction perpendicular to the first direction in a plan view (pad 132 extending across bonding structure from one edge to the other in direction perpendicular to pad 132, 140 structure separation direction; Figs. 1-2E; paragraphs [0045], [0047]), wherein the second pad extends from one edge of the second bump structure to an opposite edge of the second bump structure in the second direction in the plan view (pad 132 extending across bonding structure from one edge to the other in direction perpendicular to pad 132, 140 structure separation direction; Figs. 1-2E; paragraphs [0045], [0047]), and wherein the branch line pattern is spaced apart from a first side surface of the first pad most adjacent to the first boundary of the chip mounting region and a first side surface of the second pad most adjacent to the first boundary of the chip mounting region (second portion of conductive interconnection 120 spaced apart from side surfaces of pads 132, 140 closest to edge of region for mounting chips; Figs. 1-2E).
Koo fails to disclose wherein the semiconductor chip vertically overlaps the first and second bump structures.
However, Koo already discloses the two pads 132, 140 disposed below the chips 200, 301, 302 in the vertical Z-direction but offset therefrom in the Y-direction and so it would only require routine skill in the art to make the design choice to arrange the two pads 132, 140 to not be offset from the chips 200, 301, 302 in the Y-direction.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Koo in this manner in order to potentially provide shorter interconnect length, improved signal integrity, and reduced package footprint.
Regarding claim 14, Koo discloses the COF package of claim 13, wherein, in a plan view, each of the first bump structure and the second bump structure has a rectangular shape of which length in the first direction is smaller than a length in the second direction (bonding pad 132, 140 structures have rectangular shape having edges with different length dimensions; Figs. 1-2E).
Regarding claim 15, Koo discloses the COF package of claim 13, wherein the plurality of bump structures further include third bump structures arranged along a second boundary of the chip mounting region extending in the second direction (bonding pad 132 structures disposed in second direction along boundary of region for mounting chips; Figs. 1-2E; paragraphs [0045], [0047]), and a length of the first boundary of the chip mounting region is smaller than a length of the second boundary of the chip mounting region (region for mounting chips defined as having edges with different lengths; Figs. 1-2E).
Regarding claim 16, Koo discloses the COF package of claim 15, wherein the film substrate further includes input/output interconnect patterns extending from one edge of the base film to the third bump structures (film substrate includes conductive interconnections 120 extending from edge of base film 110 to pad 132 structures; Figs. 1-2E).
Regarding claim 17, Koo discloses the COF package of claim 13, wherein the branch line pattern is entirely within the chip mounting region (second portion of conductive interconnections 120 entirely within region for mounting chips; Figs. 1-2E).
Regarding claim 18, Koo discloses the COF package of claim 13, wherein the plurality of bump structures include one or more bump structures disposed adjacent the first bump structure and the second bump structure (bonding pad 131 structure disposed adjacent pads 132, 140; Figs. 1-2E; paragraphs [0045], [0047]), and the branch line pattern extends in a path through the outer region of the chip mounting region (second portion of conductive interconnection 120 passes through edge of region for mounting chips; Figs. 1-2E; paragraphs [0045], [0047]), and wherein the first bump structure and the second bump structure are configured to receive the same power signal through the branch line pattern (bonding pad 132, 140 structures capable of receiving the same power signal from driver circuit chip 401 via one or more of gate driver chip 200 and first and second source driver chips 301, 302; Figs. 1 and 2A; paragraph [0026]).
Koo fails to explicitly disclose the plurality of bump structures include one or more bump structures disposed between the first bump structure and the second bump structure in the first direction.
However, Koo already discloses two pads 132, 140 aligned along and between the first direction and so it would only require routine skill in the art to make the design choice to place the already disclosed third pad 131 in alignment with the pads 132, 140 along the first direction.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Koo in this manner in order to potentially provide enhanced alignment accuracy and bonding reliability, reduced risk of short circuits and improved electrical integrity, and balanced wiring density and simplified routing.
Regarding claim 20, Koo discloses a display apparatus comprising:
a chip on film (COF) package comprising a film substrate (display apparatus having COF package 100 having a film substrate and comprising base film 110 having region for mounting chips; Figs. 1-2E; paragraphs [0023], [0038]), a plurality of bump structures on the film substrate, and a display driving chip on the plurality of bump structures (bonding pad 132, 140 structures in the z-direction disposed between chip 200 and film 110; Figs. 1-2E; paragraphs [0023], [0038], [0045]);
a display panel electrically connected to the film substrate (display panel 500 electrically connected to film substrate; Figs. 1-2E; paragraphs [0023], [0038]); and
a driving printed circuit board electrically connected to the film substrate, wherein the plurality of bump structures comprise a first bump structure and a second bump structure (driver PCB 400 electrically connected to film substrate along with bonding pad 132, 140 structures; Figs. 1-2E; paragraphs [0023], [0038]), wherein the film substrate comprises:
a base film having a chip mounting region and an outer region surrounding the chip mounting region, wherein the chip mounting region vertically overlaps the display driving chip (base film 110 having region for mounting gate driver chip 200 and region outside of that; Figs. 1-2E);
a main line pattern extending on the chip mounting region of the base film (conductive interconnection 120 having first portion disposed on base film 110; Figs. 1-2E; paragraphs [0023], [0038], [0044]), the main line pattern comprising a first pad electrically coupled to the first bump structure and a first extension pattern electrically connected to the first pad (first portion of conductive interconnection 120 comprises bonding pad 132 structure including a pad and conductive line extending therefrom; Figs. 1-2E; paragraphs [0045], [0047]);
a second pad electrically coupled to the second bump structure and spaced apart from the first pad in a first direction parallel to a first boundary of the chip mounting region (pad 132, 140 structures separated in direction parallel to edge of region for mounting chips; Figs. 1-2E); and
a branch line pattern extending between the main line pattern and the second pad and electrically connecting the first bump structure to the second bump structure (second portion of conductive interconnection 120 extends between first portion of conductive interconnection 120 and pad 140 which electrically connects it to bonding pad 132 structure; Figs. 1-2E; paragraphs [0023], [0038], [0045]), wherein the first pad extends from one edge of the first bump structure to another edge of the first bump structure opposite the one edge of the first bump structure in a second direction perpendicular to the first direction in a plan view (pad 132 extending across bonding structure from one edge to the other in direction perpendicular to pad 132, 140 structure separation direction; Figs. 1-2E; paragraphs [0045], [0047]), wherein the second pad extends from one edge of the second bump structure to an opposite edge of the second bump structure in the second direction in the plan view (pad 132 extending across bonding structure from one edge to the other in direction perpendicular to pad 132, 140 structure separation direction; Figs. 1-2E; paragraphs [0045], [0047]), and wherein the branch line pattern is spaced apart from a first side surface of the first pad most adjacent to the first boundary of the chip mounting region and a first side surface of the second pad most adjacent to the first boundary of the chip mounting region (second portion of conductive interconnection 120 spaced apart from side surfaces of pads 132, 140 closest to edge of region for mounting chips; Figs. 1-2E).
Koo fails to disclose a display driving chip vertically overlapping the plurality of bump structures.
However, Koo already discloses the two pads 132, 140 disposed below the driving chips 200, 301, 302 in the vertical Z-direction but offset therefrom in the Y-direction and so it would only require routine skill in the art to make the design choice to arrange the two pads 132, 140 to not be offset from the chips 200, 301, 302 in the Y-direction.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Koo in this manner in order to potentially provide shorter interconnect length, improved signal integrity, and reduced package footprint.
Regarding claim 21, Koo discloses the COF package of claim 1, wherein the main line pattern, the first and second bump structures, and the branch line pattern are disposed on a chip-facing surface of the base film (portions of conductive interconnection 120 and pads 132, 140 are disposed on a surface of base film 110 facing a chip; Figs. 1-2E), and wherein the branch line pattern extends on the chip-facing surface from the main line pattern to the second bump structure (second portion of interconnection 120 extends on the surface from first portion of interconnection 120 to pad 140; Figs. 1-2E).
Regarding claim 22, Koo discloses the COF package of claim 1, wherein the semiconductor comprises chip pads respectively contacting and electrically connecting to the first and second bump structures (chip pads 211, 311 electrically connected to pads 132, 140; Figs. 1-2E; paragraphs [0052]-[0053]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Koo in further view of US 2018/0337196 A1 to Yang (hereinafter “Yang” – previously cited reference).
Regarding claim 12, Koo discloses the COF package of claim 1. Koo fails to disclose wherein each of the first bump structure and the second bump structure has a length between about 10 µm and about 20 µm in the first direction, and each of the first bump structure and the second bump structure has a length between about 30 µm and about 50 µm in a second direction perpendicular to the first direction.
However, Yang discloses wherein each of the first bump structure and the second bump structure has a length between about 10 µm and about 20 µm in the first direction, and each of the first bump structure and the second bump structure has a length between about 30 µm and about 50 µm in a second direction perpendicular to the first direction (electrical connection pad 113 having first side dimension of 20 microns with a second side dimension proportionally larger than the first side dimension to be in a range of 30 to 50 microns; Figs. 2C-2E; paragraphs [0038], [0042]).
Koo and Yang are both considered to be analogous to the claimed invention because they are in the same field of chip-on-film technology. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Koo to incorporate the teaching of Lie in order to potentially provide higher interconnection density with fine pitch compatibility, improved electrical contact and low resistance, and enhanced mechanical reliability and stress management.
Response to Arguments
Applicant’s arguments submitted January 19, 2026 have been fully considered. Specifically, Applicant substantively amended the independent claims, submitted corresponding statements that these amendments overcome the previous rejection, and added new claims 21-22. Examiner agrees that the amended independent claims overcome the previous 35 USC 102 rejection. However, a new ground of rejection of these claims necessitated by the amendments is presented.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818