0609DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 19, 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10, 13-18 and 20-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0074622 A1 to Koo et al. (hereinafter “Koo” – previously cited reference).
Regarding claim 1, Koo discloses a chip on film (COF) package comprising:
a film substrate comprising a base film having a chip mounting region (COF package 100 having a film substrate and comprising base film 110 having region for mounting chips; Figs. 1-2E; paragraphs [0023], [0038]), a main line pattern extending on the base film, and a branch line pattern extending on the base film and electrically connected to the main line pattern (conductive interconnections 120 having first and second portions disposed on base film 110 and electrically connected to one another; Figs. 1-2E; paragraphs [0023], [0038], [0044]);
a semiconductor chip mounted on the film substrate so as to overlap the chip mounting region (gate driver chip 200 mounted on film substrate in region for mounting chips; Figs. 1-2E; paragraphs [0023], [0038], [0049]-[0050]);
a first bump structure disposed between the semiconductor chip and the film substrate and electrically connected to the main line pattern, the first bump structure vertically overlapping the semiconductor chip (first connection terminal 221 in the z-direction disposed between and overlapping with chip 200 and film 110 and connected to first portion of conductive interconnection 120; Figs. 1-2E; paragraphs [0023], [0038], [0045]); and
a second bump structure disposed between the semiconductor chip and the film substrate and electrically connected to the branch line pattern (second connection terminal 221 in the z-direction disposed between and overlapping chip 200 and film 110 and connected to second portion of conductive interconnection 120; Figs. 1-2E; paragraphs [0023], [0038], [0045]), the second bump structure spaced apart from the first bump structure in a first direction parallel to a first edge of the chip mounting region, and vertically overlapping the semiconductor chip (second connection terminal 221 overlapping chip 200 and spaced apart from first connection terminal 221 in first direction parallel to an edge of region for mounting chips; Figs. 1-2E), wherein the branch line pattern extends so as not to overlap a first edge of the first bump structure facing the first edge of the chip mounting region and a first edge of the second bump structure facing the first edge of the chip mounting region (second portion of conductive interconnections 120 does not overlap a first edge of first connection terminal 221 nor a first edge of second connection terminal 221 facing the edge of region for mounting chips; Figs. 1-2E), wherein the semiconductor chip comprises chip pads respectively contacting the first and second bump structures (chip 200 comprising pads 211 contacting each connection terminal 221; Figs. 1-2E; paragraphs [0052]-[0053]).
Regarding claim 2, Koo discloses the COF package of claim 1, wherein the chip mounting region has a rectangular shape in a plan view, and a length of the first edge of the chip mounting region is smaller than a length of a second edge of the chip mounting region extending in a second direction perpendicular to the first direction (region for mounting chips defined as having edges with different lengths; Figs. 1-2E).
Regarding claim 3, Koo discloses the COF package of claim 1, wherein the main line pattern and the branch line pattern are configured to transmit the same power signal (gate driver chip 200 providing power signals along conductive interconnection 120; Figs. 1-2E; paragraphs [0023], [0026], [0038], [0049]).
Regarding claim 4, Koo discloses the COF package of claim 1, wherein the main line pattern includes a first pad electrically coupled to the first bump structure and a first extension pattern extending from one side of the first pad (first portion of conductive interconnections 120 comprises a first sub-portion underneath first connection terminal 221 and a second sub-portion extending therefrom; Figs. 1-2E; paragraphs [0045], [0047]), the film substrate further includes a second pad electrically coupled to the second bump structure (second portion of conductive interconnections 120 of film substrate comprises a first sub-portion underneath second connection terminal 221; Figs. 1-2E; paragraphs [0045], [0047]), the first pad extends from one edge of the first bump structure to an opposite edge of the first bump structure in a second direction perpendicular to the first direction in a plan view (first sub-portion of first portion of conductive interconnections 120 extending across first connection terminal 221 in second direction perpendicular to first direction; Figs. 1-2E; paragraphs [0045], [0047]), and the second pad extends from one edge of the second bump structure to an opposite edge of the second bump structure in the second direction in the plan view (first sub-portion of second portion of conductive interconnections 120 extending across second connection terminal 221 in second direction; Figs. 1-2E; paragraphs [0045], [0047]).
Regarding claim 5, Koo discloses the COF package of claim 4, wherein one end of the branch line pattern contacts the first extension pattern and the other end of the branch line pattern contacts one side surface of the second pad (first end of second portion of conductive interconnections 120 contacts second sub-portion of first portion of conductive interconnections 120 extending therefrom and second end of second portion of conductive interconnections 120 contacts side of first sub-portion thereof; Figs. 1-2E; paragraphs [0045], [0047]).
Regarding claim 6, Koo discloses the COF package of claim 4, wherein the branch line pattern extends from one side surface of the first pad to one side surface of the second pad, and wherein the one side surface of the first pad and the one side surface of the second pad face each other in the first direction (second portion of conductive interconnections 120 extends from side of first sub-portion underneath first connection terminal 221 to side of first sub-portion underneath second connection terminal 211; Figs. 1-2E; paragraphs [0045], [0047]).
Regarding claim 7, Koo discloses the COF package of claim 4, wherein the branch line pattern passes through an outer region of the base film outside the chip mounting region and extends from the main line pattern to the second pad (second portion of conductive interconnections 120 passes through edge of region for mounting chips from first portion of conductive interconnections 120 to first sub-portion underneath second connection terminal 221; Figs. 1-2E; paragraphs [0045], [0047]).
Regarding claim 8, Koo discloses the COF package of claim 7, wherein the film substrate further includes a third pad between the first pad and the second pad in the first direction, the COF package further comprising a third bump structure disposed between the third pad and the semiconductor chip (third portion of conductive interconnections 120 of film substrate comprises a first sub-portion underneath third connection terminal 221 disposed between sub-portions underneath first and second connection terminals 221, and the third connection terminal 221 disposed between chip 200 and third portion of conductive interconnections 120; Figs. 1-2E; paragraphs [0045], [0047]).
Regarding claim 9, Koo discloses the COF package of claim 1, further comprising a heat dissipation resin layer covering the semiconductor chip on the film substrate (resin layer may be utilized to seal chip 200 on film substrate; paragraph [0054]), wherein each of the main line pattern and the branch line pattern includes copper (conductive interconnection 120 may utilize copper; paragraph [0044]), and wherein each of the first bump structure and the second bump structure includes gold (conductive interconnections 120 may be plated with gold; paragraph [0048]).
Regarding claim 10, Koo discloses the COF package of claim 1, further comprising an underfill resin layer between the film substrate and the semiconductor chip, the underfill resin layer surrounding a sidewall of the first bump structure and a sidewall of the second bump structure (resin layer may be utilized as underfill disposed under chip 200 and above connection terminals 221; Figs. 1-2E; paragraph [0054]).
Regarding claim 13, Koo discloses a chip on film (COF) package comprising:
a film substrate (COF package 100 having a film substrate and comprising base film 110 having region for mounting chips; Figs. 1-2E; paragraphs [0023], [0038]);
a semiconductor chip mounted on the film substrate comprising chip pads (gate driver chip 200 having chip pads 211 mounted on film substrate in region for mounting chips; Figs. 1-2E; paragraphs [0023], [0038], [0049]-[0050]);
a plurality of bump structures between the film substrate and the semiconductor chip, the plurality of bump structures respectively contacting the chip pads of the semiconductor chip, and the plurality of bump structures comprising a first bump structure and a second bump structure (first and second connection terminals 221 contacting chip pads 211 and in the z-direction disposed between and overlapping with chip 200 and film 110; Figs. 1-2E; paragraphs [0023], [0038], [0045]);
an underfill material layer filling a gap between the semiconductor chip and the film substrate (resin layer may be utilized as underfill disposed under chip 200 and above film substrate; Figs. 1-2E; paragraph [0054]); and
a heat dissipation resin layer covering the semiconductor chip on the film substrate (resin layer may be utilized to seal chip 200 on film substrate; paragraph [0054]), wherein the film substrate comprises: a base film having a chip mounting region and an outer region outside the chip mounting region, the chip mounting region vertically overlapping the semiconductor chip (base film 110 having region for mounting gate driver chip 200 and region outside of that; Figs. 1-2E);
a main line pattern extending on the chip mounting region of the base film (first portion of conductive interconnections 120 disposed on region for mounting chips of base film 110; Figs. 1-2E; paragraphs [0023], [0038], [0044]), the main line pattern comprising a first pad electrically coupled to the first bump structure and a first extension pattern electrically connected to the first pad (first portion of conductive interconnections 120 comprises a first sub-portion underneath first connection terminal 221 and a second sub-portion extending therefrom; Figs. 1-2E; paragraphs [0045], [0047]);
a second pad electrically coupled to the second bump structure and spaced apart from the first pad in a first direction parallel to a first boundary of the chip mounting region (second portion of conductive interconnections 120 of film substrate comprises a first sub-portion underneath second connection terminal 221 spaced apart from first sub-portion underneath first connection terminal 221 in direction parallel to boundary of region for mounting chips; Figs. 1-2E; paragraphs [0045], [0047]); and
a branch line pattern extending between the main line pattern and the second pad and electrically connecting the first bump structure to the second bump structure (second portion of conductive interconnections 120 extends between first portion of conductive interconnections 120 and first sub-portion underneath second connection terminal 221, where connection terminals 221 are electrically connected; Figs. 1-2E; paragraphs [0023], [0038], [0045]), wherein the first pad extends from one edge of the first bump structure to an opposite edge of the first bump structure in a second direction perpendicular to the first direction in a plan view (first sub-portion of first portion of conductive interconnections 120 extending across first connection terminal 221 in second direction perpendicular to first direction; Figs. 1-2E; paragraphs [0045], [0047]), wherein the second pad extends from one edge of the second bump structure to an opposite edge of the second bump structure in the second direction in the plan view (first sub-portion of second portion of conductive interconnections 120 extending across second connection terminal 221 in second direction; Figs. 1-2E; paragraphs [0045], [0047]), wherein the branch line pattern is spaced apart from a first side surface of the first pad most adjacent to the first boundary of the chip mounting region and a first side surface of the second pad most adjacent to the first boundary of the chip mounting region (second portion of conductive interconnections 120 spaced apart from side surfaces of first sub-portions of first and second portions of conductive interconnections 120 closest to edge of region for mounting chips; Figs. 1-2E), and wherein the semiconductor chip vertically overlaps the first and second bump structures (chip 200 vertically overlapping connection terminals 221; Figs. 1-2E).
Regarding claim 14, Koo discloses the COF package of claim 13, wherein, in a plan view, each of the first bump structure and the second bump structure has a rectangular shape of which length in the first direction is smaller than a length in the second direction (connection terminals 221 have rectangular shape having edges with different length dimensions; Figs. 1-2E).
Regarding claim 15, Koo discloses the COF package of claim 13, wherein the plurality of bump structures further include third bump structures arranged along a second boundary of the chip mounting region extending in the second direction (third connection terminal 221 arranged along other boundary of region for mounting chips in the second direction; Figs. 1-2E; paragraphs [0045], [0047]), and a length of the first boundary of the chip mounting region is smaller than a length of the second boundary of the chip mounting region (region for mounting chips defined as having edges with different lengths; Figs. 1-2E).
Regarding claim 16, Koo discloses the COF package of claim 15, wherein the film substrate further includes input/output interconnect patterns extending from one edge of the base film to the third bump structures (film substrate includes portions of conductive interconnections 120 extending from edge of base film 110 to connection terminals 221; Figs. 1-2E).
Regarding claim 17, Koo discloses the COF package of claim 13, wherein the branch line pattern is entirely within the chip mounting region (second portion of conductive interconnections 120 entirely within region for mounting chips; Figs. 1-2E).
Regarding claim 18, Koo discloses the COF package of claim 13, wherein the plurality of bump structures include one or more bump structures disposed between the first bump structure and the second bump structure in the first direction (third connection terminal 221 arranged between first and second connection terminals 221 in the first direction; Figs. 1-2E; paragraphs [0045], [0047]), the branch line pattern extends in a path through the outer region of the chip mounting region (second portion of conductive interconnections 120 passes through edge of region for mounting chips; Figs. 1-2E; paragraphs [0045], [0047]), and wherein the first bump structure and the second bump structure are configured to receive the same power signal through the branch line pattern (first and second connection terminals 221 capable of receiving the same power signal from chip 200 via second portion of conductive interconnections 120; Figs. 1 and 2A; paragraph [0026]).
Regarding claim 20, Koo discloses a display apparatus comprising:
a chip on film (COF) package comprising a film substrate (display apparatus having COF package 100 having a film substrate and comprising base film 110 having region for mounting chips; Figs. 1-2E; paragraphs [0023], [0038]), a plurality of bump structures on the film substrate, and a display driving chip on and vertically overlapping the plurality of bump structures, the display driving chip comprising chip pads respectively contacting the plurality of bump structure (first and second connection terminals 221 on film substrate 110 and vertically overlapping with chip 200 having pads 211 contacting terminals 221; Figs. 1-2E; paragraphs [0023], [0038], [0045]);
a display panel electrically connected to the film substrate (display panel 500 electrically connected to film substrate; Figs. 1-2E; paragraphs [0023], [0038]); and
a driving printed circuit board electrically connected to the film substrate, wherein the plurality of bump structures comprise a first bump structure and a second bump structure (driver PCB 400 electrically connected to film substrate along with first and second connection terminals 221; Figs. 1-2E; paragraphs [0023], [0038]), wherein the film substrate comprises: a base film having a chip mounting region and an outer region surrounding the chip mounting region, wherein the chip mounting region vertically overlaps the display driving chip (base film 110 having region for mounting gate driver chip 200 and region outside of that; Figs. 1-2E); a main line pattern extending on the chip mounting region of the base film (conductive interconnections 120 having first portion disposed on base film 110; Figs. 1-2E; paragraphs [0023], [0038], [0044]), the main line pattern comprising a first pad electrically coupled to the first bump structure and a first extension pattern electrically connected to the first pad (first portion of conductive interconnections 120 comprises a first sub-portion underneath first connection terminal 221 and a second sub-portion extending therefrom; Figs. 1-2E; paragraphs [0045], [0047]); a second pad electrically coupled to the second bump structure and spaced apart from the first pad in a first direction parallel to a first boundary of the chip mounting region (second portion of conductive interconnections 120 of film substrate comprises a first sub-portion underneath second connection terminal 221 spaced apart from first sub-portion underneath first connection terminal 221 in direction parallel to boundary of region for mounting chips; Figs. 1-2E; paragraphs [0045], [0047); and a branch line pattern extending between the main line pattern and the second pad and electrically connecting the first bump structure to the second bump structure (second portion of conductive interconnections 120 extends between first portion of conductive interconnections 120 and first sub-portion underneath second connection terminal 221, where connection terminals 221 are electrically connected; Figs. 1-2E; paragraphs [0023], [0038], [0045]), wherein the first pad extends from one edge of the first bump structure to another edge of the first bump structure opposite the one edge of the first bump structure in a second direction perpendicular to the first direction in a plan view (first sub-portion of first portion of conductive interconnections 120 extending across first connection terminal 221 in second direction perpendicular to first direction; Figs. 1-2E; paragraphs [0045], [0047]), wherein the second pad extends from one edge of the second bump structure to an opposite edge of the second bump structure in the second direction in the plan view (first sub-portion of second portion of conductive interconnections 120 extending across second connection terminal 221 in second direction; Figs. 1-2E; paragraphs [0045], [0047]), and wherein the branch line pattern is spaced apart from a first side surface of the first pad most adjacent to the first boundary of the chip mounting region and a first side surface of the second pad most adjacent to the first boundary of the chip mounting region (second portion of conductive interconnections 120 spaced apart from side surfaces of first sub-portions of first and second portions of conductive interconnections 120 closest to edge of region for mounting chips; Figs. 1-2E).
Regarding claim 21, Koo discloses the COF package of claim 1, wherein the main line pattern, the first and second bump structures, and the branch line pattern are disposed on a chip-facing surface of the base film (portions of conductive interconnection 120 and connection terminals 221 are disposed on a surface of base film 110 facing a chip; Figs. 1-2E), and wherein the branch line pattern extends on the chip-facing surface from the main line pattern to the second bump structure (second portion of interconnections 120 extends on the surface from first portion of interconnections 120 to second connection terminal 221; Figs. 1-2E).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Koo in further view of US 2018/0337196 A1 to Yang (hereinafter “Yang” – previously cited reference).
Regarding claim 12, Koo discloses the COF package of claim 1. Koo fails to disclose wherein each of the first bump structure and the second bump structure has a length between about 10 µm and about 20 µm in the first direction, and each of the first bump structure and the second bump structure has a length between about 30 µm and about 50 µm in a second direction perpendicular to the first direction.
However, Yang discloses wherein each of the first bump structure and the second bump structure has a length between about 10 µm and about 20 µm in the first direction, and each of the first bump structure and the second bump structure has a length between about 30 µm and about 50 µm in a second direction perpendicular to the first direction (electrical connection pad 113 having first side dimension of 20 microns with a second side dimension proportionally larger than the first side dimension to be in a range of 30 to 50 microns; Figs. 2C-2E; paragraphs [0038], [0042]).
Koo and Yang are both considered to be analogous to the claimed invention because they are in the same field of chip-on-film technology. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Koo to incorporate the teaching of Lie in order to potentially provide higher interconnection density with fine pitch compatibility, improved electrical contact and low resistance, and enhanced mechanical reliability and stress management.
Response to Arguments
Applicant’s arguments submitted May 22, 2026 have been fully considered in the previous advisory action of June 8, 2026. Examiner provides the same response below.
Regarding claim 1, Applicant first asserts that modifying Koo to vertically overlap pads 132, 140 in the Z-direction with chips 200, 301, 302 is improper because 1) pads 140 are used for testing and may be arranged to fall outside of the circuit region’s 111 cutting line 101; and 2) the modification would run counter to Koo’s intended purpose of accommodating different chip types while maintaining a predetermined bond pitch.
However, paragraph [0069] states that Koo’s invention is not limited to the arrangement of the pads 140 described by Applicant and paragraph [0066] states that the pad 140 may be arranged outside the cutting line 101, which collectively provides implication that the pad 140 can be arranged within circuit region 111 which includes a vertical overlap with chips 200, 301, 302. Additionally, Applicant only addresses pad 140 but does not discuss pad 132, which implies that modifying Koo to have the pad 132 vertically overlap chips 200, 301, 302 would be proper.
Further, while Examiner agrees that Koo’s purpose in part includes accommodating different chip types while maintaining a predetermined bond pitch, Applicant does not explain why vertical Z-direction overlap of pads 132, 140 with chips 200, 301, 302 would affect the predetermined X-Y pitch of the other pads in circuit region 111. Also, Applicant states that Koo intentionally avoids intersections or overlaps between pads and chips, but Examiner notes that each of chips 200, 301, 302 has an overlapping pad and connection terminal. Applicant further states that such modification would make the test pads less accessible and complicate routing design, but the test pads would still be accessible for testing if extending in the Z-direction in overlap with a chip in the same manner that it is accessible extending in the Y-direction. Moreover, disposing the pads 132, 140 to be overlapping the chips 200, 301, 302 in the Z-direction would reduce the X-Y footprint of the base film 110 and the length of the conductive lines extending from chips to pads. Finally, Applicant characterizes part of Koo’s intended purpose as simplified and minimized routing while also noting that Koo utilizes a dual-surface routing strategy, which appears to undermine Applicant’s characterization.
Applicant amends some of the content from claim 22 into claim 1 and argues that Koo does not disclose this limitation. Applicant’s partial amendment clarifies the context of canceled claim 22. Examiner interpreted claim 22 as the chip pads being in electrical contact with the bump structures. Given Applicant’s clarification, Examiner agrees that Koo does not disclose the pads 211, 311 physically contacting the pads 132, 140. However, Examiner notes that Koo discloses pads 211, 311 physically and electrically contacting solder ball connection terminals 221, 321.
Regarding claim 4, Examiner and Applicant already discussed this point during the interview of April 29, 2026. Applicant again asserts that the “branch line” and the “main line extension” are not pads, but Applicant’s Drawings (e.g. Fig. 3B) define the pad 143 and the main line 141 as being the same continuous material only being distinguished by a virtual dashed line drawn into Fig. 3B. Therefore, Applicant has defined the pads as being identical to and extensions of the branch and main lines. In the analysis of claim 4, Examiner distinguished between the bonding pad 132 structure including pad and trace and the pad 132 itself and the X-Y dimensional extension of the overall structure. However, after Applicant explained their intended meaning of the claim 4 language (e.g. Fig. 3B), Examiner further noted that Koo could alternatively disclose claim 4 using a portion of the conductive lines adjacent pads 132, 140 as the claimed ‘pads’ in line with Applicant’s Fig. 3B. A similar reinterpretation of Koo could also be utilized with respect to amended claim 1 and canceled claim 22.
Further, Examiner has asserted a new ground of rejection of these claims necessitated by the amendments using a new interpretation of Koo in line with Applicant’s drawings and based upon the most recent interview conducted with Applicant.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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