DETAILED ACTION
Claims 1, 11, 12, and 18 have been amended. Claims 1-20 remain pending in the application.
Claims 1, 12 and 18 are independent.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment and Arguments
Applicant's arguments regarding rejection under 35 U.S.C. §103 have been fully considered but respectfully found not persuasive.
Applicant amended independent claims 1, 12 and 18 to further specify:
processing data associated with the first plurality of etch rates using a model, wherein the model is to output, based on the first plurality of etch rates, multiple estimated surface profiles, each one of the multiple estimated surface profiles associated with a corresponding estimated placement location of multiple estimated placement locations on the substrate support, wherein the multiple estimated surface profiles are indicative of predicted etch rate profiles for substrates processed at the corresponding estimated placement locations;
determining a recommended placement for substrates on the substrate support by identifying one of the multiple estimated placement locations associated with a predicted etch rate profile having a minimized etch rate profile characteristic and satisfying one or more threshold criterion.
In the remarks, applicant argues in substance that Kang teaches constraint conditions of substrate placement show in FIG. 16 are not model outputs and not the multiple estimated surface profiles, therefore, Kang does not teach identifying one of the multiple estimated placement locations associated with a predicted etch rate profile having a minimized etch rate profile characteristic.
While the examiner agrees that Kang teaches constraint conditions of substrate placement show in FIG. 16 are not model outputs and not the multiple estimated surface profiles. However, the examiner respectfully submit that applicant has overlooked the fact that Kang teaches use constraint conditions of substrate placement show in FIG. 16 as an input to an optimization model to calculate "residual difference from an Edge average of a current Run" i.e. “model outputs” and “multiple estimated surface profiles” corresponding to pairs of fork position RT and FB i.e. “estimated placement locations”, and identifying one of the multiple estimated placement locations associated with a predicted etch rate profile having a minimized etch rate profile characteristic ([0048] teaching position i.e. wafer placement position, Figs. 8, 14-17 [0093] – [0099] the machine learning model is trained based on the wafer profile results, teach position (defined by a pair of fork position RT and FB) within an acceptable range (Fig. 16 constraint condition) are used as an input to the optimization model that uses the trained machine learning model, for each run, the optimization model calculates an evaluation function J:
Evaluation Function J=f (residual difference from an Edge average of a current Run, model RT FE vs Unevenness of Each Point, movement change amount);
The "residual difference from an Edge average of a current Run" is the residual difference between the average film thickness of the current Run and the fill thickness of the monitor locations MP1 to M24 i.e. “estimated surface profiles” corresponding to current pair of RT and FB i.e. “associated with a corresponding estimated placement location”; the "movement change amount" of the evaluation function J represents the RT movement amount and the FB movement amount set in the next Run; The optimization model search the pairs of RT and FB within the constrain defined in the table of Fig. 16 with multiple runs, each run with different pairs of RT and FB, calculation corresponding residual difference from an Edge average of a current Run, i.e. the model is to output “multiple estimated surface profiles, each one of the multiple estimated surface profiles associated with a corresponding estimated placement location of multiple estimated placement locations on the substrate support”, and finds the pair that have the minimum evaluation function J). Therefore, applicant’s arguments are not persuasive.
The teachings of CHEN, KANG, LEE, Yamaguchi, Sakamoto, and IKEDA as disclosed in the previous office action are hereby incorporated by references to the extent applicable to the amended claims.
Another iteration of claim analysis has been made. Referring to the corresponding sections of the claim analysis below for details.
Priority
This application is filed as CIP of prior Application No. 17822009. The filed claims 1-20 includes the newly added subject matter is entitled ONLY to the actual filing date of the CIP: 05/23/2023.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, 10, 12, 15 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over CHEN US 20080080845 A1 in view of KANG US 20220270904 A1 and LEE US 20180114675 A11.
Regarding claim 12, CHEN teaches a system comprising:
a process chamber comprising a substrate support (Fig .1 [0034] [0047] PM modules etching wafers with a substrate chuck);
a substrate measurement tool ([0045] metrology tool 116);
a memory ([0032] computer readable medium);
a processing device operatively coupled to the memory ([0032] computer) the processing device to:
cause a first substrate to be processed in the process chamber while the first substrate is supported by the substrate support at a first placement location on the substrate support (Fig. 6 [0066] substrate is geometrically centered and processed), wherein the first substrate comprises a first surface profile after the processing (Figs. 2B & 6-7 [0054] [0055] [0064] – [0067] the film surface profile after etching process);
generate a first surface profile map of the first surface profile using the substrate measurement tool (Figs. 2B & 6-7 [0067] – [0068] the etched film thickness is measured at the predetermined locations);
determine a first plurality of etch rates corresponding to a first plurality of locations on the first substrate based on the first surface profile map (Figs. 2B & 6-7 [0069] – [0071] etch rate profile of teach data location is calculated);
process data associated with first plurality of etch rates using a model to determine a recommended placement for substrates on the substrate support (Figs. 2B & 6-7 [0072] – [0075] the created etch profiled data are analyzed by models to determine the parameters for substate offset); and
cause one or more of the substrates to be placed on the substrate support according to the recommended placement ([0124] robotic arm is taught to offset a substrate for next run).
CHEN does not explicitly further teach:
the model is to output, based on the first plurality of etch rates, multiple estimated surface profiles, each one of the multiple estimated surface profiles associated with a corresponding estimated placement location of multiple estimated placement locations on the substrate support, wherein the multiple estimated surface profiles are indicative of predicted etch rate profiles for substrates processed at the corresponding estimated placement locations; the recommended placement is by identifying one of the multiple estimated placement locations associated with a predicted etch rate profile having a minimized etch rate profile characteristic; and
the recommendation satisfying one or more threshold criterion.
KANG explicitly teaches in an analogous art that the model is to output, based on the first plurality of etch rates, multiple estimated surface profiles, each one of the multiple estimated surface profiles associated with a corresponding estimated placement location of multiple estimated placement locations on the substrate support, wherein the multiple estimated surface profiles are indicative of predicted etch rate profiles for substrates processed at the corresponding estimated placement locations; the recommended placement is by identifying one of the multiple estimated placement locations associated with a predicted etch rate profile having a minimized etch rate profile characteristic ([0048] teaching position i.e. wafer placement position, Figs. 8, 14-17 [0093] – [0099] the machine learning model is trained based on the wafer profile results, teach position (defined by a pair of fork position RT and FB) within an acceptable range (Fig. 16 constraint condition) are used as an input to the optimization model that uses the trained machine learning model, for each run, the optimization model calculates an evaluation function J:
Evaluation Function J=f (residual difference from an Edge average of a current Run, model RT FE vs Unevenness of Each Point, movement change amount);
The "residual difference from an Edge average of a current Run" is the residual difference between the average film thickness of the current Run and the fill thickness of the monitor locations MP1 to M24 i.e. “estimated surface profiles” corresponding to current pair of RT and FB i.e. “associated with a corresponding estimated placement location”; the "movement change amount" of the evaluation function J represents the RT movement amount and the FB movement amount set in the next Run; The optimization model search the pairs of RT and FB within the constrain defined in the table of Fig. 16 with multiple runs, each run with different pairs of RT and FB, calculation corresponding residual difference from an Edge average of a current Run, i.e. the model is to output “multiple estimated surface profiles, each one of the multiple estimated surface profiles associated with a corresponding estimated placement location of multiple estimated placement locations on the substrate support”, and finds the pair that have the minimum evaluation function J); and
LEE explicitly teaches in an analogous art that the recommendation satisfying one or more threshold criterion ([0136] the etch rate profile satisfying the uniformity threshold);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified CHEN to incorporate the teachings of KANG and LEE, because they all directed to wafer processing system, to make the system wherein the model is to output, based on the first plurality of etch rates, multiple estimated surface profiles, each one of the multiple estimated surface profiles associated with a corresponding estimated placement location of multiple estimated placement locations on the substrate support, wherein the multiple estimated surface profiles are indicative of predicted etch rate profiles for substrates processed at the corresponding estimated placement locations; the recommended placement is by identifying one of the multiple estimated placement locations associated with a predicted etch rate profile having a minimized etch rate profile characteristic; and the recommendation satisfying one or more threshold criterion. One of ordinary skill in the art would have been motivated to do this modification so as to provide optimum substrate placement, as KANG teaches in [0081].
Regarding claim 15, KANG further teaches that the model comprises a trained machine learning model and train a machine learning model to produce the trained machine learning model, wherein the machine learning model is trained using data from a plurality of processed substrates processed in the process chamber ([0078] – [0080] the learning function learns based on the inputs of processing results).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified CHEN to incorporate the teachings of KANG, because they all directed to wafer processing system, to make the system wherein the model comprises a trained machine learning model and train a machine learning model to produce the trained machine learning model, wherein the machine learning model is trained using data from a plurality of processed substrates processed in the process chamber. One of ordinary skill in the art would have been motivated to do this modification so as to provide optimum substrate placement, as KANG teaches in [0081].
Regarding claim 17, CHEN further teaches the recommended placement corresponds to an optimized placement location on the substrate support for producing a second substrate having a second plurality of etch rates at a second plurality of locations on the second substrate conforming to one or more values of one or more metrics ([0075] the corrected substrate offset is used to process the subsequent substate to obtain improved substrate profile).
Regarding claim 1, it is directed to non-transitory computer readable medium comprising instructions of carrying out the system with similar limitations as set forth in claim 12. Since CHEN, KANG and LEE teach the claimed system, they teach the instructions for implementing the system.
Regarding claim 18, it is directed to method of carrying out the system with similar limitations as set forth in claim 12. Since CHEN, KANG and LEE teach the claimed system, they teach the method steps for implementing the system.
Regarding claim 4, CHEN further teaches the recommended placement is offset from a center of the substrate support ([0074] substrate offset).
Claims 5-6 recite similar limitations to that of claim 15 therefore is rejected on the same basis.
Regarding claim 7, CHEN further teaches the first plurality of locations on the first substrate correspond to locations at a radial distance from a center of the first substrate at a plurality of azimuthal angles (Fig. 2B [0053]).
Claim 10 recites similar limitations to that of claim 17 therefore is rejected on the same basis.
Claims 2, 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over CHEN in view of KANG and LEE as applied to claims 1, 4-7, 10, 12, 15 and 17-18 above, further in view of Yamaguchi US 20140087565 A12.
Regarding claims 2, 13 and 19, CHEN further teaches cause a second substrate to be placed in the process chamber on the substrate support according to the recommended placement ([0075] subsequent substrate is placed on the substrate chuck with offset).
The combination of CHEN, KANG and LEE does not explicitly further teach the substrate is placed within an inner diameter of a process kit ring.
Yamaguchi explicitly teaches in an analogous art that the substrate is placed within an inner diameter of a process kit ring (Yamaguchi: [0141] ring holder internal diameter greater than the wafer diameter).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified CHEN, KANG and LEE to incorporate the teachings of Yamaguchi, because they all directed to wafer processing system, to make the non-transitory computer readable medium/system/method wherein the substrate is placed within an inner diameter of a process kit ring. One of ordinary skill in the art would have been motivated to do this modification so as to hold the wafer in processing chamber, as Yamaguchi teaches in [0141].
Claims 3 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over CHEN in view of KANG and LEE as applied to claims 1, 4-7, 10, 12, 15 and 17-18 above, further in view of Sakamoto US 20040159284 A13.
Regarding claims 3 and 14, the combination of CHEN, KANG and LEE does not explicitly further teach:
cause a second substrate to be processed in the process chamber while the second substrate is supported by the substrate support at a second placement location on the substrate support, wherein the second substrate comprises a second surface profile after the processing;
generate a second surface profile map of the second surface profile using the substrate measurement tool;
determine a second plurality of etch rates corresponding to a second plurality of locations on the second substrate based on the second surface profile map; and
process data associated with the second plurality of etch rates using the model, wherein the one or more estimated surface profiles associated with the one or more estimated placement locations on the substrate support are further based on the second plurality of etch rates.
Sakamoto explicitly teaches in an analogous art:
cause a second substrate to be processed in the process chamber while the second substrate is supported by the substrate support at a second placement location on the substrate support, wherein the second substrate comprises a second surface profile after the processing;
generate a second surface profile map of the second surface profile using the substrate measurement tool;
determine a second plurality of etch rates corresponding to a second plurality of locations on the second substrate based on the second surface profile map; and
process data associated with the second plurality of etch rates using the model, wherein the one or more estimated surface profiles associated with the one or more estimated placement locations on the substrate support are further based on the second plurality of etch rates ([0087] – [0098] the placement optimization is repeated, the correction amount with respect to previous run are used for the next run placement).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified CHEN, KANG and LEE to incorporate the teachings of Sakamoto, because they all directed to wafer processing system, to make the non-transitory computer readable medium/system wherein the placement optimization is repeated. One of ordinary skill in the art would have been motivated to do this modification so as to obtain new placement correction amount, as Sakamoto teaches in [0086].
Claims 8-9, 11, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over CHEN in view of KANG and LEE as applied to claims 1, 4-7, 10, 12, 15 and 17-18 above, further in view of IKEDA WO 2012073449 A14.
Regarding claim 16, CHEN further teaches wherein the one or more estimated surface profiles are based on a etch rate profile ([0071] an etch rate profile is generated for each orientation and is used for the curve fitting i.e. “estimated surface profiles”).
The combination of CHEN, KANG and LEE does not explicitly further teach:
normalizing each of the first plurality of etch rates based on an average etch rate of the first plurality of etch rates; and
the etch rate profile is a linear fitment of at least a first etch rate of the first plurality of etch rates corresponding to at least a first location of the first plurality of locations.
IKEDA explicitly teaches in an analogous art that:
normalizing each of the first plurality of etch rates based on an average etch rate of the first plurality of etch rates (Fig. 10, page 7 paragraph 4 etching rate is normalized by an average etching rate); and
the etch rate profile is a linear fitment of at least a first etch rate of the first plurality of etch rates corresponding to at least a first location of the first plurality of locations (IKEDA: Fig. 10, page 7 paragraph 4, the normalized etching rate is fit by a linear function).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified CHEN, KANG and LEE to incorporate the teachings of IKEDA, because they all directed to wafer processing system, to make the non-transitory computer readable medium/system/method wherein normalizing each of the first plurality of etch rates based on an average etch rate of the first plurality of etch rates; and the etch rate profile is a linear fitment of at least a first etch rate of the first plurality of etch rates corresponding to at least a first location of the first plurality of locations. One of ordinary skill in the art would have been motivated to do this modification so as to adjust etching rate distribution, as IKEDA teaches in page 7 paragraph 4.
Claims 8-9 and 20 recites similar limitations to that of claim 16 therefore is rejected on the same basis.
Claim 11 recites similar limitations to that of claim 16 therefore is rejected on the same basis. In addition, CHEN further teaches the first surface profile comprises a first thickness profile (Figs. 2B & 6-7 [0054] [0055] [0064] – [0067] the film thickness profile after etching process).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael Tang whose telephone number is (571)272-7437. The examiner can normally be reached M-F 7:30-4 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamini Shah can be reached on (571)272-2279. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.T./ Examiner, Art Unit 2115
/KAMINI S SHAH/ Supervisory Patent Examiner, Art Unit 2115
1 CHEN, KANG and LEE are the prior arts of record
2 Yamaguchi is the prior art of record
3 Sakamoto is the prior art of record
4 IKEDA is the prior art of record
Prosecution Insights