DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-23, 26-30 and 32-33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (PG Pub. No. US 2021/0126113 A1).
Regarding claim 21, Lin teaches an integrated circuit structure (figs. 1, 13A-13B among others: 101), comprising:
a set of nanowires (¶ 0072: 701) over a first sub-fin (¶ 0098, fig. 13B: set of 701 arranged over right fin 105);
a gate stack (¶¶ 0072, 0081: 703/107/801) surrounding each of the nanowires of the set of nanowires (fig. 13B: at least portions 703/107 surround each 701), the gate stack comprising a gate dielectric (703) and a gate electrode (107), the gate dielectric in contact with each of the nanowires of the set of nanowires (fig. 13G: 703 contacts each 701), and the gate dielectric on the top surface and along sides of the first sub-fin (fig. 13B: 703 contacts top and upper side surfaces of 105);
a fin-trim isolation structure (¶ 0099: 111) over a second sub-fin (fig. 13: 111 arranged over left fin 105);
a trench isolation structure (¶ 0030: 209) along sides of the first sub-fin and the second sub-fin (fig. 13B: 209 arranged along sides of both 105); and
a dielectric gate cut plug (¶ 0092: 109) laterally between the set of nanowires and the fin-trim isolation structure (fig. 13B: 109 arranged laterally between set of 701 and 111), the dielectric gate cut plug in contact with the fin-trim isolation structure (fig. 13B: 109 contacts 111), the dielectric gate cut plug in contact with the gate electrode of the gate stack (fig. 13B: 109 contacts 107), and the dielectric gate cut plug extending into the trench isolation structure between the first sub-fin and the second sub-fin (fig. 13B: 109 contacts top surface of 209, meeting the broadest reasonable interpretation of “extending into”).
Regarding claim 22, Lin teaches the integrated circuit structure of claim 21, wherein the set of nanowires comprises a first nanowire over the sub-fin, a second nanowire over the first nanowire, and a third nanowire over the second nanowire (¶ 0029 & fig. 13B: set of 701 includes at least three individual nanowires 701 formed from at least three layers of 207).
Regarding claim 23, Lin teaches the integrated circuit structure of claim 21, wherein the fin-trim isolation structure has a top surface at a same level as a top surface of the dielectric gate cut plug (fig. 13B: top surface of 111 at same level as top surface of 109).
Regarding claim 25, Lin teaches the integrated circuit structure of claim 21, wherein the dielectric gate cut plug has a lateral width less than a lateral width of the fin-trim isolation structure (¶¶ 0092, 0096 & fig. 13B: width W3 of 109 less than width W5 of 111).
Regarding claim 26, Lin teaches the integrated circuit structure of claim 21, wherein the second sub-fin has a top surface below a top surface of the first sub-fin (¶ 0098 & figs. 12B, 13B: top surface of left 105 below top surface of right 105 by depth D2).
Regarding claim 28, Lin teaches an integrated circuit structure (figs. 1, 13A-13B: 100), comprising:
a set of nanowires (¶ 0072: 701) over a first sub-fin (¶ 0098 & fig. 13B: set of 701 arranged over right fin 105);
a gate stack (¶¶ 0072, 0081: 703/107/810) surrounding each of the nanowires of the set of nanowires (fig. 13B: at least 703/107 surrounds each 701), the gate stack comprising a gate dielectric (703) and a gate electrode (107), the gate dielectric in contact with each of the nanowires of the set of nanowires (fig. 13B: 703 contacts each 701), and the gate dielectric on the top surface and along sides of the first sub-fin (fig. 13B: 703 arranged on top surface and upper side portions of right fin 105);
a first isolation structure (¶ 0099: 111) over a second sub-fin (fig. 13B: 111 arranged over left fin 105);
a second isolation structure (¶ 0030: 209) along sides of the first sub-fin and the second sub-fin (fig. 13B: 209 arranged along sides of left and right fins 105); and
a dielectric structure (¶ 0092: 109) laterally between the set of nanowires and the first isolation structure (fig. 13B: 109 arranged laterally between set of 701 and 111), the dielectric structure in contact with the first isolation structure (fig. 13B: 109 in contact with 111), the dielectric structure in contact with the gate electrode of the gate stack (fig. 13B: 109 in contact with 107), and the dielectric structure extending into the second isolation structure between the first sub-fin and the second sub- fin (fig. 13B: 109 contacts a top surface of 209, meeting the broadest reasonable interpretation of “extending into”).
Regarding claim 29, Lin teaches the integrated circuit structure of claim 28, wherein the set of nanowires comprises a first nanowire over the sub-fin, a second nanowire over the first nanowire, and a third nanowire over the second nanowire (¶ 0029 & fig. 13B: set of 701 includes at least three individual nanowires 701 formed from at least three layers of 207).
Regarding claim 30, Lin teaches the integrated circuit structure of claim 28, wherein the first isolation structure has a top surface at a same level as a top surface of the dielectric structure (fig. 13B: top surface of 111 at same level as top surface of 109).
Regarding claim 32, Lin teaches the integrated circuit structure of claim 28, wherein the dielectric structure has a lateral width less than a lateral width of the fin-trim isolation structure (¶¶ 0092, 0096 & fig. 13B: width W3 of 109 less than width W5 of 111).
Regarding claim 33, Lin teaches the integrated circuit structure of claim 28, wherein the second sub-fin has a top surface below a top surface of the first sub-fin (¶ 0098 & figs. 12B, 13B: top surface of left 105 below top surface of right 105 by depth D2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 24, 27, 31 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claims 23, 28 and 30 above, and further in view of Ng et al. (PG Pub. No. US 2021/0183855 A1).
Regarding claim 24, Lin teaches the integrated circuit structure of claim 23, wherein the top surface of the dielectric gate cut plug is at a same level as a top surface of the gate stack (fig. 13B: top surface of 109 at same level as top surface of 801 of stack 703/107/801).
Lin does not teach the top surface of the dielectric gate cut plug is at a same level as a top surface of the gate electrode of the gate stack.
Ng teaches an integrated circuit structure (figs. 2K-1 to 2K-4 among others) including a top surface of a dielectric gate cut plug (¶ 0086: 174) at a same level as a top surface of a gate electrode of a gate stack (¶ 0088 & fig. 2K-2: top surface of 174 coplanar with a top surface of gate electrode 166).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the device of Lin to include a top surface of the dielectric gate cut plug at a same level as a top surface of the gate electrode, as a means to minimize contact resistance to the top of the gate electrode, and/or improve manufacturing efficiency by minimizing manufacturing steps required to form gate vias (1409 of Lin).
Regarding claim 31, Lin teaches the integrated circuit structure of claim 30, wherein the top surface of the dielectric structure is at a same level as a top surface of the gate stack (fig. 13B: top surface of 109 at same level as top surface of stack 703/107/801).
Lin does not teach the top surface of the dielectric structure is at a same level as a top surface of the gate electrode of the gate stack.
Ng teaches an integrated circuit structure (figs. 2K-1 to 2K-4 among others) including a top surface of a dielectric structure (¶ 0086: 174) at a same level as a top surface of a gate electrode of a gate stack (¶ 0088 & fig. 2K-2: top surface of 174 coplanar with a top surface of gate electrode 166).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the device of Lin to include a top surface of the dielectric structure at a same level as a top surface of the gate electrode, as a means to minimize contact resistance to the top of the gate electrode, and/or improve manufacturing efficiency by minimizing manufacturing steps required to form gate vias (1409 of Lin).
Regarding claim 27, Lin teaches the integrated circuit structure of claim 28, comprising a fin-trim isolation structure (111) and a gate electrode (107) of a gate electrode stack.
Lin does not teach wherein the fin-trim isolation structure has a top surface at a same level as a top surface of the gate electrode of the gate stack.
Ng teaches an integrated circuit structure (figs. 2K-1 to 2K-4 among others) including a top surface of a fin-trim isolation structure (¶ 0058: 148) at a same level as a top surface of a gate electrode of a gate stack (¶ 0088 & fig. 2K-3: top surface of 148 coplanar with a top surface of gate electrode 166).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the device of Lin to include a top surface of the fin-trim isolation structure at a same level as a top surface of the gate electrode, as a means to minimize contact resistance to the top of the gate electrode, and/or improve manufacturing efficiency by minimizing manufacturing steps required to form gate vias (1409 of Lin).
Regarding claim 34, Lin teaches the integrated circuit structure of claim 28, comprising a first isolation structure (111) and a gate electrode (107) of a gate electrode stack.
Lin does not teach wherein the first isolation structure has a top surface at a same level as a top surface of the gate electrode of the gate stack.
Ng teaches an integrated circuit structure (figs. 2K-1 to 2K-4 among others) including a top surface of a first isolation structure (¶ 0058: 148) at a same level as a top surface of a gate electrode of a gate stack (¶ 0088 & fig. 2K-3: top surface of 148 coplanar with a top surface of gate electrode 166).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the device of Lin to include a top surface of the first isolation structure at a same level as a top surface of the gate electrode, as a means to minimize contact resistance to the top of the gate electrode, and/or improve manufacturing efficiency by minimizing manufacturing steps required to form gate vias (1409 of Lin).
Claims 35-40 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Guler et al. (PG Pub. No. US 2022/0093592 A1).
Regarding claim 35 Lin teaches a device, comprising
an integrated circuit structure (figs. 1, 13A-13B among others: 101), comprising:
a set of nanowires (¶ 0072: 701) over a first sub-fin (¶ 0098, fig. 13B: set of 701 arranged over right fin 105);
a gate stack (¶¶ 0072, 0081: 703/107/801) surrounding each of the nanowires of the set of nanowires (fig. 13B: at least portions 703/107 surround each 701), the gate stack comprising a gate dielectric (703) and a gate electrode (107), the gate dielectric in contact with each of the nanowires of the set of nanowires (fig. 13G: 703 contacts each 701), and the gate dielectric on the top surface and along sides of the first sub-fin (fig. 13B: 703 contacts top and upper side surfaces of 105);
a fin-trim isolation structure (¶ 0099: 111) over a second sub-fin (fig. 13: 111 arranged over left fin 105);
a trench isolation structure (¶ 0030: 209) along sides of the first sub-fin and the second sub-fin (fig. 13B: 209 arranged along sides of both 105); and
a dielectric gate cut plug (¶ 0092: 109) laterally between the set of nanowires and the fin-trim isolation structure (fig. 13B: 109 arranged laterally between set of 701 and 111), the dielectric gate cut plug in contact with the fin-trim isolation structure (fig. 13B: 109 contacts 111), the dielectric gate cut plug in contact with the gate electrode of the gate stack (fig. 13B: 109 contacts 107), and the dielectric gate cut plug extending into the trench isolation structure between the first sub-fin and the second sub-fin (fig. 13B: 109 contacts top surface of 209, meeting the broadest reasonable interpretation of “extending into”).
Lin does not teach the device is a computing device, comprising:
a board; and
a component coupled to the board, the component including the integrated circuit structure.
Guler teaches a computing device (¶ 0019 & fig. 9: 900), comprising:
a board (¶ 0142: 902); and
a component (¶ 0145) coupled to the board (fig. 9: at least one component coupled to 902), the component including an integrated circuit structure (¶ 0147: component housed in 900 and at least indirectly coupled to 902 comprises an integrated circuit die).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the computing device of Guler with the integrated circuit structure of Lin, as a means to provide an electronic device that processes data (Guler, ¶ 0148).
Since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 538, 416, 82 USPQ2d 1385, 1395 (2007); Sakraida v. AG Pro, Inc., 425 U.S. 273, 282, 189 USPQ 449, 453 (1976); Anderson' s-Black Rock, Inc. v. Pavement Salvage Co., 396 U.S. 57, 62-63, 163 USPQ 673, 675 (1969); Great Atlantic & P. Tea Co. v. Supermarket Equip. Corp., 340 U.S. 147, 152, 87 USPQ 303, 306 (1950). See MPEP § 2143.02. In the instant case, the integrated circuit structure of Lin could have been combined with the computing device of Guler, with no change in their respective functions.
Regarding claim 36, Lin in view of Guler teaches the computing device of claim 35, further comprising:
a memory (Guler, ¶ 0143: DRAM) coupled to the board (Guler, fig. 9: DRAM coupled to 902).
Regarding claim 37, Lin in view of Guler teaches the computing device of claim 35, further comprising:
a communication chip (Guler, ¶ 0143: 146) coupled to the board (Guler, fig. 9: 146 coupled to 902).
Regarding claim 38, Lin in view of Guler teaches the computing device of claim 35, further comprising:
a battery (Guler, ¶ 0143: battery) coupled to the board (Guler, fig. 9: battery coupled to 902).
Regarding claim 39, Lin in view of Guler teaches the computing device of claim 35, further comprising:
a display (Guler, ¶ 0143: touchscreen display) coupled to the board (Guler, fig. 9: touchscreen display coupled to 902).
Regarding claim 40, Lin in view of Guler teaches the computing device of claim 35, wherein the component is a packaged integrated circuit die (Guler, ¶ 0145).
Conclusion
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/BRIAN TURNER/Examiner, Art Unit 2818
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