DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the amendment filed 5/7/2026 in which claims 1 and 5 were amended and claims 2-4 were cancelled.
Claims 1 and 5-10 remain pending and are presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Shan (CN 113539957 and Shan hereinafter; a machine translation is used as an English language equivalent) in view of Yamazaki et al (JP 3850461 and Yamazaki hereinafter; a machine translation is used as an English language equivalent) in view of Chang (US 2020/0090979 and Chang hereinafter)
As to claims 1, 5, and 6: Shan discloses [claim 1] a method for fabricating a semiconductor device (Figs. 8, 15, and 16), comprising: forming a gate material layer (Fig. 8; 500; [0098]) on a substrate (400; [0098]), wherein the gate material layer (500) comprises an amorphous material (amorphous silicon; [0098]) having a phase transition temperature (crystallization temperature; [0098]), the amorphous material (amorphous silicon) converts into a polycrystalline material (polycrystalline silicon; [0101]) at the phase transition temperature ([0098] and [0101]), the amorphous material (500) comprises amorphous silicon (amorphous silicon; [0098]); forming a first hard mask (Fig. 8; 510; [0109]) on the gate material layer (500) at a first process temperature (inherently a process temperature is used in depositing the mask material 510; [0109]), wherein the first process temperature is less than the phase transition temperature (as the material 500 remains amorphous from its formation through etching of the mask materials 510 and 520, the first process temperature of the first hard mask 510 is below the crystallization temperature/phase transition temperature; [0114], [0120], [0122], and [0157]-[0163]), the first hard mask (510) comprises a nitride (silicon nitride; [0111]); and forming a second hard mask (Fig. 8; 520; [0109]) on the first hard mask (510) at a second process temperature (inherently a process temperature is used in depositing the mask material 520; [0109]), wherein the second process temperature is less than the phase transition temperature (as the material 500 remains amorphous from its formation through etching of the mask materials 510 and 520, the second process temperature of the second hard mask 520 is below the crystallization temperature/phase transition temperature; [0114], [0120], [0122], and [0157]-[0163]); [claim 6] wherein the second hard mask (520) comprises an oxide (silicon oxide; [0113]).
Shan fails to expressly disclose where [claim 1] the phase transition temperature is 590 0C to 610 0C; the first process temperature is greater than or equal to 560 0C, and is less than 590 0C; [claim 5] wherein reactants for forming the first hard mask comprises hexachlorodisilane and ammonia.
Shan discloses that the first hard mask is silicon nitride and inherently teaches that the silicon nitride is formed below the phase transition temperature of amorphous silicon in order to keep the silicon material amorphous.
Yamazaki discloses in [0129] that amorphous silicon can have a crystallization temperature/phase transition temperature of about 600 0C to 650 0C and the temperature is dependent upon the method of forming the film and the film thickness.
Chang discloses in [0073] that a hardmask of silicon nitride can be formed using hexachlorodisilane and ammonia at a temperature of between 570 0C and 650 0C.
The disclosed phase transition temperature of amorphous silicon overlaps with the claimed range; and the disclosed film formation temperature for silicon nitride overlaps with the claimed range.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary skills to form the amorphous silicon using a method and to a desired thickness that allows for later layers to be formed at temperatures well known in the prior art using well known reactants such that the phase transition temperature of the formed amorphous silicon overlaps with the claimed range and the temperature of formation of the first hardmask of silicon nitride is below the phase transition temperature and within the claimed range in order to ensure that the silicon nitride formed is of good quality and prevents crystallization of the amorphous material of Shan as desired by Shan.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Shan in view of Yamazaki in view of Chang as applied to claim 6 above, and further in view of Tran et al (US 2009/0035584 and Tran hereinafter).
As to claims 7 and 8: Although the method disclosed by Shan in view of Yamazaki in view of Chang shows substantial features of the claimed invention (discussed in paragraph 8 above), it fails to expressly disclose:
[claim 7] wherein the second process temperature is greater than or equal to 380 0C, and is less than or equal to 420 0C; [claim 8] wherein reactants for forming the second hard mask comprise silane and nitrous oxide.
Shan discloses that the second hard mask is silicon oxide and inherently teaches that the silicon oxide is formed below the phase transition temperature of amorphous silicon in order to keep the silicon material amorphous.
Yamazaki discloses in [0129] that amorphous silicon can have a crystallization temperature/phase transition temperature of about 600 0C to 650 0C and the temperature is dependent upon the method of forming the film and the film thickness.
Tran discloses in [0040] that a hard mask formed of silicon oxide can be formed using silane and nitrous oxide (N2O) at a temperature of less than about 400 0C.
The disclosed phase transition temperature of amorphous silicon overlaps with the claimed range; and the disclosed film formation temperature for silicon oxide overlaps with the claimed range.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary skills to form the amorphous silicon using a method and to a desired thickness that allows for later layers to be formed at temperatures well known in the prior art using well known reactants such that the phase transition temperature of the formed amorphous silicon overlaps with the claimed range and the temperature of formation of the second hardmask of silicon oxide is below the phase transition temperature and within the claimed range in order to ensure that the silicon oxide formed is of good quality and prevents crystallization of the amorphous material of Shan as desired by Shan.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Shan in view of Yamazaki in view of Chang as applied to claim 1 above, and further in view of Zhang et al (CN 104183477 and Zhang hereinafter; a machine translation is used as an English language equivalent).
Although the method disclosed by Shan in view of Yamazaki in view of Chang shows substantial features of the claimed invention (discussed in paragraph 8 above), it fails to expressly disclose:
further comprising: forming a high dielectric constant material layer on the substrate; and forming a metal containing layer on the high dielectric constant material layer, wherein the gate material layer is disposed on the metal containing layer.
Shan discloses forming the amorphous silicon gate material for a gate replacement structure ([0027]).
Zhang discloses a method of forming a replacement gate further comprising: forming a high dielectric constant material layer (Fig. 2A; 204; [0037], page 21) on the substrate (200; [0037], page 20); and forming a metal containing layer (Fig. 2A; 205; [0037], page 25) on the high dielectric constant material layer (204), wherein the gate material layer (Fig. 2A; 207; [0037], page 21) is disposed on the metal containing layer (205).
A person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to use the dummy structure of Zhang, namely including a high dielectric constant layer on the substrate, a metal containing layer on the high dielectric constant layer, and forming the dummy gate material on the metal containing layer, in the replacement gate process of Shan combined with Yamazaki and Chang using amorphous silicon as the dummy gate material in order to provide a method that allows for a replacement gate to be formed without having residue formed in the dummy gate trench and the line edge roughness of the dummy gate material allows for improved performance of the final device ([0024] of Shan and [0012] of Zhang).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Shan in view of Yamazaki in view of Chang as applied to claim 1 above, and further in view of Chien et al (US 2022/0328631 and Chien hereinafter).
Shan combined with Yamazaki and Chang discloses further comprising: patterning the second hard mask (520), the first hard mask (510) and the gate material layer (500) to form a gate stack (Fig 16; gate stack comprises 550; [0152]-[0159]).
Shan in view of Yamazaki in view of Chang fails to expressly disclose forming a spacer surrounding the gate stack.
Chien discloses in Figs. 5A-5C that during forming a gate stack used in a replacement gate process, spacers 82 can be formed on the gate stack comprising 74.
Given the teachings of Chien, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Shan in view of Yamazaki in view of Chang by employing the well-known or conventional features of gate replacement fabrication, such as displayed by Chien, by employing a spacer around the dummy gate stack in order to prevent a short between the source/drain regions and the final gate structure ([0039]).
Response to Arguments
Applicant's arguments filed 5/7/2026 have been fully considered but they are not persuasive.
In the remarks, applicant argues in substance that:
Shan discloses that the first preset deposition temperature for forming the amorphous silicon material layer 500 is less than or equal to 510°C, or in the range of 400°C to 510°C, which implies that the phase transition temperature of the amorphous silicon material layer 500 is higher than 510°C. Therefore, the first preset deposition temperature disclosed by Shan is significantly lower than the phase transition temperature of the present application.
The present application pertains to an advanced semiconductor logic device process utilizing silicon wafer substrates, whereas Yamazaki relates to TFTs and LCDs, in which the substrate is a glass substrate or an insulating substrate. The requirements for substrate properties (silicon wafer vs. glass) and device performance (high-end logic operations vs. display switching) of the present application and Yamazaki are significantly different. Yamazaki focuses on promoting crystallization of amorphous silicon into crystalline silicon, whereas Shan aims to prevent amorphous silicon from transforming into polycrystalline silicon. A PHOSITA would have no reasonable motivation to combine Yamazaki with Shan.
The upper limit of the temperature range disclosed by Chang is as high as 650°C. If a temperature were randomly selected according to Chang’s teaching, such as 620°C, it would directly cause the amorphous silicon of the present application to transform into polycrystalline silicon. Furthermore, Chang fails to teach or suggest the technical motivation of maintaining the interface flatness of amorphous silicon to enhance electrical performance. Therefore, there is no motivation to control the process temperature for forming the silicon nitride to be less than 590°C.
Examiner respectfully traverses applicant’s remarks.
As to points a) and b), in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In response to applicant's argument that Yamazaki discloses forming a TFT with an amorphous silicon layer that is crystallized while Shan teaches a semiconductor device (not a TFT) with an amorphous silicon layer, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). While Shan (and the present invention) and Yamazaki are directed to different semiconductor products, they are both directed to the semiconductor technology field/devices and are relevant, related arts in that regard. While Shan discloses that the first preset deposition temperature is less than 510°C, a person having ordinary skill in the art before the effective filing date would know that the crystallization temperature of amorphous silicon depends upon the deposition method and film thickness, as taught in [0129] by Yamazaki. This is an objective fact about amorphous silicon that is not dependent upon what type of device it is used in. Therefore, while Shan teaches a layer of amorphous silicon through its deposition and thickness has a phase transition temperature lower than that of the claimed invention, Yamazaki discloses that not only can this phase transition change depending upon the method of forming the amorphous silicon and the film thickness also discloses that there is known an amorphous silicon layer with a phase transition temperature that overlaps with the instant/claimed invention. Further, as stated in MPEP 2144(I), “[t]he rationale to modify or combine the prior art does not have to be expressly stated in the prior art; the rationale may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law. In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988); In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992); see also In re Kotzab, 217 F.3d 1365, 1370, 55 USPQ2d 1313, 1317 (Fed. Cir. 2000) (setting forth test for implicit teachings); In re Eli Lilly & Co., 902 F.2d 943, 14 USPQ2d 1741 (Fed. Cir. 1990) (discussion of reliance on legal precedent); In re Nilssen, 851 F.2d 1401, 1403, 7 USPQ2d 1500, 1502 (Fed. Cir. 1988) (references do not have to explicitly suggest combining teachings); Ex parte Clapp, 227 USPQ 972 (Bd. Pat. App. & Inter. 1985) (examiner must present convincing line of reasoning supporting rejection); and Ex parte Levengood, 28 USPQ2d 1300 (Bd. Pat. App. & Inter. 1993) (reliance on logic and sound scientific reasoning).” Thus, there is a reason to combine Yamazaki with Shan given that Yamazaki is provided to show general knowledge about amorphous silicon materials in the semiconductor technology field.
As to point c), Chang discloses a range that overlaps with the claimed range. Chang discloses that it would have been well known to a person having ordinary skill in the art before the effective filing date would know that silicon nitride hardmasks can be formed using the same precursors as the instant/claimed invention with a temperature between 570°C -650°C. Therefore, while applicant argues that a temperature higher than that of the claimed invention could be randomly selected, so could a temperature within the claimed range. A person having ordinary skill in the art before the effective filing date of the claimed invention using only routine skill in the art in view of the teachings of Chang would have been able to choose a value that is within the claimed range and, as such, the claimed limitation/range is taught by the combination of the prior art. As state in MPEP 2144(IV), “[t]he reason or motivation to modify the reference may often suggest what the inventor has done, but for a different purpose or to solve a different problem. It is not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant. See, e.g., In re Kahn, 441 F.3d 977, 987, 78 USPQ2d 1329, 1336 (Fed. Cir. 2006) (motivation question arises in the context of the general problem confronting the inventor rather than the specific problem solved by the invention); Cross Med. Prods., Inc. v. Medtronic Sofamor Danek, Inc., 424 F.3d 1293, 1323, 76 USPQ2d 1662, 1685 (Fed. Cir. 2005) ("One of ordinary skill in the art need not see the identical problem addressed in a prior art reference to be motivated to apply its teachings."); In re Lintner, 458 F.2d 1013, 173 USPQ 560 (CCPA 1972) (discussed below); In re Dillon, 919 F.2d 688, 16 USPQ2d 1897 (Fed. Cir. 1990), cert. denied, 500 U.S. 904 (1991) (discussed below).” Further, as stated in MPEP 2144(I), “[t]he rationale to modify or combine the prior art does not have to be expressly stated in the prior art; the rationale may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law. In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988); In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992); see also In re Kotzab, 217 F.3d 1365, 1370, 55 USPQ2d 1313, 1317 (Fed. Cir. 2000) (setting forth test for implicit teachings); In re Eli Lilly & Co., 902 F.2d 943, 14 USPQ2d 1741 (Fed. Cir. 1990) (discussion of reliance on legal precedent); In re Nilssen, 851 F.2d 1401, 1403, 7 USPQ2d 1500, 1502 (Fed. Cir. 1988) (references do not have to explicitly suggest combining teachings); Ex parte Clapp, 227 USPQ 972 (Bd. Pat. App. & Inter. 1985) (examiner must present convincing line of reasoning supporting rejection); and Ex parte Levengood, 28 USPQ2d 1300 (Bd. Pat. App. & Inter. 1993) (reliance on logic and sound scientific reasoning).” Thus, there is a reason to combine Chang with Shan given that Chang is provided to show general knowledge about silicon nitride materials in the semiconductor technology field.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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