DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I (claims 1-10) in the reply filed on 12/10/2025 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shan (CN 113539957 and Shan hereinafter; a machine translation is used as an English language equivalent).
As to claims 1, 3, and 6: Shan discloses [claim 1] a method for fabricating a semiconductor device (Figs. 8, 15, and 16), comprising: forming a gate material layer (Fig. 8; 500; [0098]) on a substrate (400; [0098]), wherein the gate material layer (500) comprises an amorphous material (amorphous silicon; [0098]) having a phase transition temperature (crystallization temperature; [0098]), and the amorphous material (amorphous silicon) converts into a polycrystalline material (polycrystalline silicon; [0101]) at the phase transition temperature ([0098] and [0101]); forming a first hard mask (Fig. 8; 510; [0109]) on the gate material layer (500) at a first process temperature (inherently a process temperature is used in depositing the mask material 510; [0109]), wherein the first process temperature is less than the phase transition temperature (as the material 500 remains amorphous from its formation through etching of the mask materials 510 and 520, the first process temperature of the first hard mask 510 is below the crystallization temperature/phase transition temperature; [0114], [0120], [0122], and [0157]-[0163]); and forming a second hard mask (Fig. 8; 520; [0109]) on the first hard mask (510) at a second process temperature (inherently a process temperature is used in depositing the mask material 520; [0109]), wherein the second process temperature is less than the phase transition temperature (as the material 500 remains amorphous from its formation through etching of the mask materials 510 and 520, the second process temperature of the second hard mask 520 is below the crystallization temperature/phase transition temperature; [0114], [0120], [0122], and [0157]-[0163]); [claim 3] wherein the first hard mask (510) comprises a nitride (silicon nitride; [0111]); [claim 6] wherein the second hard mask (520) comprises an oxide (silicon oxide; [0113]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 4, and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Shan in view of Yamazaki et al (JP 3850461 and Yamazaki hereinafter; a machine translation is used as an English language equivalent) in view of Chang (US 2020/0090979 and Chang hereinafter).
As to claims 2, 4, and 5: Shan discloses [claim 2] wherein the amorphous material (500) comprises amorphous silicon (amorphous silicon; [0098]).
Shan fails to expressly disclose where [claim 2] the phase transition temperature is 590 0C to 610 0C; [claim 4] wherein the first process temperature is greater than or equal to 560 0C, and is less than 590 0C; [claim 5] wherein reactants for forming the first hard mask comprises hexachlorodisilane and ammonia.
Shan discloses that the first hard mask is silicon nitride and inherently teaches that the silicon nitride is formed below the phase transition temperature of amorphous silicon in order to keep the silicon material amorphous.
Yamazaki discloses in [0129] that amorphous silicon can have a crystallization temperature/phase transition temperature of about 600 0C to 650 0C and the temperature is dependent upon the method of forming the film and the film thickness.
Chang discloses in [0073] that a hardmask of silicon nitride can be formed using hexachlorodisilane and ammonia at a temperature of between 570 0C and 650 0C.
The disclosed phase transition temperature of amorphous silicon overlaps with the claimed range; and the disclosed film formation temperature for silicon nitride overlaps with the claimed range.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary skills to form the amorphous silicon using a method and to a desired thickness that allows for later layers to be formed at temperatures well known in the prior art using well known reactants such that the phase transition temperature of the formed amorphous silicon overlaps with the claimed range and the temperature of formation of the first hardmask of silicon nitride is below the phase transition temperature and within the claimed range in order to ensure that the silicon nitride formed is of good quality and prevents crystallization of the amorphous material of Shan as desired by Shan.
Claims 2, 7, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Shan in view of Yamazaki in view of Tran et al (US 2009/0035584 and Tran hereinafter).
As to claims 2, 7, and 8: Shan discloses [claim 2] wherein the amorphous material (500) comprises amorphous silicon (amorphous silicon; [0098]).
Shan fails to expressly disclose where [claim 2] the phase transition temperature is 590 0C to 610 0C; [claim 7] wherein the second process temperature is greater than or equal to 380 0C, and is less than or equal to 420 0C; [claim 8] wherein reactants for forming the second hard mask comprise silane and nitrous oxide.
Shan discloses that the second hard mask is silicon oxide and inherently teaches that the silicon oxide is formed below the phase transition temperature of amorphous silicon in order to keep the silicon material amorphous.
Yamazaki discloses in [0129] that amorphous silicon can have a crystallization temperature/phase transition temperature of about 600 0C to 650 0C and the temperature is dependent upon the method of forming the film and the film thickness.
Tran discloses in [0040] that a hard mask formed of silicon oxide can be formed using silane and nitrous oxide (N2O) at a temperature of less than about 400 0C.
The disclosed phase transition temperature of amorphous silicon overlaps with the claimed range; and the disclosed film formation temperature for silicon oxide overlaps with the claimed range.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary skills to form the amorphous silicon using a method and to a desired thickness that allows for later layers to be formed at temperatures well known in the prior art using well known reactants such that the phase transition temperature of the formed amorphous silicon overlaps with the claimed range and the temperature of formation of the second hardmask of silicon oxide is below the phase transition temperature and within the claimed range in order to ensure that the silicon oxide formed is of good quality and prevents crystallization of the amorphous material of Shan as desired by Shan.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Shan in view of Zhang et al (CN 104183477 and Zhang hereinafter; a machine translation is used as an English language equivalent).
Although the method disclosed by Shan shows substantial features of the claimed invention (discussed in paragraph 7 above), it fails to expressly disclose:
further comprising: forming a high dielectric constant material layer on the substrate; and forming a metal containing layer on the high dielectric constant material layer, wherein the gate material layer is disposed on the metal containing layer.
Shan discloses forming the amorphous silicon gate material for a gate replacement structure ([0027]).
Zhang discloses a method of forming a replacement gate further comprising: forming a high dielectric constant material layer (Fig. 2A; 204; [0037], page 21) on the substrate (200; [0037], page 20); and forming a metal containing layer (Fig. 2A; 205; [0037], page 25) on the high dielectric constant material layer (204), wherein the gate material layer (Fig. 2A; 207; [0037], page 21) is disposed on the metal containing layer (205).
A person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to use the dummy structure of Zhang, namely including a high dielectric constant layer on the substrate, a metal containing layer on the high dielectric constant layer, and forming the dummy gate material on the metal containing layer, in the replacement gate process of Shan using amorphous silicon as the dummy gate material in order to provide a method that allows for a replacement gate to be formed without having residue formed in the dummy gate trench and the line edge roughness of the dummy gate material allows for improved performance of the final device ([0024] of Shan and [0012] of Zhang).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Shan in view of Chien et al (US 2022/0328631 and Chien hereinafter).
Shan discloses further comprising: patterning the second hard mask (520), the first hard mask (510) and the gate material layer (500) to form a gate stack (Fig 16; gate stack comprises 550; [0152]-[0159]).
Shan fails to expressly disclose forming a spacer surrounding the gate stack.
Chien discloses in Figs. 5A-5C that during forming a gate stack used in a replacement gate process, spacers 82 can be formed on the gate stack comprising 74.
Given the teachings of Chien, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Shan by employing the well-known or conventional features of gate replacement fabrication, such as displayed by Chien, by employing a spacer around the dummy gate stack in order to prevent a short between the source/drain regions and the final gate structure ([0039]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
1/4/2026