Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s remarks/amendment of claims 1-9 and 11-24 in the reply filed on January 16th, 2025 are acknowledged. Claims 1 and 24 have been amended. Claims 10 and 25-39 have been withdrawn from consideration. Claims 1-39 are pending.
Action on merits of claims 1-9 and 11-24 follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 4, 6, 8-9, 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Aichi (US 2018/0122955, hereinafter as Aichi ‘955) in view of Chang (US 2005/0074914, hereinafter as Chang ‘914).
Regarding Claim 1, Aichi ‘955 teaches a thin film transistor substrate comprising:
a first thin film transistor (Fig. 5a, (101); [0081]) disposed on a base substrate; and
a second thin film transistor (Fig. 5a, (201); [0081]) spaced apart from the first thin film transistor, wherein the first thin film transistor comprises a first active layer (Fig. 5a, (31A); [0082]) and a first gate electrode (Fig. 5a, (7A); [0050]) that overlaps with at least a portion of the first active layer (31A/37), wherein the second thin film transistor comprises a second active layer (Fig. 5a, (31B/35); [0054]) and a second gate electrode (Fig. 5a, (7B); [0054]) that overlaps with at least a portion of the second active layer (31B/35), wherein the first active layer (31A/37) includes a first channel part (31A) overlapping with the first gate electrode (7A), and a first conductive part penetration region (37; [0082]) disposed at an end of the first channel part (31A), wherein the second active layer (31B/35) includes a second channel part (31B) overlapping with the second gate electrode (7B), and a second conductive part (35; [0083]) penetration region disposed at an end of the second channel part (31B), and wherein a length of the first conductive part penetration region (37) is longer than a length of the second conductive part penetration region (35).
Thus, Aichi ‘955 is shown to teach all the features of the claim with the exception of explicitly the features: “a length of the first channel part is shorter than a length of the second channel part”.
Chang ‘914 teaches a length of the first channel part (Fig. 1, (14a); [0031]) is shorter than a length of the second channel part (Fig. 1, (16a); [0034]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Aichi ‘955 by having a length of the first channel part is shorter than a length of the second channel part for the purpose of improving the electric performance of the TFT device (see para. [0047]) as suggested by Chang ‘914.
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Fig. 5 (Aichi ‘955)
Regarding Claim 4, Aichi ‘955 teaches the first active layer further includes a first conductive part (36; [0082]) formed at one side of the first conductive part penetration region (37) opposite to the first channel part (31A), and wherein the second active layer further includes a second conductive part (34; [0083]) formed at one side of the second conductive part penetration region (35) opposite to the second channel part (31B) (see Fig. 5).
Regarding Claim 6, Aichi ‘955 teaches the first conductive part (36) does not overlap with the first gate electrode (7A), and the second conductive part (34) does not overlap with the second gate electrode (7B) (see Fig. 5).
Regarding Claim 8, Aichi ‘955 teaches a gate insulating layer (5; [0069]) disposed between the first active layer (31A) and the first gate electrode (7A) and between the second active layer (31B) and the second gate electrode (7B) (see Fig. 5).
Regarding Claim 9, Aichi ‘955 teaches the gate insulating layer (5) includes a first gate insulating layer disposed between the first active layer (31A) and the first gate electrode (7A), and a second gate insulating layer disposed between the second active layer (31B) and the second gate electrode (7B) (see Fig. 5).
Regarding Claim 11, Aichi ‘955 teaches a first interlayer insulating layer (11) disposed on the first thin film transistor and the second thin film transistor (see Fig. 5).
Regarding Claim 17, Aichi ‘955 teaches the first active layer (31A) and the second active layer (31B) are formed on a same layer (see Fig. 5).
Claims 2-3, 5, 7, 12-16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Aichi ‘955 and Chang ‘914 as applied to claim 1 above, and further in view of Toyota (US 2008/0299693, hereinafter as Toyo ‘693).
Regarding Claim 2, Aichi ‘955 teaches the second conductive part penetration region (35) overlaps with the second gate electrode (7B) (see Fig. 5).
Thus, Aichi ‘955 and Chang ‘914 are shown to teach all the features of the claim with the exception of explicitly the features: “the first conductive part penetration region overlaps with the first gate electrode”.
Toyo ‘693 teaches the first conductive part penetration region overlaps with the first gate electrode (see Fig. 11B; [0174]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Aichi ‘955 and Chang ‘914 by having the first conductive part penetration region overlaps with the first gate electrode for the purpose of adjusting the threshold of the TFT device (see para. [0174]) as suggested by Toyo ‘693.
Regarding Claim 3, Aichi ‘955, Chang ‘914 and Toyo ‘693 are shown to teach all the features of the claim with the exception of explicitly the features: “an impurity concentration of the first conductive part penetration region is higher than an impurity concentration of the second conductive part penetration region”.
However, it has been held to be within the general skill of a worker in the art to select an impurity concentration of the first/second conductive part penetration region such that an impurity concentration of the first conductive part penetration region is higher than an impurity concentration of the second conductive part penetration region on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select an impurity concentration of the first conductive part penetration region is higher than an impurity concentration of the second conductive part penetration region in order to improve the performance of the TFT devices.
Regarding Claim 5, Aichi ‘955, Chang ‘914 and Toyo ‘693 are shown to teach all the features of the claim with the exception of explicitly the features: “an impurity concentration of the first conductive part is higher than an impurity concentration of the second conductive part”.
However, it has been held to be within the general skill of a worker in the art to select an impurity concentration of the first/second conductive part such that an impurity concentration of the first conductive part is higher than an impurity concentration of the second conductive part on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select an impurity concentration of the first conductive part is higher than an impurity concentration of the second conductive part in order to improve the performance of the TFT devices.
Regarding Claim 7, Aichi ‘955, Chang ‘914 and Toyo ‘693 are shown to teach all the features of the claim with the exception of explicitly the features: “an impurity concentration of the first conductive part penetration region increases in a direction from the end of the first channel part toward the first conductive part, and an impurity concentration of the second conductive part penetration region increases in a direction from the end of the second channel part toward the second conductive part”.
However, it has been held to be within the general skill of a worker in the art to select an impurity concentration of the first/second conductive part penetration region such that an impurity concentration of the first conductive part penetration region increases in a direction from the end of the first channel part toward the first conductive part, and an impurity concentration of the second conductive part penetration region increases in a direction from the end of the second channel part toward the second conductive part on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select an impurity concentration of the first conductive part penetration region is higher than an impurity concentration of the second conductive part penetration region in order to improve the performance of the TFT devices.
Regarding Claim 12, Aichi ‘955 teaches a portion of the gate insulating layer overlapping with the first thin film transistor is doped with impurities doped in the first active layer (see Fig. 6).
Product by process limitation:
The expression “is doped with impurities” is/are taken to be a product by process limitation and is given no patentable weight. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al., 218 USPQ 289, 292 (Fed. Cir. 1983); In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old and obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
Regarding Claim 13, Aichi ‘955 teaches a portion of the first interlayer insulating layer (11) overlapping with the first thin film transistor is not doped with impurities doped in the first active layer (see Fig. 11d).
Regarding Claim 14, Aichi ‘955, Chang ‘914 and Toyo ‘693 are shown to teach all the features of the claim with the exception of explicitly the features: “a portion of the first interlayer insulating layer overlapping with the second thin film transistor is doped with impurities doped in the second active layer”.
However, it has been held to be within the general skill of a worker in the art to have a portion of the first interlayer insulating layer overlapping with the second thin film transistor is doped with impurities doped in the second active layer on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have a portion of the first interlayer insulating layer overlapping with the second thin film transistor is doped with impurities doped in the second active layer in order to improve the performance of the TFT devices.
Product by process limitation:
The expression “is doped with impurities” is/are taken to be a product by process limitation and is given no patentable weight. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al., 218 USPQ 289, 292 (Fed. Cir. 1983); In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old and obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
Regarding Claim 15, Aichi ‘955, Chang ‘914 and Toyo ‘693 are shown to teach all the features of the claim with the exception of explicitly the features: “a highest value of a distribution of an impurity concentration along a vertical direction of a region overlapping with the first conductive part overlaps with at least partially with the first active layer, and a highest value of a distribution of an impurity concentration along a vertical direction of a region overlapping with the second conductive part does not overlap with the second active layer”.
However, it has been held to be within the general skill of a worker in the art to have a highest value of a distribution of an impurity concentration along a vertical direction of a region overlapping with the first conductive part overlaps with at least partially with the first active layer, and a highest value of a distribution of an impurity concentration along a vertical direction of a region overlapping with the second conductive part does not overlap with the second active layer on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have a highest value of a distribution of an impurity concentration along a vertical direction of a region overlapping with the first conductive part overlaps with at least partially with the first active layer, and a highest value of a distribution of an impurity concentration along a vertical direction of a region overlapping with the second conductive part does not overlap with the second active layer in order to improve the performance of the TFT devices.
Regarding Claim 16, Aichi ‘955 teaches a gate insulating layer (5) disposed between the first active layer (31A) and the first gate electrode (7A) and between the second active layer (31B) and the second gate electrode (7B), and a first interlayer insulating layer (11) disposed on the first thin film transistor and the second thin film transistor,
Aichi ‘955, Chang ‘914 and Toyo ‘693 are shown to teach all the features of the claim with the exception of explicitly the features: “an impurity concentration is distributed from the gate insulating layer to the first active layer along a vertical direction of a region overlapping with the first conductive part, with the highest value overlapping with at least partially with the first active layer, and an impurity concentration is distributed from the first interlayer insulating layer to the second active layer along a vertical direction of a region overlapping with the second conductive part, with the highest value overlapping with the gate insulating layer”.
However, it has been held to be within the general skill of a worker in the art to have an impurity concentration is distributed from the gate insulating layer to the first active layer along a vertical direction of a region overlapping with the first conductive part, with the highest value overlapping with at least partially with the first active layer, and an impurity concentration is distributed from the first interlayer insulating layer to the second active layer along a vertical direction of a region overlapping with the second conductive part, with the highest value overlapping with the gate insulating layer on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have an impurity concentration is distributed from the gate insulating layer to the first active layer along a vertical direction of a region overlapping with the first conductive part, with the highest value overlapping with at least partially with the first active layer, and an impurity concentration is distributed from the first interlayer insulating layer to the second active layer along a vertical direction of a region overlapping with the second conductive part, with the highest value overlapping with the gate insulating layer in order to improve the performance of the TFT devices
Regarding Claim 18, Toyo ‘693 teaches the first thin film transistor is a driving transistor for driving a display element of a pixel driving unit of a display apparatus (see Fig. 3A; para. [0058]).
Regarding Claim 19, Toyo ‘693 teaches the second thin film transistor constitutes a gate driver of a gate-in-panel circuit of a display apparatus (see Fig. 2).
Claims 20-24 are rejected under 35 U.S.C. 103 as being unpatentable over Aichi ‘955, Chang ‘914 as applied to claim 1 above, and further in view of Yamayaki (US 2002/0134979, hereinafter as Yama ‘979).
Regarding Claim 20, Aichi ‘955 and Chang ‘914 are shown to teach all the features of the claim with the exception of explicitly the features: “the second thin film transistor is a switching transistor of a pixel driving unit of a display apparatus”.
Yama ‘979 teaches the second thin film transistor is a switching transistor (Fig. 1, (201); [0037]) of a pixel driving unit of a display apparatus.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Aichi ‘955 and Chang ‘914 by having the second thin film transistor is a switching transistor of a pixel driving unit of a display apparatus in order to capable of displaying an image with high brightness (see para. [0010]).
Regarding Claim 21, Yama ‘979 teaches a plurality of pixels, each of which includes a display element and a pixel driving unit configured to drive the display element (see Fig. 2A).
Regarding Claim 22, Yama ‘979 teaches a driving transistor (202) configured to supply a current to the display element according to a data voltage, and a switching transistor (201) configured to supply the data voltage to a gate electrode of the driving transistor according to a scan signal, and wherein the first thin film transistor constitutes the driving transistor (see para. [0037]).
Regarding Claim 23, Yama ‘979 teaches the second thin film transistor (201) constitutes the switching transistor (see para. [0037]).
Regarding Claim 24, Toyo ‘693 teaches a gate driver of a gate-in-panel circuit for supplying the scan signal (see Fig. 2; para. [0023]-[0024]),
Yama ‘979 teaches the second thin film transistor constitutes the gate driver (see Fig. 20; [0291]).
Response to Arguments
Applicant’s arguments with respect to claims 1-9 and 11-24, filed on January 16th, 2026, have been considered but are moot in view of the new ground of rejection.
Interviews After Final
Applicants note that an interview after a final rejection is permitted in order to place the application in condition for allowance or to resolve issues prior to appeal. However, prior to the interview, the intended purpose and content of the interview should be presented briefly, preferably in writing. Upon review of the agenda, the Examiner may grant the interview if the examiner is convinced that disposal or clarification for appeal may be accomplished with only nominal further consideration. Interviews merely to restate arguments of record or to discuss new limitations will be denied. See MPEP § 714.13
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Dzung Tran whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Supervisor Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893