Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The examiner notes that foreign patent documents are relied upon in this action. All quotations, figure numbers, and paraphrasing of these documents refer to the translations thereof attached to this action.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun (WO 2020073857 A1) in view of Iketani (US 20200015364 A1).
Regarding claim 1, Sun teaches, in FIG. 7, an apparatus comprising a “printed circuit board” (see title, this is a package substrate), in which a plurality of layers (see “via anti-pads” 1, 2, 3, S1 and S2, which indicates the existence of pads, or “layers”) and a plurality of voids (the anti-pads themselves), wherein the package substrate comprises a first layer (layer of anti-pad S3) having a first void (anti-pad 1), the first void having a first radius, a second layer (layer of anti-pad 2) having a second void (anti-pad 3), the second layer over the first layer (see FIG. 7), the second void having a second radius smaller than the first radius, third layer (layer of anti-pad S2) having a third void (anti-pad 1), the third layer over the second layer (see FIG. 7), the third void having a third radius larger than the second radius (see FIG. 7) and a via within (see abstract, FIG. 7, unlabeled), and extending through at least one of, the first, second, and third voids (see FIG. 7).
Sun does not explicitly teach that the via and pads are metal, and does not teach that the substrate is under a die.
Iketani teaches, in FIG. 3, a “via structure” 330 into which a “conductive material such as conductive metal, or copper, is deposited” (paragraph 0057). Further, “conducting layers” 310a-310e (metal is a conductor, see above, therefore these may be metal pads) having voids (anti-pads, see FIG. 3) through which the metal via extends. Iketani also teaches, in paragraph 0051 “A multilayer PCB [like the multilayer PCB taught by Sun] can be a chip substrate, a motherboard, a backplane, a backpanel.” The examiner notes that “chip substrate” and “backplane” both indicate that a chip (IC die) can be implemented on top of the PCB structure. The examiner notes that this constitutes an IC package.
It would have been obvious to one having ordinary skill in the art at the effective filing date to use metal in the pads and vias taught by Sun, as taught by Iketani. One having ordinary skill in the art is motivated to do so because metals are excellent conductors, useful for interconnections, as is very well known in the art. Also see that Iketani acknowledges metals as “conductive.” See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007). One having ordinary skill in the art is also motivated to use this structure as a holder for an IC die because “A via structure [described structure] can be a plated through-hole used for transmitting electrical signals from one conducting layer to another,” (Iketani, paragraph 0051) allowing an IC die to transmit outputs to other components.
Regarding claim 2, Sun further teaches, in FIG. 1, a first connection to the via (unlabeled, see connection structure at the top of the via) which is in or under the first layer and a second connection to the via (unlabeled, see connection structure at the bottom of the via) that is in or over the third layer. Also see annotated FIG. 1 below.
Regarding claim 3, Sun further teaches, in FIG. 1, that the via comprises a first pad at the first connection or a second pad at the second connection . Also see unlabeled pad at second connection point A of FIG. 5.
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Regarding claim 4, although Sun does not explicitly teach that the first radius is substantially equal to the third diameter, Sun does teach, in FIG. 7, a void profile around the via that has a first and second slope which meet at a midpoint (anti-via 2). Applicant has not disclosed that the first radius being substantially equal to the third radius provides an advantage, is used for a particular purpose, or solves a stated problem other than the function of the overall anti-via profile (which does not require the first radius to be substantially equal to the third radius).
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the void radii of Sun such that the first void radius is substantially equal to the third void radius. This is because one of ordinary skill in the art would have expected this design variation to be one of several straightforward ways of forming the via structure taught by Sun. See present specification paragraphs 0116 and 0118. Also see In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). Also see MPEP 2144.04.
Regarding claim 5, Sun further teaches, in FIG. 7, a fourth “anti-pad” (void) 3 at a via in a fourth layer which has a fourth radius, the fourth layer is between the first and third layers, the first and third radii are greater than the fourth radius, and the fourth radius is greater than the second radius.
As stated above, Sun does not explicitly teach that this layer is metal, but Iketani teaches metal layers.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the apparatus taught by Sun such that the fourth layer is metal, for the reasons stated above.
Regarding claim 6, Sun further teaches, in FIG. 7, a fifth “anti-pad” (void) 5 which has a fourth radius, the fifth layer is between the first and third layers, the second layer is between the fourth and fifth layers, the first and third radii are greater than the fifth radius, and the fifth radius is greater than the second radius.
As stated above, Sun does not explicitly teach that this layer is metal, but Iketani teaches metal layers.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the apparatus taught by Sun such that the fifth layer is metal, for the reasons stated above.
Regarding claim 7, Sun further teaches, in FIG. 7 a void profile around the via has a first slope adjacent an end of the via; the void profile has a second slope adjacent a midpoint of the via; and the second slope is greater than the first slope. Note that the right direction may be considered a “+x” direction, which, in combination with the +z direction defined by FIG. 7, can be used to calculate slope.
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Regarding claim 8, Sun further teaches, in FIG. 7, that the plurality of layers comprises at least one pair of the layers above or below a midpoint of the via; each such pair comprises a distal layer (ex, layer S2 or S3) further from the midpoint and an intervening layer nearer to the midpoint (ex, layer 1 or 3, respectively); and the distal layer comprises a distal void having a radius greater than a radius of an intervening void in the intervening layer.
Regarding claim 9, Sun further teaches, in FIG. 2, a second via (unlabeled, also a first via), and a void at the second via overlaps an individual one of the voids at the first via.
Sun does not explicitly teach that this via is metal, but Iketani teaches metal vias.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the apparatus taught by Sun such that the fourth metal layer is metal, for the reasons stated above.
Regarding claim 10, Sun further teaches, in FIGs. 5 and 6, a first via structure (one of the center two vias in FIG. 5, the via of FIG. 6) and a second via structure (one of the peripheral via structures of FIG. 5, also see FIGs. 1 and 2 for similar structures) with first and second pluralities of voids (the second plurality of voids in the top two layers of FIG. 5, also see FIGs. 1 and 2), in which the second plurality of voids are substantially equal in radii.
Sun does not explicitly teach that the first via is beneath the IC die. As shown above, Iketani teaches a multilayered PCB for use as an IC chip substrate.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the substrate taught by Sun such that a second metal via with a plurality of voids with substantially equal radii, as further taught by Sun, and such that the first metal via is beneath the IC die, as taught by Iketani. One having ordinary skill in the art is motivated to form the second metal via under the IC chip in order to utilize the via as an output interconnect, as taught by Iketani above.
Claim(s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun (WO 2020073857 A1) in view of Yang (US 20210320085 A1).
Regarding claim 11, Sun teaches in FIG. 7, an apparatus comprising a “printed circuit board” (second substrate), in which a plurality of layers (see “via anti-pads” 1, 2, 3, S1 and S2, which indicates the existence of pads, or “layers”) and a stack of “anti-pads”, wherein the apparatus comprises a via (unlabeled, see FIG. 7) extending through the anti-pads, a first layer (layer of anti-pad S3) in which is a first anti-pad 1, the anti-pad having a first diameter, a second layer (layer of anti-pad 2) having a second anti-pad 3, the second layer over the first layer (see FIG. 7), the second anti-pad having a second diameter smaller than the first diameter (the first diameter is greater than the second diameter), a third layer (layer of anti-pad S2) in which is a third anti-pad 1, the third layer over the second layer (see FIG. 7), the third anti-pad having a third diameter larger than the second diameter (see FIG. 7).
Sun does not teach a first substrate through which a power supply is routed, or an IC die.
Yang teaches, in paragraph 0032 a “semiconductor package” 100 which includes a “second substrate” (first substrate) 120 which is can be connected a “first substrate” (second substrate) and subsequently to a “power source” (paragraph 0032). FIG. 1 also shows these substrates coupled via solders balls 170 to a “semiconductor die” (IC die) 130.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device taught by Sun such that the IC package has both a first and second substrate, and that the IC is coupled to a power supply through the first substrate, as taught by Yang. One having ordinary skill in the art is motivated to do so in order to, for example, “a dual-die package including the first semiconductor die 130 and the second semiconductor die 140 can be functionalized due to such a configuration of the electrical connections” (Yang, paragraph 0032, the examiner notes that a dual-die package is advantageous due to additional computational/storage power being enabled).
Regarding claim 12, Sun further teaches, in FIG. 1, a first connection to the via (unlabeled, see connection pad at the top of the via) which is in or under the first layer and a second connection to the metal via is in or over the third metal layer (unlabeled, see connection pad at the bottom of the via). Also see annotated FIG. 1 above. FIG. 5 also shows that a second anti-pad 2 is equal to or greater in diameter than a first pad (at the top of the via of claim 5).
Applicant has not disclosed that the first radius being substantially equal to the third radius provides an advantage, is used for a particular purpose, or solves a stated problem other than the function of the overall anti-via profile (which does not require the first radius to be substantially equal to the third radius).
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the pad diameter and second anti-pad diameter of Sun such that the second diameter is equal to or greater than a diameter of the first or second pad. This is because one of ordinary skill in the art would have expected this design variation to be one of several straightforward ways of forming the via and pad structure taught by Sun. See present specification paragraphs 0115. Also see In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). Also see MPEP 2144.04.
Regarding claim 13, Regarding claim 4, although Sun does not explicitly teach that the first diameter is substantially equal to the third diameter, Sun does teach, in FIG. 7, an anti-pad profile around the via that has a first and second slope which meet at a midpoint (anti-via 2). Applicant has not disclosed that the first diameter being substantially equal to the diameter radius provides an advantage, is used for a particular purpose, or solves a stated problem other than the function of the overall anti-via profile (which does not require the first diameter to be substantially equal to the third diameter).
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the anti-pad diameters of Sun such that the first anti-pad diameter is substantially equal to the third anti-pad diameter. This is because one of ordinary skill in the art would have expected this design variation to be one of several straightforward ways of forming the via structure taught by Sun. See present specification paragraphs 0072 and 0114. Also see In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). Also see MPEP 2144.04.
Regarding claim 14, Sun further teaches, in FIG. 7, Sun further teaches, in FIG. 7, a fourth anti-pad 3 at a metal via in a fourth layer which has a fourth radius, the fourth layer is between the first and third layers, the first and third diameters are greater than the fourth diameter, and the fourth diameter is greater than the second diameter, a fifth anti-pad 5 which has a fourth diameter, the fifth layer is between the first and third metal layers, the second layer is between the fourth and fifth layers, the first and third diameters are greater than the fifth diameter, and the fifth diameter is greater than the second diameter.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun (WO 2020073857 A1).
Regarding claim 15, Sun teaches in FIG. 7, an apparatus comprising a “printed circuit board” (substrate), in which a plurality of layers (see “via anti-pads” 1, 2, 3, S1 and S2, which indicates the existence of pads, or “layers”) and a plurality of “anti-pads”, wherein the apparatus comprises a via (unlabeled, see FIG. 7) extending through the following antipads: a first layer (layer of anti-pad S3) in which is a first anti-pad 1, the anti-pad having a first diameter, a second layer (layer of anti-pad 2) having a second anti-pad 3, the second layer over the first layer (see FIG. 7), the second anti-pad having a second diameter smaller than the first diameter (the first diameter is greater than the second diameter), a third layer (layer of anti-pad S2) in which is a third anti-pad 1, where the second layer is between the first and third layers (see FIG. 7). Although Sun does not explicitly teach that the first diameter is substantially equal to the third diameter, Sun does teach, in FIG. 7, an anti-pad profile around the via that has a first and second slope which meet at a midpoint (anti-via 2).
Sun does not explicitly teach that the pads are made of conductors.
Iketani teaches, in FIG. 3, “conducting layers” 310a-310e having anti-pads, (see FIG. 3) through which the metal via extends.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the pads taught by Sun such that they are made of conductors. One having ordinary skill in the art is motivated to do so because they are “used for transmitting electrical signals from one conducting layer to another,” (Iketani, paragraph 0051).” Applicant has not disclosed that the first diameter being substantially equal to the diameter radius provides an advantage, is used for a particular purpose, or solves a stated problem other than the function of the overall anti-via profile (which does not require the first diameter to be substantially equal to the third diameter).
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the anti-pad diameters of Sun such that the first anti-pad diameter is substantially equal to the third anti-pad diameter. This is because one of ordinary skill in the art would have expected this design variation to be one of several straightforward ways of forming the via structure taught by Sun. See present specification paragraphs 0072 and 0114. Also see In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). Also see MPEP 2144.04. The examiner notes that the above described structure necessitates the method of claim 15 (it cannot be formed by a separate process), and therefore the method of claim 15 is obvious over the above described structure.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun (WO 2020073857 A1) in view of Iketani (US 20200015364 A1).
Regarding claim 16, as explained above, Sun teaches the limitations of claim 15. Sun does not explicitly teach the coupling of an IC die to the substrate.
Iketani teaches in paragraph 0051, “A multilayer PCB [like the multilayer PCB taught by Sun] can be a chip substrate, a motherboard, a backplane, a backpanel” The examiner notes that “chip substrate” and “backplane” both indicate that a chip (IC die) can be implemented on top of the PCB structure. The examiner notes that this constitutes an IC package.
It would have been obvious to one having ordinary skill in the art at the effective filing date to couple an IC die to the substrate. One having ordinary skill in the art is also motivated to use this structure as a holder for an IC die because “A via structure [described structure] can be a plated through-hole used for transmitting electrical signals from one conducting layer to another,” (Iketani, paragraph 0051) allowing an IC die to transmit outputs to other components. The examiner notes that the above described structure necessitates the method of claim 16 it cannot be formed by a separate process), and therefore the method of claim 16 is obvious over the above described structure.
Regarding claim 17, Iketani teaches that the “multilayer PCB” may be a “chip substrate” and “backpanel.” The examiner notes that the substrate being a “backpanel” means that the IC die is coupled over the substrate. Additionally, “A via structure can be a plated through-hole used for transmitting electrical signals from one conducting layer to another” (Iketani paragraph 0051).
It would have been obvious to one having ordinary skill in the art at the effective filing date to couple the IC die over the via, as taught by Iketani. One having ordinary skill in the art is motivated to do so in order to, for example, achieve the functionality of sending signals between layers as taught by Iketani above. The examiner notes that the above described structure necessitates the method of claim 18 (it cannot be formed by a separate process), and therefore the method of claim 18 is obvious over the above described structure.
Regarding claim 18 Sun further teaches, in FIG. 1, a first connection to the via (unlabeled, see connection structure at the top of the via) which is in or under the first layer and a second connection to the via (unlabeled, see connection structure at the bottom of the via) that is in or over the third layer. Also see annotated FIG. 1 below.
The examiner notes that the above described structure necessitates the method of claim 18 (it
cannot be formed by a separate process), and therefore the method of claim 18 is obvious over the above described structure.
Regarding claim 19, Sun further teaches, in FIG. 7, a fourth “anti-pad” (void) 3 at a via in a fourth layer which has a fourth radius, the fourth layer is between the first and third layers, the first and third radii are greater than the fourth radius, and the fourth radius is greater than the second radius.
As stated above, Sun does not explicitly teach that this layer is a conductor, but Iketani teaches conductive layers.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the apparatus taught by Sun such that the fourth layer is a conductor, for the reasons stated above. The examiner notes that the above described structure necessitates the method of claim 19 (it cannot be formed by a separate process), and therefore the method of claim 19 is obvious over the above described structure.
Regarding claim 20, Sun further teaches, in FIG. 7, a fifth “anti-pad” (void) 5 which has a fourth radius, the fifth layer is between the first and third layers, the second layer is between the fourth and fifth layers, the first and third radii are greater than the fifth radius, and the fifth radius is greater than the second radius.
As stated above, Sun does not explicitly teach that this layer is a conductor, but Iketani teaches conductive layers.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the apparatus taught by Sun such that the fifth layer is a conductor, for the reasons stated above. The examiner notes that the above described structure necessitates the method of claim 20 (it cannot be formed by a separate process), and therefore the method of claim 20 is obvious over the above described structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:Rengarajan (US 20140182891 A1) – FIG. 1 shows a plurality of stacked “conductive ground layers” 1661-g, with voids (filled by “dielectric region 126”) which are of varying radii/diameters.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights