CTNF 18/202,046 CTNF 81034 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections Claims 11, 12, 17, 18 and 19 are objected to because of the following informalities: In claim 11, line 4, substitute “an” with -- the first -- before “RDL.” In claim 12, line 4, substitute “an” with -- the first -- before “RDL.” In claim 12, line 8, substitute “glass” with -- substrate -- before “core layer.” In claim 17, line 3, substitute “third” with -- first -- before “glass sub-layer.” In claim 17, line 5, substitute “the” with -- a -- before “first layer.” In claim 18, line 4, substitute “the” with -- a -- before “first layer.” Claim 19 depends form claim 18, so it is objected for the same reason. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-3 and 5-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Juang et al. (US Pub. 2023/0411171; hereinafter “Juang”) . Regarding Claim 1 , Juang discloses an electronic device, comprising: an electronic package substrate 12 including: a glass core layer 101 (page 5, paragraph 49) having a first surface (top surface) and a second surface (bottom surface) (see fig. 17); multiple channels 103 (page 1, paragraph 11) within the glass core layer 101 between the first surface and the second surface (see fig. 17) (through-glass vias DVa, DVb, DVc are necessarily formed by first creating through-holes or channels in the glass core layer 101, such as the deep openings 103 as shown in Figure 1, which are subsequently filled with conductive material to form the through-glass vias); and a first redistribution layer (RDL) 108 (page 2, paragraph 24) including multiple sub-layers of conductive traces (MF11, MF12, MF13, MF14) formed in an organic material (PM11, PM12, PM 13, PM 14) (page 2, paragraphs 21-24; see fig. 17), wherein a first surface (bottom surface) of the RDL 108 contacts the first surface (top surface) of the glass core layer 101 (see fig. 17). Regarding Claim 2 , Juang discloses wherein the glass core layer 101 includes multiple glass sub-layers (101a, 101b, 101c) bonded together (page 5, paragraph 49; see fig. 17). Regarding Claim 3 , Juang discloses wherein the glass core layer 101 includes multiple rows of channels 103 (the openings 103 in which through-glass vias DVa, DVc are formed) in the glass core layer (see fig. 17). Regarding Claim 5 , Juang discloses including: a second RDL 112 (page 3, paragraph 29) contacting the second surface (bottom surface) of the glass core layer 101 (see fig. 17); and wherein the multiple rows of channels 103 include a first row (top row) of channels 103 arranged closer to the first RDL 108 than the second RDL 112 and a second row (bottom row) of channels 103 arranged closer to the second RDL 112 than the first RDL 108 (see fig. 17). Regarding Claim 6 , Juang discloses wherein the glass core layer 101 includes at least one through glass via (TGV) DVb arranged between two channels 103 of the multiple channels 103 (the TGV DVb is arranged between two channels 103 where TGV DVa and TGV DVc are formed; see fig. 17). Regarding Claim 7 , Juang discloses including: a second RDL 112 (page 3, paragraph 29) including multiple sublayers of conductive traces (MF21, MF22, MF23) formed in an organic material (PM21, PM 22, PM23) (page 3, paragraphs 30-33), wherein a first surface (top surface) of the second RDL 112 contacts the second surface (bottom surface) of the glass core layer 101 (see fig. 17); and wherein the at least one TGV DVb provides electrical continuity between a conductive trace MF11 of the first RDL 108 and a conductive trace MF21 of the second RDL 112 (see fig. 17) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Juang . Regarding Claim 4 , Juang discloses wherein the multiple rows of channels 103 include a first row (top row) of channels 103 having a first width (see fig. 17), and a second row (bottom row) of channels 103 having a second width (see fig. 17). Juang fails to disclose explicitly wherein the second width is different from the first width. The instant claim merely requires that the first width be different from the second width without specifying any particular dimensions, range of dimensions, or relationship between the widths, and the specification does not disclose any unexpected results associated with the claimed difference in widths. Accordingly, absent of evidence of criticality or unexpected results associated with the claimed difference in widths, selecting different channel widths for different rows would have amounted to nothing more than routine optimization of a known design parameter. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to routinely select different widths for different rows of channels to accommodate particular design considerations, such as manufacturing tolerances, routing constrains, mechanical strength, or electrical interconnection requirements . 07-21-aia AIA Claim s 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over Juang in view of Kamgaing (US Pub. 2022/0394849) . Regarding Claims 8 and 9 , Juang fails to disclose explicitly [Re claim 8] wherein a cross section of a channel of the multiple channels has one of a square shape or a rectangular shape; and [Re claim 9] wherein at least one surface of a channel of the multiple channels is a curved surface. However, Kamgaing discloses a plurality of circular vias 217 (page 3, paragraph 48; see fig. 2A), or a plurality of rectangular vias 217 (page 3, paragraph 49; see fig. 2B) formed in a glass core layer 205 (page 2, paragraphs 37 and 42). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a plurality of vias having predetermined shapes in a glass core layer, as taught by Kamgaing in order to enhance structural reliability while providing efficient electrical interconnection through the glass core layer. Regarding Claim 10 , Juang discloses an electronic system, comprising: an electronic package substrate 12 including: a substrate core layer 101 (page 5, paragraph 49) including multiple channels 103 (page 1, paragraph 11) within the substrate core layer 101 between a first surface (top surface) of the substrate core layer 101 and a second surface (bottom surface) of the substrate core layer 101 (through-glass vias DVa, DVb, DVc are necessarily formed by first creating through-holes or channels in the glass core layer 101, such as the deep openings 103 as shown in Figure 1, which are subsequently filled with conductive material to form the through-glass vias); at least one integrated circuit (IC) (D21, D22, D23) (semiconductor dies; page 4, paragraph 41) mounted on the electronic package substrate 12 (see fig. 17). Juang fails to disclose explicitly wherein a manifold coupled to the electronic package substrate and configured to provide fluid to the channels. However, Kamgaing discloses wherein via holes 115, which are formed in a glass core layer 105 may remain unfilled in order to provide features such as liquid cooling channels (e.g., to function as a fluidic pathway) (page 2, paragraph 39; page 3, paragraph 45; see fig. 1C). Further, to provide liquid cooling through the channels, the electronic package substrate must be coupled to a fluid distribution system, such as a manifold, piping network, reservoir, or chamber, to supply coolant to and circulate coolant through the liquid cooling channels. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a liquid cooling channel coupled to a manifold to provide fluid to the channel, as taught by Kamgaing, in order to supply and circulate coolant through the electronic package substrate for removing heat generated by the electronic components, thereby improving thermal management, enhancing heat dissipation, and increasing the reliability and performance of the electronic package. Regarding Claim 11 , Juang in view of Kamgaing discloses wherein the substrate core layer 101 is a glass core layer (page 5, paragraph 49), and the electronic package substrate 12 includes: a first redistribution layer (RDL) 108 (page 2, paragraph 24) arranged between the first surface (top surface) of the glass core layer 101 and the IC (D21, D22, D23) (see fig. 17), wherein the first RDL 108 includes multiple sub-layers of conductive traces (MF11, MF12, MF13, MF14) formed in an organic material (PM11, PM12, PM 13, PM 14) (page 2, paragraphs 21-24; see fig. 17); and a through glass via (TGV) (DVa, DVb, DVc) arranged in the glass core layer 101 (page 5, paragraph 49) adjacent to a first channel of the multiple channels (the liquid cooling channel in Kamgaing), wherein the first RDL 108 provides electrical continuity between the TGV (DVa, DVb, DVc) and the IC (D21, D22, D23) (see fig. 17). Regarding Claim 12 , Juang discloses wherein the electronic package substrate includes: a first redistribution layer (RDL) 108 (page 2, paragraph 24) arranged between the first surface (top surface) of the substrate core layer 101 and the IC (D21, D22, D23) (see fig. 17), wherein the first RDL 108 includes multiple sublayers of conductive traces (MF11, MF12, MF13, MF14) formed in an organic material (PM11, PM12, PM 13, PM 14) (page 2, paragraphs 21-24; see fig. 17); a second RDL 112 (page 3, paragraph 29) arranged on the second surface (bottom surface) of the substrate core layer 101 (see fig. 17); and wherein the substrate core layer 101 includes multiple rows of channels 103 (the openings 103 in which through-glass vias DVa, DVc are formed), including a first row (top row) of channels 103 closer to the first RDL 108 than the second RDL 112 and a second row (bottom row) of channels 103 closer to the second RDL 112 than the first RDL 108 (see fig. 17). Regarding Claim 13 , Juang discloses wherein the first row (top row) of channels 103 has a first width (see fig. 17), and the second row (bottom row) of channels 103 has a second width (see fig. 17). Juang fails to disclose explicitly wherein the second width is different from the first width. The instant claim merely requires that the first width be different from the second width without specifying any particular dimensions, range of dimensions, or relationship between the widths, and the specification does not disclose any unexpected results associated with the claimed difference in widths. Accordingly, absent of evidence of criticality or unexpected results associated with the claimed difference in widths, selecting different channel widths for different rows would have amounted to nothing more than routine optimization of a known design parameter. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to routinely select different widths for different rows of channels to accommodate particular design considerations, such as manufacturing tolerances, routing constrains, mechanical strength, or electrical interconnection requirements. Regarding Claim 14 , Juang in view of Kamgaing discloses wherein the electronic package substrate 12 includes: a through via (DVa, DVb, DVc) arranged in the substrate core layer 101 adjacent to a first channel of the multiple channels (the liquid cooling channel in Kamgaing). Juang fails to disclose explicitly a printed circuit board (PCB); and wherein the second RDL provides electrical continuity between the through via and the PCB. However, Kamgaing discloses wherein a printed circuit board (PCB) 991 is coupled to a package substrate 901 by interconnects 992 (page 6, paragraph 83; see fig. 9). The PCB 991 in Kamgaing may be connected to the package substrate 12 in Juang via interconnects B2 (see fig. 17), whereby the second RDL 112 in Juang provides electrical continuity between the through via (DVa, DVb, DVc) and the PCB. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to connect a PCB to package substrate, as taught by Kamgaing, in order to provide electrical interconnection for signal and power routing between the PCB and the package substrate in a packaged electronic system. Allowable Subject Matter Claims 15, 16 and 20 are allowed, and claims 17-19 will be allowed after correcting the objections set forth above. The following is an examiner’s statement of reasons for allowance: Claim 15 recites forming multiple trenches in a first substrate sub-layer, wherein the multiple trenches are formed in a first surface of the first substrate sub-layer; bonding a second substrate sub-layer to the first surface of the first substrate sub-layer to cover the multiple trenches to form a substrate core layer having multiple channels within the substrate core layer. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record. Claims 16-20 depend from claim 15, so they are allowed or will be allowed for the same reason. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHEUNG LEE/Primary Examiner, Art Unit 2812 July 1, 2026 Application/Control Number: 18/202,046 Page 2 Art Unit: 2812 Application/Control Number: 18/202,046 Page 3 Art Unit: 2812 Application/Control Number: 18/202,046 Page 4 Art Unit: 2812 Application/Control Number: 18/202,046 Page 5 Art Unit: 2812 Application/Control Number: 18/202,046 Page 6 Art Unit: 2812 Application/Control Number: 18/202,046 Page 7 Art Unit: 2812 Application/Control Number: 18/202,046 Page 8 Art Unit: 2812 Application/Control Number: 18/202,046 Page 9 Art Unit: 2812 Application/Control Number: 18/202,046 Page 10 Art Unit: 2812 Application/Control Number: 18/202,046 Page 11 Art Unit: 2812 Application/Control Number: 18/202,046 Page 12 Art Unit: 2812
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