Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 (and dependent claims 18-20 dependent therefrom) is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitation “the sidewall portion of the second sub-gate electrode” in line14-15. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 17 is interpreted in the instant Office action as follows: “the sidewall portion of the second sub-gate electrode” is equivalent to “a sidewall portion of the second sub-gate electrode”. This interpretation is to be confirmed by applicant in the next office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, 10-16, and 21 are rejected under 35 U.S.C. 102(a)(1)as being anticipated by Ryu (US 20190259839 A1).
Regarding claim 1, Ryu discloses an integrated circuit (IC) device (Fig. 30) comprising:
a gate trench (105) inside a substrate (101), the gate trench including a bottom portion (See annotated figure) and a sidewall portion (See annotated figure);
a gate electrode structure (a collection of 108, 710, and 111) disposed apart from the bottom portion and the sidewall portion of the gate trench (apart by intervening 106), the gate electrode structure including a gate electrode (a collection of 108 and 710) and a gate capping layer (111), the gate electrode including a first sub-gate electrode (108) in a lower portion of the gate trench (See annotated figure for direction designation) and a second sub-gate electrode (710) on the first sub-gate electrode (directly on), the gate capping layer being on the second sub-gate electrode (directly on); and
a gate insulating layer (a collection of 106 and 309′) between (horizontally and vertically sandwiched between) the gate trench and the gate electrode structure, the gate insulating layer including a base insulating layer (106) and a reinforcing insulating layer (309′), the base insulating layer being between the bottom portion and the sidewall portion of the gate trench and the gate electrode structure (horizontally and vertically sandwiched between), and the reinforcing insulating layer being on and in direct contact with a sidewall portion of the second sub-gate electrode (See annotated figure for designated sidewall portion).
Illustrated below is a marked and annotated figure of Fig. 30 of Ryu.
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Regarding claim 2, Ryu discloses the IC device of claim 1 (Fig. 30), wherein the first sub-gate electrode includes a metal layer ([0067]: “metal-based materials”), the second sub-gate electrode includes a polysilicon layer doped with impurities ([0290]: “polysilicon doped with an N-type impurity”), and the reinforcing insulating layer includes a silicon oxide layer ([0315]: “The DICS may include lanthanum atoms” in combination with [0186]: “a lanthanum-diffused silicon oxide”).
Regarding claim 3, Ryu discloses the IC device of claim 1 (Fig. 30), wherein the reinforcing insulating layer further includes an upper surface reinforcing insulating layer (See annotated figure for a designated portion of 309′) on an upper surface portion of the second sub-gate electrode (horizontally on).
Regarding claim 4, Ryu discloses the IC device of claim 3 (Fig. 30), wherein the reinforcing insulating layer further includes a lower surface reinforcing insulating layer (See annotated figure for a designated portion of 309′) on a lower surface portion of the second sub-gate electrode (horizontally on).
Regarding clam 7, Ryu discloses the IC device of claim 1 (Fig. 30), wherein a second width (W4) at a middle level of the second sub-gate electrode is greater (“greater” in the horizontal direction because of overhanging portions) than a first width (1st Width, See annotated figure) at a middle level of the first sub-gate electrode.
Regarding claim 21, Ryu discloses the IC device of claim 1 (Fig. 30), wherein the reinforcing insulating layer is disposed between (“between” because 309′ is at a vertical height in between the heights of 111 and 108) the gate capping layer and the first sub-gate electrode in a vertical direction (See annotated figure for direction designation).
Note that claim 1 was previously address above, however, it’s being addressed differently here based on the reading of the reference, particularly to the selected embodiment of Ryu in order to address the dependent claim 10.
Regarding claim 1, Ryu discloses an integrated circuit (IC) device (Fig. 8B) comprising:
a gate trench (105) inside a substrate (101), the gate trench including a bottom portion (See annotated figure) and a sidewall portion (See annotated figure);
a gate electrode structure (a collection of 210, 220, and 111) disposed apart from the bottom portion and the sidewall portion of the gate trench (apart by intervening 106), the gate electrode structure including a gate electrode (a collection of 210 and 220) and a gate capping layer (111), the gate electrode including a first sub-gate electrode (210) in a lower portion of the gate trench (See annotated figure for direction designation) and a second sub-gate electrode (220) on the first sub-gate electrode (indirectly on), the gate capping layer being on the second sub-gate electrode (directly on); and
a gate insulating layer (a collection of 106 and 109) between (horizontally and vertically sandwiched between) the gate trench and the gate electrode structure, the gate insulating layer including a base insulating layer (106) and a reinforcing insulating layer (109), the base insulating layer being between the bottom portion and the sidewall portion of the gate trench and the gate electrode structure (horizontally and vertically sandwiched between), and the reinforcing insulating layer being on and in direct contact with a sidewall portion of the second sub-gate electrode (See annotated figure for designated sidewall portion).
Illustrated below is a marked and annotated figure of Fig. 8B of Ryu.
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Regarding claim 10, Ryu discloses the IC device of claim 1 (Fig. 8B), wherein a thickness of an upper sidewall of the reinforcing insulating layer (vertical thickness A, See annotated figure for measurement endpoints) on an upper sidewall portion of the second sub-gate electrode (directly on) is greater (“greater” because it vertically extends beyond thickness B) than a thickness of a lower sidewall of the reinforcing insulating layer (vertical thickness B, See annotated figure for measurement endpoints) on a lower sidewall portion of the second sub-gate electrode.
Regarding independent claim 11, Ryu discloses an integrated circuit (IC) device (Fig. 30) comprising:
a gate trench (105) inside a substrate (101), the gate trench including a bottom portion (See annotated figure) and a sidewall portion (See annotated figure);
a gate electrode structure (a collection of 108, 710, and 111) disposed apart from the bottom portion and the sidewall portion of the gate trench (apart by intervening 106) inside the gate trench, the gate electrode structure including a gate electrode (a collection of 108 and 710) and a gate capping layer (111), the gate electrode including a first sub-gate electrode (108) in a lower portion of the gate trench (See annotated figure for direction designation) and a second sub-gate electrode (710) on the first sub-gate electrode (directly on), the gate capping layer being on the second sub-gate electrode (directly on); and
a gate insulating layer (a collection of 106 and 309′) between (horizontally and vertically sandwiched between) the gate trench and the gate electrode structure, the gate insulating layer including a base insulating layer (106) and a reinforcing insulating layer (309′), the base insulating layer being between the bottom portion and the sidewall portion of the gate trench and the gate electrode structure (horizontally and vertically sandwiched between), and the reinforcing insulating layer being on and in direct contact with a sidewall portion of the second sub-gate electrode (See annotated figure for designated sidewall portion),
wherein a second thickness of the gate insulating layer (the combined thickness of 106 with 309′ is D2+W2) between (horizontally between) the sidewall portion of the second sub-gate electrode and the sidewall portion of the gate trench on a top level of the second sub-gate electrode is greater than (“greater than” by the amount of W2) a first thickness of the gate insulating layer (only the thickness of 106 is D2) between (horizontally between) a sidewall portion of the gate capping layer and the sidewall portion of the gate trench on a bottom level of the gate capping layer.
Regarding claim 13, Ryu discloses the IC device of claim 11 (Fig. 30), wherein the first sub-gate electrode includes a metal layer ([0067]: “metal-based materials”), and the second sub-gate electrode includes a polysilicon layer doped with impurities ([0290]: “polysilicon doped with an N-type impurity”).
Regarding claim 14, Ryu discloses the IC device of claim 11 (Fig. 30), wherein the reinforcing insulating layer further includes an upper surface reinforcing insulating layer (See annotated figure for a designated portion of 309′) on an upper surface portion of the second sub-gate electrode (horizontally on).
Regarding claim 15, Ryu discloses the IC device of claim 11 (Fig. 30), wherein the reinforcing insulating layer further includes a lower surface reinforcing insulating layer (See annotated figure for a designated portion of 309′) on a lower surface portion of the second sub-gate electrode (horizontally on).
Note that claim 11 was previously address above, however, it’s being addressed differently here based on the reading of the reference, particularly to the selected embodiment of Ryu in order to address the dependent claims 12 and 16.
Regarding independent claim 11, Ryu discloses an integrated circuit (IC) device (Fig. 8B) comprising:
a gate trench (105) inside a substrate (101), the gate trench including a bottom portion (See annotated figure) and a sidewall portion (See annotated figure);
a gate electrode structure (a collection of 210, 220, and 111) disposed apart from the bottom portion and the sidewall portion of the gate trench (apart by intervening 106) inside the gate trench, the gate electrode structure including a gate electrode (a collection of 210 and 220) and a gate capping layer (111), the gate electrode including a first sub-gate electrode (210) in a lower portion of the gate trench (See annotated figure for direction designation) and a second sub-gate electrode (220) on the first sub-gate electrode (indirectly on), the gate capping layer being on the second sub-gate electrode (directly on); and
a gate insulating layer (a collection of 106 and 109) between (horizontally and vertically sandwiched between) the gate trench and the gate electrode structure, the gate insulating layer including a base insulating layer (106) and a reinforcing insulating layer (109), the base insulating layer being between the bottom portion and the sidewall portion of the gate trench and the gate electrode structure (horizontally and vertically sandwiched between), and the reinforcing insulating layer being on and in direct contact with a sidewall portion of the second sub-gate electrode (See annotated figure for designated sidewall portion),
wherein a second thickness of the gate insulating layer (the combined horizontal thickness of 106 with 109) between (horizontally between) the sidewall portion of the second sub-gate electrode and the sidewall portion of the gate trench on a top level of the second sub-gate electrode is greater (“greater” by the horizontal thickness of 109) than a first thickness of the gate insulating layer (only the horizontal thickness of 106) between (horizontally between) a sidewall portion of the gate capping layer and the sidewall portion of the gate trench on a bottom level of the gate capping layer.
Regarding claim 12, Ryu discloses the IC device of claim 11 (Fig. 8B), wherein a fourth thickness of the gate insulating layer (the combined horizontal thickness of 106 with 109) between the sidewall portion of the second sub-gate electrode and the sidewall portion of the gate trench on a bottom level of the second sub-gate electrode is greater (“greater” by the horizontal thickness of 109) than a third thickness of the gate insulating layer (only the horizontal thickness of 106) between a sidewall portion of the first sub-gate electrode and the sidewall portion of the gate trench on a top level of the first sub-gate electrode.
Regarding claim 16, Ryu discloses the IC device of claim 11 (Fig. 8B), wherein a thickness of an upper sidewall of the reinforcing insulating layer (vertical thickness A, See annotated figure for measurement endpoints) on an upper sidewall portion of the second sub-gate electrode (directly on) is greater (“greater” because it vertically extends beyond thickness B) than a thickness of a lower sidewall of the reinforcing insulating layer (vertical thickness B, See annotated figure for measurement endpoints) on a lower sidewall portion of the second sub-gate electrode.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu as applied to claim 1 above, and further in view of Song (US 20200388679 A1).
Regarding claim 5, Ryu discloses the IC device of claim 1 (Fig. 30), but fails to teach “wherein the gate insulating layer further includes a liner insulating layer on the bottom portion and the sidewall portion of the gate trench”.
Song discloses (Claim 1 limitations) a gate insulating layer (Fig. 3: 130) between the gate trench (140t) and the gate electrode structure (120), the gate insulating layer including a base insulating layer (a secondly formed layer of [0057]: “an oxide/nitride/oxide (ONO) structure”, i.e., the nitride) […], the base insulating layer being between the bottom portion and the sidewall portion of the gate trench and the gate electrode structure, […] (Claim 5 limitations) wherein the gate insulating layer further includes a liner insulating layer (a firstly formed layer of [0057]: “an oxide/nitride/oxide (ONO) structure”, i.e., the oxide nearest the trench) on the bottom portion and the sidewall portion of the gate trench.
Modifying the gate insulating layer of Ryu by having a multi-layer configuration consistent with the teachings of Song would arrive at the claimed layer configuration. A person of ordinary skill in the art before the effective filing date would have a reasonable expectation of success because Ryu teaches the gate insulating layer may be varied to include at least the same materials for the same functional layer ([0066]: “may include a silicon oxide, a silicon nitride, a silicon oxynitride, a high-k material, or a combination thereof”). Song provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed layer configuration in that it would improve device reliability ([0057]: “to have long life reliability”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed layer configuration because it would improve device reliability. MPEP 2143 (I)(G).
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu in view of Song.
Regarding independent claim 17 as noted in the 112(b) rejection, Ryu discloses an integrated circuit (IC) device (Fig. 30) comprising:
a gate trench (105) inside a substrate (101), the gate trench including a bottom portion (See annotated figure) and a sidewall portion (See annotated figure);
a gate electrode structure (a collection of 108, 710, and 111) disposed apart from the bottom portion and the sidewall portion of the gate trench (apart by intervening 106) inside the gate trench, the gate electrode structure including a gate electrode (a collection of 108 and 710) including a first sub-gate electrode (108) in a lower portion of the gate trench (See annotated figure for direction designation) and including a metal layer ([0067]: “metal-based materials”), and a second sub-gate electrode (710) on the first sub-gate electrode (directly on) and including a polysilicon layer doped with impurities ([0290]: “polysilicon doped with an N-type impurity”), and a gate capping layer (111) on the second sub-gate electrode (directly on); and
a gate insulating layer (a collection of 106 and 309′) between the gate trench and the gate electrode structure (horizontally and vertically sandwiched between), the gate insulating layer including a liner insulating layer (106) on the bottom portion and the sidewall portion of the gate trench (directly on) and including a silicon oxide layer ([0066]: “may include a silicon oxide”), […] and a reinforcing insulating layer (309′) on and in direct contact with a sidewall portion of the second sub-gate electrode (See annotated figure for designated sidewall portion) and including a silicon oxide layer ([0315]: “The DICS may include lanthanum atoms” in combination with [0186]: “a lanthanum-diffused silicon oxide”),
wherein a second thickness of the reinforcing insulating layer and the [gate insulating layer] (the combined thickness of 106 with 309′ is D2+W2) on the sidewall portion of the second sub-gate electrode on a top level of the second sub-gate electrode is greater than (“greater than” by the amount of W2) a first thickness of the [gate insulating layer] (only the thickness of 106 is D2) on a sidewall portion of the gate capping layer on a bottom level of the gate capping layer.
Ryu teaches the gate insulating layer but fails to teach the gate insulating layer having a configuration with “a base insulating layer between the liner insulating layer and the gate electrode structure, […]
wherein a second thickness of the reinforcing insulating layer and the base insulating layer on the sidewall portion of the second sub-gate electrode on a top level of the second sub-gate electrode is greater than a first thickness of the base insulating layer on a sidewall portion of the gate capping layer on a bottom level of the gate capping layer”.
Song discloses a gate insulating layer (Fig. 3: 130) between the gate trench (140t) and the gate electrode structure (120), the gate insulating layer including a liner insulating layer (a firstly formed layer of [0057]: “an oxide/nitride/oxide (ONO) structure”, i.e., the oxide nearest the trench) on the bottom portion and the sidewall portion of the gate trench and including a silicon oxide layer ([0056]: “silicon oxide”), a base insulating layer (a secondly formed layer of [0057]: “an oxide/nitride/oxide (ONO) structure”, i.e., the nitride) between the liner insulating layer and the gate electrode structure.
Modifying the gate insulating layer of Ryu by having a multi-layer configuration consistent with the teachings of Song would arrive at the claimed layer configuration. A person of ordinary skill in the art before the effective filing date would have a reasonable expectation of success because Ryu teaches the gate insulating layer may be varied to include at least the same materials for the same functional layer ([0066]: “may include a silicon oxide, a silicon nitride, a silicon oxynitride, a high-k material, or a combination thereof”). Song provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed layer configuration in that it would improve device reliability ([0057]: “to have long life reliability”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed layer configuration because it would improve device reliability. MPEP 2143 (I)(G).
Regarding claim 18, Ryu in view of Song discloses the IC device of claim 17 (Ryu: Fig. 30), wherein the reinforcing insulating layer is further on an upper surface portion of the second sub-gate electrode to surround (309′ is horizontally on each side of the corners of electrode 710, therefore it partially surrounds these corners) an upper corner of the second sub-gate electrode.
Note that claim 17 was previously address above, however, it’s being addressed differently here based on the reading of the reference, particularly to the selected embodiment of Ryu in order to address the dependent claim 19.
Regarding independent claim 17 as noted in the 112(b) rejection, Ryu discloses an integrated circuit (IC) device (Fig. 8B) comprising:
a gate trench (105) inside a substrate (101), the gate trench including a bottom portion (See annotated figure) and a sidewall portion (See annotated figure);
a gate electrode structure (a collection of 210, 220, and 111) disposed apart from the bottom portion and the sidewall portion of the gate trench (apart by intervening 106) inside the gate trench, the gate electrode structure including a gate electrode (a collection of 210 and 220) including a first sub-gate electrode (210) in a lower portion of the gate trench (See annotated figure for direction designation) and including a metal layer ([0148]: “titanium nitride”), and a second sub-gate electrode (220) on the first sub-gate electrode (indirectly on) and including a polysilicon layer doped with impurities ([0149]: “polysilicon doped with an N-type impurity”), and a gate capping layer (111) on the second sub-gate electrode (directly on); and
a gate insulating layer (a collection of 106 and 109) between the gate trench and the gate electrode structure (horizontally and vertically sandwiched between), the gate insulating layer including a liner insulating layer (106) on the bottom portion and the sidewall portion of the gate trench (directly on) and including a silicon oxide layer ([0066]: “may include a silicon oxide”), […] and a reinforcing insulating layer (109) on and in direct contact with a sidewall portion of the second sub-gate electrode (See annotated figure for designated sidewall portion) and including a silicon oxide layer ([0145]: “dipole inducing layer” in combination with [0186]: “a lanthanum-diffused silicon oxide”),
wherein a second thickness of the reinforcing insulating layer and the [gate insulating layer] (the combined horizontal thickness of 106 with 109) on the sidewall portion of the second sub-gate electrode on a top level of the second sub-gate electrode is greater than (“greater than” by the horizontal thickness of 109) a first thickness of the [gate insulating layer] (only the horizontal thickness of 106) on a sidewall portion of the gate capping layer on a bottom level of the gate capping layer.
Ryu teaches the gate insulating layer but fails to teach the gate insulating layer having a configuration with “a base insulating layer between the liner insulating layer and the gate electrode structure, […]
wherein a second thickness of the reinforcing insulating layer and the base insulating layer on the sidewall portion of the second sub-gate electrode on a top level of the second sub-gate electrode is greater than a first thickness of the base insulating layer on a sidewall portion of the gate capping layer on a bottom level of the gate capping layer”.
Song discloses a gate insulating layer (Fig. 3: 130) between the gate trench (140t) and the gate electrode structure (120), the gate insulating layer including a liner insulating layer (a firstly formed layer of [0057]: “an oxide/nitride/oxide (ONO) structure”, i.e., the oxide nearest the trench) on the bottom portion and the sidewall portion of the gate trench and including a silicon oxide layer ([0056]: “silicon oxide”), a base insulating layer (a secondly formed layer of [0057]: “an oxide/nitride/oxide (ONO) structure”, i.e., the nitride) between the liner insulating layer and the gate electrode structure.
Modifying the gate insulating layer of Ryu by having a multi-layer configuration consistent with the teachings of Song would arrive at the claimed layer configuration. A person of ordinary skill in the art before the effective filing date would have a reasonable expectation of success because Ryu teaches the gate insulating layer may be varied to include at least the same materials for the same functional layer ([0066]: “may include a silicon oxide, a silicon nitride, a silicon oxynitride, a high-k material, or a combination thereof”). Song provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed layer configuration in that it would improve device reliability ([0057]: “to have long life reliability”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed layer configuration because it would improve device reliability. MPEP 2143 (I)(G).
Regarding claim 19, Ryu in view of Song discloses the IC device of claim 17 (Ryu: Fig. 8B), wherein a fourth thickness of the reinforcing insulating layer and the base insulating layer (the combined horizontal thickness of 106 with 109) on the sidewall portion of the second sub-gate electrode on a bottom level of the second sub-gate electrode is greater (“greater” by the horizontal thickness of 109) than a third thickness of the base insulating layer (only the horizontal thickness of 106) on a sidewall portion of the first sub-gate electrode on a top level of the first sub-gate electrode.
Allowable Subject Matter
Claims 8-9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claim 8 is the inclusion of the limitation “wherein a sidewall profile of the gate capping layer is curved so that a width of the gate capping layer gradually decreases along a direction from an upper surface portion of the gate capping layer to a lower surface portion of the gate capping layer” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “curved” and “gradually decreases” in combination with all other limitations in claims 8 and 1. The prior art of record describes methods producing structures shaped substantially similar to the claimed structures, but claim 8 includes shape limitations that go beyond an obvious difference of shape because the claimed shape is a resultant shape produced by a method that is both different from the prior art and is not reasonably rendered obvious when considering the method required to produce all other structures of the claimed device.
The primary reason for the allowable subject matter of claim 20 is the inclusion of the limitation “a sidewall profile of the gate capping layer is curved so that a width of the gate capping layer gradually decreases along a direction from an upper surface portion of the gate capping layer to a lower surface portion of the gate capping layer, and a sidewall profile of the second sub-gate electrode is curved so that a width of the second sub-gate electrode gradually decreases along a direction from an upper surface portion of the second sub-gate electrode to a lower surface portion of the second sub-gate electrode” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “curved” and “gradually decreases” in combination with all other limitations in claims 20 and 17. The prior art of record describes methods producing structures shaped substantially similar to the claimed structures, but claim 20 includes shape limitations that go beyond an obvious difference of shape because the claimed shape is a resultant shape produced by a method that is both different from the prior art and is not reasonably rendered obvious when considering the method required to produce all other structures of the claimed device.
Response to Arguments
Applicant's arguments filed 1/27/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 1 that “Kim does not disclose or suggest the above-noted features of amended claim 1”. Remarks at pg. 13.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Ryu has been relied upon in the instant Office action as necessitated by the claim amendment.
Applicant argues:
Applicant argues with respect to new claim 21 that “the device isolation layer 110 (highlighted in yellow) is not disposed between the capping pattern 230 (highlighted in red) and the gate electrode 210 (highlighted in red) in a vertical direction”. Remarks at pg. 15.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 21 have been considered but are moot because the rejection in the instant Office action does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Ryu has been relied upon in the instant Office action.
Applicant argues:
Applicant argues with respect to amended claim 11 that “the asserted references taken individually or in any proper combination do not anticipate nor render obvious amended claim 11”. Remarks at pg. 15.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Ryu has been relied upon in the instant Office action as necessitated by the claim amendment.
Applicant argues:
Applicant argues with respect to amended claim 17 that “the asserted references taken individually or in any proper combination do not anticipate nor render obvious amended claim 17”. Remarks at pg. 16.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Ryu and Song have been relied upon in the instant Office action as necessitated by the claim amendment.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
/Kretelia Graham/ Supervisory Patent Examiner, Art Unit 2817 February 20, 2026