DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
An amendment filed on 06/15/2026 in response to the Office Action mailed on 03/13/2026 is
being acknowledged and entered into the record. The present Final rejection is made by taking into
full consideration all the amendments.
Response to Arguments
On page 10 of the remarks filed on 06/15/2026, with respect to the 102 rejection of Claim 1, Applicant argues that the cited references do not teach the newly recited limitations of the amended claim 1. These arguments have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of 103 rejection is made in view of the previously cited reference of Nuotio and Jeon and in combination with newly found prior art references of Corisis. The combination of Nuotio/Jeon/Corisis teaches all of the limitations of amended Claim 1, as outlined in the rejection below.
On page 11 of the remarks filed on 06/15/2026, with respect to the amended Claim 1, Applicant argues that Jeon fails to teach the dies 231 and 232 are in an inverted orientation relative to each other, as recited in amended Claim 1 and that Jeon's alleged output terminal contacts the bottom side of one MOSFET and the top side of the other MOSFET and therefore does not include a lower portion configured for connection to a busbar and connected to connections pads on the bottom sides of both the first and second MOSFETs. These arguments have been fully considered but are not persuasive. The above limitations are already taught by the primary reference of Nuotio, as outlined in the rejection below. In fact, Jeon is relied upon only to teach an upper output terminal portion connected to the lower output terminal portion, Furthermore, in response to applicant's arguments against the references individually, one cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As such, the combination of Nuotio/Jeon/Corisis teaches all of the limitations of amended Claim 1, as outlined in the rejection below. Therefore, Jeon is still relied upon for the rejection of Claim 1.
On page 10 of the remarks filed on 06/15/2026, with respect to the 103 rejection of Claim 10, Applicant argues that the cited references do not teach the newly recited limitations of the amended claim 10. These arguments have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of 103 rejection is made in view of the previously cited reference of Nuotio and Ho and in combination with newly found prior art reference of Corisis. The combination of Nuotio/Ho/Corisis teaches all of the limitations of amended Claim 10, as outlined in the rejection below.
Claim Rejections - 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Rejection note: Italicized claim limitations are limitations not explicitly disclosed in the primary
reference but disclosed in the secondary references.
Claims 1, 4, 5, 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Nuotio (US 20230068223 A1), in view of Jeon (US 20160126157 A1) and Corisis et al. (US 6381141).
Regarding Claim 1 Nuotio teaches an electronic package, comprising:
a first Metal Oxide Silicon Field Effect Transistor (MOSFET) die 400b arranged in a first orientation, including (a) a first MOSFET gate connection pad 230_1 and a first MOSFET source connection pad 220_1 on an upper side of the first MOSFET die 400b, and (b) a first MOSFET drain connection pad 210_1 on a lower side of the first MOSFET die 400b (see annotated Fig. 4: 400b, 230_1, 210_1, 220_1, Fig. 2: 210, 230, 220, paragraph 0025, 0030);
a second MOSFET die 400a arranged in a second orientation inverted relative to the first orientation, including (a) a second MOSFET drain connection pad 210_2 on an upper side of the second MOSFET die 400a and (b) a second MOSFET gate connection pad 230_2 and a second MOSFET source connection pad 220_2 on a lower side of the second MOSFET die 400a (see annotated Fig. 4: 210_1, 210_2, 220_1, 220_1, 230_1, 230_2, Fig. 2: 210, 230, 220, paragraph 0025, 0030);
an upper conductive routing structure 44 extending over the first MOSFET die 400b and second MOSFET die 400a (Fig. 4: 44, 400a, 400b, paragraph 0030);
a lower conductive routing structure 41 extending under the first MOSFET die 400b and second MOSFET die 400a (Fig. 4: 41, 400a, 400b, paragraph 0030);
an output terminal 415c including:
a lower output terminal portion 415c configured for connection to a busbar extending under the first MOSFET die 400b and second MOSFET die 400a (see Fig. 4: 415c, Fig. 7: 630, paragraph 0030, 0031, paragraph 0058),
Note that in the implementation shown in Fig. 7, the conductive layer 630 corresponding to the conductive layer 415c of Fig. 4 is connected to a lead frame pin 505d allowing for connection with external busbars (see paragraph 0058).
the lower output terminal portion 415c including respective elements of the lower conductive routing structure 41, wherein the lower output terminal portion 415c is connected to (a) the first MOSFET drain connection pad 210_1 on the lower side of the first MOSFET die 400b and (b) the second MOSFET source connection pad 220_2 on the lower side of the second MOSFET die 400a (see annotated Fig. 4: 415c, 41, 210_1, 220_2, paragraph 0030, 0031);
and an upper output terminal portion connected to the lower output terminal portion and configured for connection to circuitry provided on a device substrate extending over the first MOSFET die 400b and second MOSFET die 400a;
and an encapsulation structure 460 at least partially encapsulating the first MOSFET die 400b and the second MOSFET die 400a (Fig. 4: 460, 400a, 400b, paragraph 0039).
Note that the bottom of Fig. 4 in the given orientation is interpreted as the upper side and the top of Fig. 4 is interpreted as the lower side.
Jeon teaches an electronic package comprising an output terminal 263-1, 213-2, 252-1, including the following limitation not disclosed in Nuotio:
an upper output terminal portion 263-1 connected to the lower output terminal portion 213-2 (see Fig. 2: 263-1, 252-1, 213-2, 260, 210 paragraph 0055).
Note that the terminals 263-1, 213-2 are connected to each other via the conductive spacer 252-1 and thus, the output terminals 263-1, 213-2 together with the spacer 252-1 is interpreted as the output terminal.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nuotio and Jeon in order to have the output terminal include an upper output terminal portion connected to the lower output terminal portion. Doing so would allow for efficient current collection and routing.
Corisis et al. teaches an electronic package comprising the following limitations not disclosed in Nuotio:
an output terminal 30 configured for connection to circuitry provided on a device substrate 14 extending over the first die and second die (see annotated Fig. 5: 14, column 2, lines 45-60, column 3, lines 40-49);
Note that the terminals 30 are connected to the circuit board 14 of Fig. 5, which is interpreted as the device substrate with circuitry, via the solder balls 21.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nuotio, Jeon and Cosisis et al. in order to have the upper output terminal portion connected to the lower output terminal portion of Nuotio modified by Jeon configured for connection to circuitry provided on a device substrate extending over the first MOSFET die 400b and second MOSFET die of Nuotio. Doing so would enable the electronic package to interface with external electronic components in a device substrate.
Regarding Claim 4, Nuotio teaches the electronic package of Claim 1, comprising:
(a) a high voltage terminal 445d connected to the second MOSFET drain connection pad 210_2, the high voltage terminal 445d including respective elements of the upper conductive routing structure 44 (see Fig. 4: 445d, 44, 210_2, paragraph 0030, 0031); and
(b) a ground terminal 445c connected to the first MOSFET source connection pad 220_1, the ground terminal 445c including respective elements of the upper conductive routing structure 44 (see Fig. 4: 445c, 44, 220_1, paragraph 0030, 0031).
Regarding Claim 5, Nuotio teaches the electronic package of Claim 1, wherein the first MOSFET die 400b comprises a first silicon carbide (SiC) MOSFET, and the second MOSFET die 400b comprises a second SiC MOSFET (paragraph 0026).
Regarding Claim 8, Nuotio teaches the electronic package of Claim 1, wherein at least one of the upper conductive routing structure 530 or the lower conductive routing structure 630 comprises a lead frame 505d, 605d (see annotated Fig. 7: 530, 630, 505d, 605d, paragraph 0057).
Note that Fig. 4 of Nuotio can be considered as a cross-sectional view of Fig. 7 through vertical line A-B of Fig. 7 and therefore reads on the same embodiment.
Regarding Claim 9, Nuotio teaches the electronic package of Claim 1, comprising: a third MOSFET die 400d arranged in the first orientation; and a fourth MOSFET 400c arranged in the second orientation inverted relative to the first orientation; wherein the upper conductive routing structure 530 extends over the first MOSFET die 400b, second MOSFET die 400a, third MOSFET die 400d, and fourth MOSFET die 400c; and wherein the lower conductive routing structure 630 extends under the first MOSFET die 400b, second MOSFET die 400a, third MOSFET die 400d, and fourth MOSFET die 400c (see annotated Fig. 7: 400a, 400b, 400c, 400d, 530, 630, paragraph 0055, 0056).
Note that Fig. 4 of Nuotio can be considered as a cross-sectional view of Fig. 7 through vertical line A-B of Fig. 7 and therefore reads on the same embodiment.
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Annotated Fig. 4 of Nuotio (US 20230068223 A1).
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Annotated Fig. 5 of Corisis et al. (US 6381141).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Nuotio (US 20230068223 A1), in view of Jeon (US 20160126157 A1) and Corisis et al. (US 6381141), as applied to Claim 1 above, further in view of Zhang et al. (US 20200194395 A1).
Regarding Claim 2, Nuotio fails to explicitly teach the electronic package of Claim 1, wherein the electronic package comprises a panel level package (PLP).
However, Zhang et al. teaches an electronic package, wherein the electronic package comprises a panel level package (PLP) (paragraph 0003, 0004, Fig. 21A-22B).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nuotio and Zhang et al. in order to have the electronic package of Nuotio comprise a panel level package (PLP). Doing so would yield simpler assembly process and reduced form factor, as recognized by Zhang et al. (paragraph 0004).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Nuotio (US 20230068223 A1), in view of Jeon (US 20160126157 A1) and Corisis et al. (US 6381141), as applied to Claim 1 above, further in view of Yoon et al. (US 20230154841 A1).
Regarding Claim 6, Nuotio fails to explicitly teach the electronic package of Claim 1, wherein at least one of the upper conductive routing structure or the lower conductive routing structure comprises a redistribution layer (RDL).
However, Yoon et al. teaches an electronic package, wherein at least one of the upper conductive routing structure 2400 or the lower conductive routing structure 2300 comprises a redistribution layer (RDL) (Fig. 7: 2300, 2400, paragraph 0089).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nuotio and Yoon et al. in order to have at least one of the upper conductive routing structure or the lower conductive routing structure of Nuotio comprise a redistribution layer (RDL). Doing so would enable highly integrated electronic packages with an increased number of connection terminals for input/output, as recognized by Yoon et al. (paragraph 0003).
Regarding Claim 7, Nuotio fails to explicitly teach the electronic package of Claim 1, wherein: the upper conductive routing structure comprises multiple stacked upper redistribution layers (RDLs); and the lower conductive routing structure comprises multiple stacked lower RDLs.
However, Yoon et al. teaches an electronic package, wherein: the upper conductive routing structure 2400 comprises multiple stacked upper redistribution layers (RDLs) 2422; and the lower conductive routing structure 2300 comprises multiple stacked lower RDLs 2322 (Fig. 7: 2300, 2322, 2400, 2422, paragraph 0090, 0096).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nuotio and Yoon et al. in order to have the upper conductive routing structure comprise multiple stacked upper redistribution layers (RDLs) and the lower conductive routing structure comprise multiple stacked lower RDLs. Doing so would enable highly integrated electronic packages with an increased number of connection terminals for input/output, as recognized by Yoon et al. (paragraph 0003).
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Nuotio (US 20230068223 A1), in view of Ho et al. (US 20120032259 A1) and Corisis et al. (US 6381141).
Regarding Claim 10, Nuotio teaches an electronic device, comprising: an electronic package, comprising:
a plurality of first Metal Oxide Silicon Field Effect Transistor (MOSFET) dies 400b, 400d arranged in a first orientation (annotated Fig. 7: 400b, 400d, annotated Fig 4: 400b, paragraph 0030, 0055, 0056);
a plurality of second MOSFET dies 400a, 400c arranged in a second orientation inverted relative to the first orientation (annotated Fig. 7: 400a, 400c, annotated Fig 4: 400a, paragraph 0030, 0055, 0056);
a first conductive routing structure 41 including at least one first conductive routing layer 415f, 415e, 415d, 415c extending over the plurality of first MOSFET dies 400b, 400d and over the plurality of second MOSFET dies 400a, 400c, the first conductive routing structure 41 defining: a first MOSFET drain connection structure 415c connected to respective drain connection pads 210_1 on the plurality of first MOSFET dies 400b, 400d; a second MOSFET source connection structure 415c connected to respective source connection pads 220_2 on the plurality of second MOSFET dies 400a, 400c; and a second MOSFET gate connection structure connected to respective gate connection pads 230_2 on the plurality of second MOSFET dies 400a, 400c (see annotated Fig. 4: 44, 415c, 445f, 210_1, 400a, 400b, Fig. 2: 210, 230, 220, annotated Fig. 7, paragraph 0030);
Note that Fig. 4 of Nuotio can be considered as a cross-sectional view of Fig. 7 through vertical line A-B of Fig. 7 and therefore read on the same embodiment.
and a second conductive routing structure 44 including at least one second conductive routing layer 445f, 445e, 445d extending under the plurality of first MOSFET dies 400b, 400d and under the plurality of second MOSFET dies 400a, 400c, the second conductive routing structure 44 defining: a second MOSFET drain connection structure 445d connected to respective drain connection pads 210_2 on the plurality of second MOSFET dies 400a, 400c; and a first MOSFET source connection structure 445c connected to respective source connection pads 220_1 on the plurality of first MOSFET dies 440b, 400d (see annotated Fig. 4: 44, 445c, 445d, 210_1, 210_2, 220_1, 220_1, 230_1, 230_2, Fig. 2: 210, 230, 220, annotated Fig. 7, paragraph 0030);
and wherein the first conductive routing structure 41 defining the first MOSFET drain connection structure 415c and the second MOSFET source connection structure 415c is configured for connection to (a) a busbar extending over the first MOSFET dies 400b, 400d and second MOSFET dies 400a, 400c and (b) electronics provided on a device substrate extending under the first MOSFET dies and second MOSFET dies (see Fig. 4: 415c, 41, 400a, 400b, Fig. 7: 400a, 400b, 400c, 400d, 630, paragraph 0030, 0031, paragraph 0058),
Note that in the implementation shown in Fig. 7, the conductive layer 630, corresponding to the conductive layer 415c of Fig. 4 is connected to a lead frame pin 505d allowing for connection with external busbars (see paragraph 0058).
Ho et al. teaches a MOSFET device comprising the following limitations not disclosed in Nuotio:
a first conductive routing structure defining a MOSFET gate connection structure 121 connected to respective gate connection pad on the MOSFET die 100 (annotated Fig. 1: first conductive routing structure, 121, 100, paragraph 0013).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nuotio and Ho et al. in order to have the first conductive routing structure of Nuotio defining a second MOSFET gate connection structure connected to respective gate connection pads on the plurality of second MOSFET dies. Doing so would provide access to the gate electrode of the second MOSFETs, as recognized by Ho et al. (paragraph 0004), allowing for easier routing of signals across the die.
Corisis et al. teaches an electronic package comprising the following limitations not disclosed in Nuotio:
wherein the first conductive structure 30 is configured for connection to electronics provided on a device substrate 14 extending under the first dies and second dies (see annotated Fig. 5: 14, column 2, lines 45-60, column 3, lines 40-49).
Note that the conductive structure 30 are connected to the circuit board 14 of Fig. 5, which is interpreted as the device substrate with circuitry, via the solder balls 21.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nuotio, Jeon and Cosisis et al. in order to have the first conductive structure of Noutio configured for connection to electronics provided on a device substrate extending under the first dies and second dies of Noutio. Doing so would enable the electronic package to interface with external electronic components in a device substrate.
Regarding Claim 11, Nuotio teaches the electronic device of Claim 10, the electronic package comprising an encapsulation structure 360 at least partially encapsulating the plurality of first MOSFET dies 400b, 400d, the plurality of second MOSFET dies 400a, 400c, the first conductive routing structure 530, and the second conductive routing structure 630 (See annotated Fig. 7: 360, paragraph 0058).
Note that the encapsulation structure is indexed 360 in Fig. 7 but 460 in paragraph 0058 of the specification.
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Annotated Fig. 7 of Nuotio (US 20230068223 A1).
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Annotated Fig. 1 of Ho et al. (US 20120032259 A1).
Regarding Claim 12, Nuotio teaches the electronic device of Claim 10, the electronic package comprising a first MOSFET gate connection structure 415d connected to respective gate connection pads 230_1 on the plurality of first MOSFET dies 400b, 400d, the first MOSFET gate connection structure 415d including at least one conductive element formed in the first conductive routing structure 41 (see annotated Fig. 4: 415d, 400b, paragraph 0030).
Nuotio fails to teach the first MOSFET gate connection structure 415d including at least one conductive element formed in the second conductive routing structure 44.
However, Ho et al. teaches the MOSFET gate connection structure 121 including at least one conductive element formed in the first conductive routing structure and at least one conductive element formed in the second conductive routing structure (see annotated Fig. 1, paragraph 0013).
Note that the gate connection structure 121 extends through both the first and second conductive routing structures and therefore would include a portion formed in the first conductive routing structure and a portion formed in the second conductive routing structure.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nuotio and Ho et al. in order to have the first MOSFET gate connection structure including at least one conductive element formed in the first conductive routing structure and at least one conductive element formed in the second conductive routing structure. Doing so would achieve routing flexibility allowing for sperate local and global routing such as local connection to gate pads and long-distance routing.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Nuotio (US 20230068223 A1), in view of Ho et al. (US 20120032259 A1) and Corisis et al. (US 6381141), as applied to Claim 10 above, further in view of Otremba (US 7271470 B1).
Regarding Claim 14, Nuotio teaches the electronic device of Claim 10, comprising a substrate 445b; wherein the second MOSFET drain connection structure 445d and the first MOSFET source connection structure 445c are mounted on the substrate 445b (see annotated Fig. 4: 445b, 445d, 445c, paragraph 0036), except that the substrate 445b is a printed circuit board and that the drain/source connection structures are mounted to respective electronics on the printed circuit board.
However, Otremba teaches an electronic device, comprising a printed circuit board as a support structure for the first MOSFET 32 and second MOSFET 33 (See Fig. 3: 32, 33, column 3, lines 20-35, column 14, lines 57-67 ).
Note that the lead frame 34, 35, 36, 37 of Fig. 3 is attached to a PCB according to column 3, lines 20-35.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the substrate of Nuotio with the PCB of Otremba in order to yield predictable results of achieving equivalent structural and electrical support.
Furthermore, it would have been obvious to a person of ordinary skill in the art that when the printed circuit board of Otremba is substituted for the substrate of Nuotio, the second MOSFET drain connection structure and the first MOSFET source connection structure will be mounted to respective electronics on the printed circuit board.
Regarding Claim 15, Nuotio teaches the electronic device of Claim 10, comprising a substrate 415b, 445b; wherein the second MOSFET source connection structure 415c, the first MOSFET drain connection structure 415c, the first MOSFET gate connection structure 415e, and the second MOSFET gate connection structure 445f are mounted on the substrate 415b, 445b (see annotated Fig. 4: 415b, 445b, 415d, 445f, 415e, paragraph 0036), except that the substrate 415b, 445b is a printed circuit board and the connection structures are mounted to respective electronics on the printed circuit board.
However, Otremba teaches an electronic device, comprising a printed circuit board as a support structure for the first MOSFET 32 and second MOSFET 33 (See Fig. 3: 32, 33, column 3, lines 20-35, column 14, lines 57-67 ).
Note that the lead frame 34, 35, 36, 37 of Fig. 3 is attached to a PCB according to column 3, lines 20-35.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the substrate of Nuotio with the PCB of Otremba in order to yield predictable results of achieving equivalent structural and electrical support.
Furthermore, it would have been obvious to a person of ordinary skill in the art that when the printed circuit board of Otremba is substituted for the substrate of Nuotio, the second MOSFET source connection structure, the first MOSFET drain connection structure, the first MOSFET gate connection structure, and the second MOSFET gate connection structure would be mounted to respective electronics on the printed circuit board.
Claims 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Nuotio (US 20230068223 A1), in view of Jeon (US 20160126157 A1) and Corisis et al. (US 6381141), as applied to Claim 1 above, further in view of Ho et al. (US 20120032259 A1).
Regarding Claim 24, Nuotio teaches the electronic package of Claim 1, comprising a second MOSFET gate contact 445f connected to the second MOSFET gate connection pad 230_2, the second MOSFET gate contact 445f including (a) upper elements formed in the upper conductive routing structure 44 (see annotated Fig. 4: 445f, 230_2, paragraph 0030), but fails to teach the second MOSFET gate contact 445f including (b) lower elements formed in the lower conductive routing structure 41.
However, Ho et al. teaches a MOSFET device comprising a MOSFET gate contact 121 connected to the MOSFET gate connection pad 120, the second MOSFET gate contact 121 including (a) upper elements formed in the upper conductive routing structure and (b) lower elements formed in the lower conductive routing structure. (see annotated Fig. 1: 120, 121, paragraph 0013).
Note that the gate connection structure 121 extends through both the upper and lower conductive routing structures and therefore would include a portion formed in the upper routing structure and a portion formed in the lower routing structure.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nuotio and Ho et al. in order to have the second MOSFET gate contact including (a) upper elements formed in the upper conductive routing structure and (b) lower elements formed in the lower conductive routing structure. Doing so would achieve routing flexibility allowing for sperate local and global routing such as local connection to gate pads and long-distance routing.
Regarding Claim 25, Nuotio fails to teach the electronic package of Claim 24, wherein the second MOSFET gate contact further includes an intermediate conductive routing structure connecting the upper elements of the second MOSFET gate contact with the lower elements of the second MOSFET gate contact.
However, Ho et al. teaches wherein the MOSFET gate contact further includes an intermediate conductive routing structure connecting the upper elements of the MOSFET gate contact 121 with the lower elements of the MOSFET gate contact 121 (see annotated Fig. 1, paragraph 0013).
Note that the portion of the gate contact 121 extending between the upper and lower routing layers of Fig. 1 is interpreted the intermediate conductive routing structure.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nuotio and Ho et al. in order to have the second MOSFET gate contact further include an intermediate conductive routing structure connecting the upper elements of the second MOSFET gate contact with the lower elements of the second MOSFET gate contact. Doing so would allow for improved layout flexibility by providing a transition layer between local and global routing.
Regarding Claim 26, Nuotio teaches the electronic package of Claim 1, comprising a first MOSFET gate contact 415e connected to the first MOSFET gate connection pad 230_1 (see annotated Fig. 4: 415e, 230_1, paragraph 0030), but fails to teach the first MOSFET gate contact 415e including respective elements of the upper conductive routing structure 44.
However, Ho et al. teaches a MOSFET device comprising a MOSFET gate contact 121 connected to the MOSFET gate connection pad 120, the MOSFET gate contact 121 including respective elements of the upper conductive routing structure (see annotated Fig. 1: 120, 121, paragraph 0013).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Nuotio and Ho et al. in order to have the first MOSFET gate contact including respective elements of the upper conductive routing structure. Doing so would provide access to the gate pads of the first MOSFETs, as recognized by Ho et al. (paragraph 0004), allowing for easier routing of signals across the die.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Nuotio (US 20230068223 A1), in view of Jeon (US 20160126157 A1) and Corisis et al. (US 6381141), as applied to Claim 4 above, further in view of Otremba (US 7271470 B1).
Regarding Claim 28, Nuotio teaches the electronic package of Claim 4, wherein the device substrate 445b comprises a printed circuit board; wherein the ground terminal 445c and the high voltage terminal 445d are mounted to respective electronics on the printed circuit board (see annotated Fig. 4: 445b, 445c, 445d, paragraph 0036).
Otremba teaches an electronic device, comprising a printed circuit board as a support structure for the first MOSFET 32 and second MOSFET 33 (See Fig. 3: 32, 33, column 3, lines 20-35, column 14, lines 57-67 ).
Note that the lead frame 34, 35, 36, 37 of Fig. 3 is attached to a PCB according to column 3, lines 20-35.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the substrate of Nuotio with the PCB of Otremba in order to yield predictable results of achieving equivalent structural and electrical support.
Furthermore, it would have been obvious to a person of ordinary skill in the art that when the printed circuit board of Otremba is substituted for the substrate of Nuotio, the ground terminal and the high voltage terminal will be mounted to respective electronics on the printed circuit board.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at 571-272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 09/09/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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