Attorney Docket Number: 69620-108
Filing Date: 05/26/2023
Claimed Priority Date: 05/26/2022 (PRO 63/365,342)
Inventor: Tseng
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 06/03/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 06/03/2026 in reply to the previous Office action mailed on 12/03/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-22, with claims 11-22 remaining withdrawn from consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 4 is rejected under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 4 recites the limitation “the hardness of one of said bump buffer layers away from said first bump layer”. No particular or specific “bump buffer layers” has been previously recited or “said” to be located away from the first bump layer. In fact, no orientation, positioning, or disposition for any of the recited bump buffer layers in relation to any of the first and second bump layers is ever disclosed in the claims to provide sufficient support that “one of said bump buffer layers” is guaranteed to be positioned “away from” said first bump layer. Accordingly, there is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation “the hardness of one of said bump buffer layers close to said first bump layer”. No particular or specific “said bump buffer layers” has been previously recited or “said” to be close to the first bump layer. In fact, no orientation, positioning, or disposition for any of the recited bump buffer layers in relation to any of the first and second bump layers is ever disclosed in the claims to provide sufficient support that “one of said bump buffer layers” is guaranteed to be positioned “close to” said first bump layer. Accordingly, there is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 5-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Abe (US 2007/0222085).
Regarding claim 1, Abe (see, e.g., fig. 7) shows all aspects of the instant invention, including a bump structure 43A, disposed on a chip 51, comprising:
a first bump layer 42A, disposed on said chip; and
a second bump layer 42a, disposed on a top surface of said first bump layer;
wherein:
the materials of said first bump layer 42A and said second bump layer 42a are the same conductive material (e.g., Gold or “Au”) (see, e.g., pars.0044/ll.16-17 and 0045/ll.1); and
the hardness of said first bump layer is different from the hardness of said second bump layer (see, e.g., pars.0025, 0035/ll.5-7, 0044/ll.16-18, and 0045/ll.1-3)
Regarding claim 5, Abe (see, e.g., pars.0025, 0035/ll.5-7, 0044/ll.16-18, and 0045/ll.1-3) shows that the hardness of said first bump layer 42A is smaller than the hardness of said second bump layer 42a.
Regarding claim 6, Abe (see, e.g., fig. 7 and par.0049/ll.3) shows that said first bump layer 42A is located on at least one metal layer 52A, and said at least one metal layer is located on said chip 51.
Regarding claim 7, Abe (see, e.g., fig. 7) shows that said first bump layer 42A is located on a passivation layer 53, said passivation layer is located on a contact pad 53A, and said contact pad is located on said chip 51 and contacting said chip.
Regarding claim 8, Abe (see, e.g., fig. 7 and par.0049/ll.3) shows that said first bump layer 42A is located on at least one metal layer 52A, and said at least one metal layer is located on said passivation layer 53. Furthermore, although Abe does not explicitly specify that layer 53A is metal, Abe teaches metals, such as gold and copper, to be suitable material for forming similar such layers (see, e.g., pars.0003/ll.9 and 0015/ll.6). Therefore, Abe shows again that said first bump layer 42A is located on at least one metal layer 53A, and said at least one metal layer is located on said passivation layer 53.
Regarding claim 9, Abe (see, e.g., figs. 5 and 7) shows that said passivation layer 53 has an opening, and said contact pad 53A and said first bump layer 42A correspond to said opening.
Regarding claim 10, Abe (see, e.g., fig. 7 and par.0049/ll.3) shows that said first bump layer 42A is located on at least one metal layer 52A, said at least one metal layer corresponds to said opening, and said at least one metal layer is located on and contacts said contact pad 53A.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Seo (US 2020/0075524) in view of Abe, Motoyoshi (US 2021/0399184), and Meyyappan (US 2023/0187337).
Regarding claim 1, Seo (see, e.g., fig. 3) shows most aspects of the instant invention, including a bump structure 140, disposed on a substrate 110, comprising:
a first bump layer 142, disposed on said substrate 110; and
a second bump layer 146, disposed on a top surface of said first bump layer;
wherein:
the materials of said first bump layer 142 and said second bump layer 146 are conductive material (see, e.g., pars.0026/ll.15-16 and 0059/ll.6-7); and
the hardness of said first bump layer is different from the hardness of the second bump layer (see, e.g., par.0031/ll.1-3)
Although Seo shows most aspects of the instant invention, and further specifies that Seo’s substrate may include semiconductor material (see, e.g., par.0022/ll.3-6), Seo fails to specify that Seo’s substrate is a chip. Abe, in the same field of endeavor, teaches that chips of semiconductor material perform suitably as substrates for bump structures, and that such chips can facilitate forming high frequency modules designed for high frequency applications (see, e.g., Abe: pars.0003/ll.1-5, 0049/ll.1-2, and 0051).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Abe’s semiconductor substrate constitute a chip, as taught by Abe, because these were recognized as equivalents in the semiconductor art, and so as to facilitate and/or expand the high frequency applications of Seo’s device.
Furthermore, although Seo shows most aspects of the instant invention, including that materials of the first and second bump layers are conductive material, Seo fails to specify that the materials of said first bump layer and said second bump layer are the same conductive material. Abe, in the same field of endeavor, teaches a similar bump structure to Seo, showing a bump structure 43A having a first bump layer 42A of a first conductive material and a second bump layer 42a of a second conductive material (see, e.g., pars.0044/ll.16-17 and 0045/ll.1). Abe teaches that the bump structure performs equally well regardless of whether the materials of said first bump layer and said second bump layer are the same conductive material or different conductive materials, so long as the first and second bump layers have different hardnesses, which can be ensured even with different first and second bump layer conductive materials (see, e.g., Abe: fig. 7, pars.0044/ll.16-17, 0045/ll.1, and 0070, and claims 7-8). Additionally, Motoyoshi, also in the same field of endeavor, teaches a bump structure having a first bump layer of a first conductive material and a second bump layer of a second conductive material, wherein the first conductive material may be the same as or may be different from the second conductive material and wherein the first and second bump layers have different hardnesses (see, e.g., Motoyoshi: pars.0062-0063). Motoyoshi, like Abe, teaches that as long as the first and second bump layers have different hardnesses, the bump structure performs as desired regardless of whether the materials of said first and second bump layers are the same conductive material or different conductive materials (see, e.g., Motoyoshi: pars.0062-0063). Moreover, Meyyappan, in the same field of endeavor as Seo, teaches that when the layers of a bump structure are formed from a same conductive material, an affinity between the layers is ensured and the layers more easily form an electrical connection (see, e.g., Meyyappan: par.0031/ll.5-8).
Abe and Motoyoshi are evidence showing that one of ordinary skill in the art would appreciate that having the materials of a first bump layer and a second bump layer be the same conductive material would be equivalent to having the materials of a first bump layer and a second bump layer be different conductive materials, and that such differences would result in no unexpected changes in the performance of the bump structure of Seo. That is, the materials of both Seo’s and Abe’s or Motoyoshi’s bump layers would yield the predictable result of suitably forming layers in a bump structure with differing individual hardness levels. Furthermore, Meyyappan is evidence showing that one of ordinary skill in the art would appreciate that there is incentive to form the first and second bump layers of a bump structure from the same material, so as to ensure an affinity between the bump layers and more easily form an electrical connection between them.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either the materials of a first bump layer and a second bump layer be the same conductive material, as taught by Abe and Motoyoshi, or the materials of a first bump layer and a second bump layer be different conductive materials, as taught by Seo, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of suitably forming layers in a bump structure with differing individual hardness levels. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007). Furthermore, in light of Meyyappan, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the materials of Seo’s first bump layer and second bump layer be the same conductive material, as taught by Meyyappan, so as to ensure an affinity between Seo’s bump layers and to more easily form an electrical connection between Seo’s bump layers.
Regarding claim 2, Seo (see, e.g., fig. 3 and pars.0026/ll.18-20, 0029/ll.4-6, 0030/ll.3-4, and 0031) shows that:
at least one bump buffer layer 144 is disposed between said first bump layer 142 and said second bump layer 146;
the materials of said first bump layer and said second bump layer are the same conductive material (see the comments stated above in paragraphs 21-23, which are considered to be repeated here); and
the hardness of said at least one bump buffer layer is different from the hardness of said first bump layer and said second bump layer
Although Seo/Abe/Motoyoshi/Meyyappan shows most aspects of the instant invention, including that the materials of said first bump layer and said second bump layer are the same conductive material (see the comments stated above in paragraphs 21-23, which are considered to be repeated here), Seo fails to specify that the material of said at least one bump buffer layer is the same conductive material as that of the first and second bump layers. Meyyappan, in the same field of endeavor as Seo, teaches that when the layers of a bump structure are formed from a same conductive material, an affinity between the layers is ensured and the layers more easily form an electrical connection (see, e.g., Meyyappan: par.0031/ll.5-8)
Therefore, it would have been obvious at the time of filing the invention to have all the bump layers of Seo’s device, that is – the first bump layer, the second bump layer, and the at least one bump buffer layer, be the same conductive material, as taught by Meyyappan, so as to ensure an affinity between the layers of Seo’s bump structure and to more easily form an electrical connection between the layers of Seo’s bump structure. See also the comments stated above in paragraphs 21-23 regarding the equivalency and interchangeability of materials in differing hardness layers of a bump structure, which are considered to be repeated here as applied to Seo’s at least one bump buffer layer.
Additionally, for the sake of clarity of the record, it is noted that specific claim limitation that the layer disposed between the first bump layer and the second bump layer is a bump buffer layer is a property of the device of Seo/Abe/Motoyoshi/Meyyappan.
Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See also Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
In the instant case, Seo teaches the same layers in a bump structure comprising different hardnesses as recited in the claim, therefore, the layer disposed between the first bump layer and the second bump layer will have the “buffer” property also recited in the claim.
Regarding claim 3, Seo (see, e.g., fig. 3 and pars.0026/ll.18-20, 0029/ll.4-6, 0030/ll.3-4, and 0031) shows that the hardness of said first bump layer 142 is smaller than the hardness of said at least one bump buffer layer 144, and the hardness of said at least one bump buffer layer is smaller than the hardness of said second bump layer 146.
Regarding claim 4, Seo (see, e.g., figs. 3 and 17 and par.0065/ll.1-2) shows that:
said at least one bump buffer layer 144 includes a plurality of bump buffer layers 147, 148;
the hardness of said first bump layer 142 is smaller than the hardness of said bump buffer layers 147, 148 (i.e., 144) (see, e.g., pars.0026/ll.18-20, 0029/ll.4-6); and
the hardness of said bump buffer layers 147, 148 (i.e., 144) is smaller than the hardness of said second bump layer 146 (see, e.g., par.0030/ll.3-4)
Although Seo fails to explicitly specify that the hardness of said bump buffer layers decreases stepwise while approaching said first bump layer and that the hardness of a bump buffer layer 147 most away from said first bump layer is greater than the hardness of a bump buffer layer 148 closest to said first bump layer, Seo teaches that when layers in a bump structure comprise a stepwise hardness decrease such that the bottommost layer has the smallest hardness, that potential delamination of the bottommost layer may be mitigated or prevented (see, e.g., figs. 3 and 17 and par.0031). Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the hardness of Seo’s said bump buffer layers decrease stepwise while approaching Seo’s first bump layer (i.e., approaching the bottommost layer), which inherently subsequently results in the hardness of the bump buffer layer most away from Seo’s first bump buffer layer being greater than the hardness of the bump buffer layer closest to Seo’s first bump layer, so as to mitigate or prevent delamination of the bump buffer layer closest to Seo’s first bump layer (i.e., Seo’s bottommost bump buffer layer 148).
With regards to other language recited in claim 4, see the comments stated above in paragraphs 5-6.
Regarding claim 5, Seo (see, e.g., fig. 3 and par.0031/ll.1-3) shows that the hardness of said first bump layer 142 is smaller than the hardness of said second bump layer 146.
Regarding claim 6, Seo (see, e.g., fig. 3) shows that said first bump layer 142 is located on at least one metal layer 130, and said at least one metal layer is located on said chip 110 (see paragraphs 18-20 above regarding “said chip”, wherein the comments stated there are considered to be repeated here).
Regarding claim 7, Seo (see, e.g., fig. 3) shows that said first bump layer 142 is located on a passivation layer 122, said passivation layer is located on a contact pad 120, and said contact pad is located on said chip 110 and contacting said chip (see paragraphs 18-20 above regarding “said chip”, wherein the comments stated there are considered to be repeated here).
Regarding claim 8, Seo (see, e.g., fig. 3) shows that said first bump layer 142 is located on at least one metal layer 130, and said at least one metal layer is located on said passivation layer 122.
Regarding claim 9, Seo (see, e.g., fig. 3) shows that said passivation layer 122 has an opening, and said contact pad 120 and said first bump layer 142 correspond to said opening.
Regarding claim 10, Seo (see, e.g., fig. 3) shows that said first bump layer 142 is located on at least one metal layer 130, said at least one metal layer corresponds to said opening, and said at least one metal layer is located on and contacts said contact pad 120.
Response to Arguments
With regards to the claims, Applicant argues:
Abe’s stud bump 43A is formed by welding of the Au wire 42A and the Au film 42a, further, the Au film 42a is coated around the Au wire 42A, and it is clear from Abe’s FIG. 7 that the Au film 42a is not disposed on the top surface of the Au wire 42A. Thereby, Abe fails to disclose “a bump structure… comprising a second bump layer disposed on a top surface of said first bump layer”, as claimed in amended claim 1 of this application.
The Examiner responds:
Terms such as “top”, “bottom”, “side”, and the like describe relative spatial positions and do not, without more, impose a fixed or absolute physical orientation on claimed components. Accordingly, the relevant surface is determined by the relative arrangement of the recited components in accordance with the language recited in the claims. Here, Abe expressly establishes that relative arrangement. Specifically, figure 7 of Abe shows a second bump layer 42a disposed on an outermost surface of a first bump layer 42A. Thus, the Abe teaches a second bump layer disposed on a top surface of said first bump layer, as recited in the amended claim.
With regards to the claims, Applicant additionally argues:
After Abe’s resin substrate 41 modifies Seo's substrate, Seo in view of Abe cannot disclose the first bump layer disposed on the chip and the second bump layer disposed on the top surface of the first bump layer as claimed in amended Claim 1 of this application. After Abe's stud bump 43A modifies Seo's bump structure 140, Seo in view of Abe cannot disclose the first bump layer disposed on the chip and the second bump layer disposed on the top surface of the first bump layer as claimed in amended Claim 1 of this application while Seo's bump structure 140 is different from Abe's stud bump 43A in structure. Seo discloses the bump structure 140 of the stacked structure, whereas Abe discloses the stud bump 43A in the peripheral structure. The applicant believes that Seo in view of Abe will cause Seo changing the principle of operation thereof, and thus, fails to teach the amended claim 1.
The Examiner responds:
In response to applicant’s arguments against Seo and Abe, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Applicant’s response to the 35 U.S.C. 103 rejections under Seo appear to solely address Abe and fail to incorporate Motoyoshi and Meyyeppan, as was written in the initial rejection.
Nevertheless, these arguments are not persuasive because they are based on a mischaracterization of the rejection. The rejection does not rely on Abe to teach a resin substrate substituting Seo’s substrate. The rejection regarding the substrate is specifically to teach that chips of semiconductor material perform suitably as substrates for bump structures, wherein Seo already teaches semiconductor-material substrates to be compatible with Seo’s device (see, e.g., Seo: par.0022/ll.3-6), and wherein Abe further teaches that such modification would be incentivized as such chip substrates can facilitate forming high frequency modules designed for high frequency applications (see, e.g., Abe: pars.0003/ll.1-5, 0049/ll.1-2, and 0051). Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Seo’s semiconductor substrate constitute a chip, as taught by Abe, because these were recognized as equivalents in the semiconductor art, and so as to facilitate and expand the high frequency applications of Seo’s device.
Furthermore, Seo, the primary reference, already teaches a bump structure. Specifically, Seo (see, e.g., fig. 3) discloses a bump structure 140 including a first bump layer 142 and a second bump layer 146. Accordingly, the presence of a chip-based substrate in Abe has no bearing on these features since they are already taught or suggested by Seo alone. Subsequently, the substrate modification suggested by Abe would not alter Seo’s bump structure, which is necessary for the functionality of Seo’s device that already supports the use of semiconductor-based substrates. Thus, the combination of Abe and Seo would have yielded the claimed configuration, with predictable results.
Additionally, the 35 U.S.C. 103 rejections over Seo do not rely on Abe for any limitations directed to the overall physical disposition of the bump, and the 35 U.S.C. 103 rejections over Seo further do not rely Abe alone regarding any limitations concerning the bump at all. Seo, the primary reference, already teaches a bump structure. Specifically, Seo (see, e.g., fig. 3 and par.0031/ll.1-3) discloses a bump structure 140 including a first bump layer 142 and a second bump layer 146, wherein the hardness of said first bump layer is different from the hardness of said second bump layer. Abe instead, alongside Motoyoshi and Meyyappan, is relied on solely to teach that the materials of bump layers may be the same or may differ, that differences in the hardness of bump layers may be achieved through the use of both same materials and different materials, and that such differences in materials would result in no unexpected changes in the performance of the bump structure. Accordingly, the incorporation of Abe, alongside Motoyoshi and Meyyappan, does not result in changing the principle of operation of Seo, as Seo already teaches the bump structure shape/disposition primarily relied on in the rejection. Even so, it is observed that the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
As stated, Abe is not relied on to change the structure of Seo’s bump structure from the physical disposition or shape illustrated in Seo to the structure illustrated in Abe. Rather, Abe, Motoyoshi, and Meyyappan are only relied on to teach that first and second bump layers formed of the same material function equivalently to first and second bump layers formed from different materials (see, e.g., Abe: fig. 7, pars.0044/ll.16-17, 0045/ll.1, and 0070, and claims 7-8 and Motoyoshi: see, e.g., pars.0062-0063). Meyyappan even provides incentive for modification to have the same material, teaching that when the layers of a bump structure are formed from a same conductive material that an affinity between the layers is ensured and the layers more easily form an electrical connection (see, e.g., Meyyappan: par.0031/ll.5-8). It is again noted that Applicant’s response to the 35 U.S.C. 103 rejections under Seo appear to solely address Abe and fail to incorporate Motoyoshi and Meyyeppan, as was written in the initial rejection.
Abe and Motoyoshi are evidence showing that one of ordinary skill in the art would appreciate that having the materials of a first bump layer and a second bump layer be the same conductive material would be equivalent to having the materials of a first bump layer and a second bump layer be different conductive materials, and that such differences would result in no unexpected changes in the performance of the bump structure of Seo. That is, the materials of both Seo’s and Abe’s or Motoyoshi’s bump layers would yield the predictable result of suitably forming layers in a bump structure with differing individual hardness levels. Furthermore, Meyyappan is evidence showing that one of ordinary skill in the art would appreciate that there is incentive to form the first and second bump layers of a bump structure from the same material, so as to ensure an affinity between the bump layers and more easily form an electrical connection between them.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either the materials of a first bump layer and a second bump layer be the same conductive material, as taught by Abe and Motoyoshi, or the materials of a first bump layer and a second bump layer be different conductive materials, as taught by Seo, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of suitably forming layers in a bump structure with differing individual hardness levels. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007). Furthermore, in light of Meyyappan, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the materials of Seo’s first bump layer and second bump layer be the same conductive material, as taught by Meyyappan, so as to ensure an affinity between Seo’s bump layers and to more easily form an electrical connection between Seo’s bump layers.
Accordingly, Applicant’s arguments do not overcome the prima facie case of obviousness, and the rejection under 35 U.S.C. § 103 is therefore maintained.
Applicant’s amendments to the specification, drawings, and claims have overcome the objections to the specification and drawings put forth in the previous Office action mailed on 12/03/2025. Accordingly, the objections to the specification, drawings, and claims put forth in the previous Office action are hereby withdrawn.
Applicant’s other arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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