Attorney Docket Number: 69620-108
Filing Date: 05/26/2023
Claimed Priority Date: 05/26/2022 (PRO 63/365,342)
Inventor: Tseng
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the election filed on 11/13/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Elections/Restrictions
Applicant’s election without traverse of Invention I, reading on a semiconductor device, and Species 3, reading on figure 5, in the reply filed on 11/13/2025, is acknowledged. Lines 19-22 of page 2 and line 9 of page 3 of the “Applicant Arguments/Remarks Made in an Amendment” REM document filed by the applicant on 11/13/2025 are interpreted by the examiner to mean that the applicant regards claims 1-10 as reading on the elected invention and elected species. The examiner agrees. Accordingly, claims 11-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected invention and/or species, there being no allowable generic or linking claim.
Drawings
Quotes from the specification are from the published application US 2024/0347491.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character not mentioned in the description: A3 (see, e.g., figure 6E).
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "6I" and "61" have both been used to designate the figure directly following figure 6H (see, e.g., fig. 6I and par.0042/ll.1).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Quotes from the specification are from the published application US 2024/0347491.
The disclosure is objected to because of the following informalities:
In par.0019/ll.18, “the first bump layer 322 with lower harness” should read “the first bump layer 322 with lower hardness”
Appropriate correction is required. No new matter should be added.
Claim Objections
The claims are objected to because of the following informalities:
In claim 6/ll.2, “said at least one metal layer is located of said chip” should read “said at least one metal layer is located on said chip”
Appropriate correction is required. No new matter should be added.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 4 is rejected under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 4 recites the limitation “the hardness of said bump buffer layer away from said first bump layer”. No particular or specific “bump buffer layer” has been previously recited or “said” to be located away from the first bump layer. Accordingly, there is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation “the hardness of said bump buffer layer close to said first bump layer”. No particular or specific “bump buffer layer” has been previously recited or “said” to be close to the first bump layer. Accordingly, there is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 5-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Abe (US 2007/0222085).
Regarding claim 1, Abe (see, e.g., fig. 7) shows all aspects of the instant invention, including a bump structure 43A, disposed on a chip 51, comprising:
a first bump layer 42A, disposed on said chip; and
a second bump layer 42a, disposed on said first bump layer
wherein:
the materials of said first bump layer 42A and said second bump layer 42a are the same conductive material (e.g., Gold or “Au”) (see, e.g., pars.0044/ll.16-17 and 0045/ll.1); and
the hardness of said first bump layer is different from the hardness of said second bump layer (see, e.g., pars.0025, 0035/ll.5-7, 0044/ll.16-18, and 0045/ll.1-3)
Regarding claim 5, Abe (see, e.g., pars.0025, 0035/ll.5-7, 0044/ll.16-18, and 0045/ll.1-3) shows that the hardness of said first bump layer 42A is smaller than the hardness of said second bump layer 42a.
Regarding claim 6, Abe (see, e.g., fig. 7 and par.0049/ll.3) shows that said first bump layer 42A is located on at least one metal layer 52A, and said at least one metal layer is located on said chip 51.
Regarding claim 7, Abe (see, e.g., fig. 7) shows that said first bump layer 42A is located on a passivation layer 53, said passivation layer is located on a contact pad 53A, and said contact pad is located on said chip 51 and contacting said chip.
Regarding claim 8, Abe (see, e.g., fig. 7 and par.0049/ll.3) shows that said first bump layer 42A is located on at least one metal layer 52A, and said at least one metal layer is located on said passivation layer 53. Furthermore, although Abe does not explicitly specify that layer 53A is metal, Abe teaches metals, such as gold and copper, to be suitable material for forming similar such layers (see, e.g., pars.0003/ll.9 and 0015/ll.6). Therefore, Abe shows again that said first bump layer 42A is located on at least one metal layer 53A, and said at least one metal layer is located on said passivation layer 53.
Regarding claim 9, Abe (see, e.g., figs. 5 and 7) shows that said passivation layer 53 has an opening, and said contact pad 53A and said first bump layer 42A correspond to said opening.
Regarding claim 10, Abe (see, e.g., fig. 7 and par.0049/ll.3) shows that said first bump layer 42A is located on at least one metal layer 52A, said at least one metal layer corresponds to said opening, and said at least one metal layer is located on and contacts said contact pad 53A.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Seo (US 2020/0075524) in view of Abe, Motoyoshi (US 2021/0399184), and Meyyappan (US 2023/0187337).
Regarding claim 1, Seo (see, e.g., fig. 3) shows most aspects of the instant invention, including a bump structure 140, disposed on a substrate 110, comprising:
a first bump layer 142, disposed on said substrate 110; and
a second bump layer 146, disposed on said first bump layer
wherein:
the materials of said first bump layer 142 and said second bump layer 146 are conductive material (see, e.g., pars.0026/ll.15-16 and 0059/ll.6-7); and
the hardness of said first bump layer is different from the hardness of the second bump layer (see, e.g., par.0031/ll.1-3)
Although Seo shows most aspects of the instant invention, and further specifies that Seo’s substrate may include semiconductor material (see, e.g., par.0022/ll.3-6), Seo fails to specify that Seo’s substrate is a chip. Abe, in the same field of endeavor, teaches that chips of semiconductor material perform suitably as substrates for bump structures, and that such chips can facilitate forming high frequency modules designed for high frequency applications (see, e.g., Abe: pars.0003/ll.1-5, 0049/ll.1-2, and 0051).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Abe’s semiconductor substrate constitute a chip, as taught by Abe, because these were recognized as equivalents in the semiconductor art, and so as to facilitate and/or expand the high frequency applications of Seo’s device.
Furthermore, although Seo shows most aspects of the instant invention, including that materials of the first and second bump layers are conductive material, Seo fails to specify that the materials of said first bump layer and said second bump layer are the same conductive material. Abe, in the same field of endeavor, teaches a similar bump structure to Seo, showing a bump structure 43A having a first bump layer 42A of a first conductive material and a second bump layer 42a of a second conductive material (see, e.g., pars.0044/ll.16-17 and 0045/ll.1). Abe teaches that the bump structure performs equally well regardless of whether the materials of said first bump layer and said second bump layer are the same conductive material or different conductive materials, so long as the first and second bump layers have different hardnesses, which can be ensured even with different first and second bump layer conductive materials (see, e.g., Abe: fig. 7, pars.0044/ll.16-17, 0045/ll.1, and 0070, and claims 7-8). Additionally, Motoyoshi, also in the same field of endeavor, teaches a bump structure having a first bump layer of a first conductive material and a second bump layer of a second conductive material, wherein the first conductive material may be the same as or may be different from the second conductive material and wherein the first and second bump layers have different hardnesses (see, e.g., Motoyoshi: pars.0062-0063). Motoyoshi, like Abe, teaches that as long as the first and second bump layers have different hardnesses, the bump structure performs as desired regardless of whether the materials of said first and second bump layers are the same conductive material or different conductive materials (see, e.g., Motoyoshi: pars.0062-0063). Moreover, Meyyappan, in the same field of endeavor as Seo, teaches that when the layers of a bump structure are formed from a same conductive material, an affinity between the layers is ensured and the layers more easily form an electrical connection (see, e.g., Meyyappan: par.0031/ll.5-8).
Abe and Motoyoshi are evidence showing that one of ordinary skill in the art would appreciate that having the materials of a first bump layer and a second bump layer be the same conductive material would be equivalent to having the materials of a first bump layer and a second bump layer be different conductive materials, and that such differences would result in no unexpected changes in the performance of the bump structure of Seo. That is, the materials of both Seo’s and Abe’s or Motoyoshi’s bump layers would yield the predictable result of suitably forming layers in a bump structure with differing individual hardness levels. Furthermore, Meyyappan is evidence showing that one of ordinary skill in the art would appreciate that there is incentive to form the first and second bump layers of a bump structure from the same material, so as to ensure an affinity between the bump layers and more easily form an electrical connection between them.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either the materials of a first bump layer and a second bump layer be the same conductive material, as taught by Abe and Motoyoshi, or the materials of a first bump layer and a second bump layer be different conductive materials, as taught by Seo, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of suitably forming layers in a bump structure with differing individual hardness levels. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007). Furthermore, in light of Meyyappan, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the materials of Seo’s first bump layer and second bump layer be the same conductive material, as taught by Meyyappan, so as to ensure an affinity between Seo’s bump layers and to more easily form an electrical connection between Seo’s bump layers.
Regarding claim 2, Seo (see, e.g., fig. 3 and pars.0026/ll.18-20, 0029/ll.4-6, 0030/ll.3-4, and 0031) shows that:
at least one bump buffer layer 144 is disposed between said first bump layer 142 and said second bump layer 146;
the materials of said first bump layer and said second bump layer are the same conductive material (see the comments stated above in paragraphs 30-32, which are considered to be repeated here); and
the hardness of said at least one bump buffer layer is different from the hardness of said first bump layer and said second bump layer
Although Seo/Abe/Motoyoshi/Meyyappan shows most aspects of the instant invention, including that the materials of said first bump layer and said second bump layer are the same conductive material (see the comments stated above in paragraphs 30-32, which are considered to be repeated here), Seo fails to specify that the material of said at least one bump buffer layer is the same conductive material as that of the first and second bump layers. Meyyappan, in the same field of endeavor as Seo, teaches that when the layers of a bump structure are formed from a same conductive material, an affinity between the layers is ensured and the layers more easily form an electrical connection (see, e.g., Meyyappan: par.0031/ll.5-8)
Therefore, it would have been obvious at the time of filing the invention to have all the bump layers of Seo’s device, that is – the first bump layer, the second bump layer, and the at least one bump buffer layer, be the same conductive material, as taught by Meyyappan, so as to ensure an affinity between the layers of Seo’s bump structure and to more easily form an electrical connection between the layers of Seo’s bump structure. See also the comments stated above in paragraphs 30-32 regarding the equivalency and interchangeability of materials in differing hardness layers of a bump structure, which are considered to be repeated here as applied to Seo’s at least one bump buffer layer.
Additionally, for the sake of clarity of the record, it is noted that specific claim limitation that the layer disposed between the first bump layer and the second bump layer is a bump buffer layer is a property of the device of Seo/Abe/Motoyoshi/Meyyappan.
Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See also Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
In the instant case, Seo teaches the same layers in a bump structure comprising different hardnesses as recited in the claim, therefore, the layer disposed between the first bump layer and the second bump layer will have the “buffer” property also recited in the claim.
Regarding claim 3, Seo (see, e.g., fig. 3 and pars.0026/ll.18-20, 0029/ll.4-6, 0030/ll.3-4, and 0031) shows that the hardness of said first bump layer 142 is smaller than the hardness of said at least one bump buffer layer 144, and the hardness of said at least one bump buffer layer is smaller than the hardness of said second bump layer 146.
Regarding claim 4, Seo (see, e.g., figs. 3 and 17 and par.0065/ll.1-2) shows that:
said at least one bump buffer layer 144 includes a plurality of bump buffer layers 147, 148;
the hardness of said first bump layer 142 is smaller than the hardness of said bump buffer layers 147, 148 (i.e., 144) (see, e.g., pars.0026/ll.18-20, 0029/ll.4-6); and
the hardness of said bump buffer layers 147, 148 (i.e., 144) is smaller than the hardness of said second bump layer 146 (see, e.g., par.0030/ll.3-4)
Although Seo fails to explicitly specify that the hardness of said bump buffer layers decreases stepwise while approaching said first bump layer and that the hardness of a bump buffer layer 147 most away from said first bump layer is greater than the hardness of a bump buffer layer 148 closest to said first bump layer, Seo teaches that when layers in a bump structure comprise a stepwise hardness decrease such that the bottommost layer has the smallest hardness, that potential delamination of the bottommost layer may be mitigated or prevented (see, e.g., figs. 3 and 17 and par.0031). Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the hardness of Seo’s said bump buffer layers decrease stepwise while approaching Seo’s first bump layer (i.e., approaching the bottommost layer), which inherently subsequently results in the hardness of the bump buffer layer most away from Seo’s first bump buffer layer being greater than the hardness of the bump buffer layer closest to Seo’s first bump layer, so as to mitigate or prevent delamination of the bump buffer layer closest to Seo’s first bump layer (i.e., Seo’s bottommost bump buffer layer 148).
Regarding claim 5, Seo (see, e.g., fig. 3 and par.0031/ll.1-3) shows that the hardness of said first bump layer 142 is smaller than the hardness of said second bump layer 146.
Regarding claim 6, Seo (see, e.g., fig. 3) shows that said first bump layer 142 is located on at least one metal layer 130, and said at least one metal layer is located on said chip 110 (see paragraphs 27-29 above regarding “said chip”, wherein the comments stated there are considered to be repeated here).
Regarding claim 7, Seo (see, e.g., fig. 3) shows that said first bump layer 142 is located on a passivation layer 122, said passivation layer is located on a contact pad 120, and said contact pad is located on said chip 110 and contacting said chip (see paragraphs 27-29 above regarding “said chip”, wherein the comments stated there are considered to be repeated here).
Regarding claim 8, Seo (see, e.g., fig. 3) shows that said first bump layer 142 is located on at least one metal layer 130, and said at least one metal layer is located on said passivation layer 122.
Regarding claim 9, Seo (see, e.g., fig. 3) shows that said passivation layer 122 has an opening, and said contact pad 120 and said first bump layer 142 correspond to said opening.
Regarding claim 10, Seo (see, e.g., fig. 3) shows that said first bump layer 142 is located on at least one metal layer 130, said at least one metal layer corresponds to said opening, and said at least one metal layer is located on and contacts said contact pad 120.
Conclusion
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814