DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 & 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over (US-9,620,488) by Yu et al (“Yu”) in view of (US-2020/0161218) by Shank et al (“Shank”).
Regarding claim 1, Yu discloses in FIG. 1F and related text, e.g., a semiconductor structure, comprising:
a first wafer (100, etc.), comprising a first substrate (100) and a first dielectric layer (107, 122, etc.) on the first substrate, wherein a plurality of through-silicon via (TSV) structures (118) in an array arrangement (“at least one through substrate via (TSV) 118”; thus, at least 2 are explicitly taught; thus making it a 2 by 1 array, by definition; thus meeting limitations) are formed in the first substrate, and the TSV structures extend through the first substrate along a direction from the first substrate to the first dielectric layer (see FIG. 1F) and extend into a partial thickness of the first dielectric layer (see FIG. 1F).
Yu does not disclose “an isolation ring structure, arranged in the first substrate surrounding a periphery of the plurality of TSV structures in the array arrangement and extending through the first substrate along the direction from the first substrate to the first dielectric layer, wherein the isolation ring structure electrically isolates the plurality of TSV structures from a remainder of the first substrate”.
Shank discloses in FIGs. 2-3 & 3A-B and related text, e.g., “an isolation ring structure (“isolation ring structure” (made of DTI’s 450b/450c) is best seen in FIG. 3; both 450b and 450c form complete DTI “isolation rings structures”), arranged in the first substrate (FIG. 2, 100; Abstract: “The deep trench isolation structures may extend partially or entirely through the substrate”) surrounding a periphery of the plurality of TSV structures (best seen in FIG. 3; 450b/450c surround plurality of 750’s) in the array arrangement (best seen in FIG. 3; a 2x1 array of TSVs 750 is shown) and extending through the first substrate (Abstract says that they pass through entire substrate, as was cited above) along the direction from the first substrate (100) to the first dielectric layer (FIG. 2; both 820 at the bottom and 470 at the top, read on limitations), wherein the isolation ring structure electrically isolates the plurality of TSV structures from a remainder of the first substrate (see FIG. 2 and 3; the combination shows the complete isolation is taught).”
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Yu with “an isolation ring structure, arranged in the first substrate surrounding a periphery of the plurality of TSV structures in the array arrangement and extending through the first substrate along the direction from the first substrate to the first dielectric layer, wherein the isolation ring structure electrically isolates the plurality of TSV structures from a remainder of the first substrate” as taught by Shank, in order to provide for “adequate isolation” of TSVs (par. 6).
Regarding claim 2, the combined device of Yu and Shank disclose in cited figures and related text, e.g., wherein the semiconductor structure comprises a plurality of isolation ring structures (at least 3 are shown in FIG. 3).
Regarding claim 12, the combined device of Yu and Shank disclose in cited figures and related text, e.g., further comprising: a second wafer (Yu, FIG. 1F, 200, etc.), bonded to the first wafer and comprising a second substrate (200) and a second dielectric layer (202, 208, etc.) on the second substrate, wherein the second dielectric layer faces the first dielectric layer (see FIG. 1F).
Regarding claim 13, the combined device of Yu and Shank disclose in cited figures and related text, e.g., wherein the first wafer further comprises: a first interconnecting structure (various 123/125/131, etc.), arranged in the first substrate (problem; “first interconnecting structure” is in “first wafer” in Applicant’s disclosure, not in “first substrate” [Wingdings font/0xE0] substrate is a semiconductor; there is no “interconnecting structure” in it, by definition; it is in the overall wafer, which includes both the “first substrate” and “interconnecting structure”; Examiner will play along with Applicant’s wording in the claim, but, Applicant is advised to fix it before allowance; for purposes of rejection, Yu has whatever it is that Applicant claims [Wingdings font/0xE0] various 123/125/131, etc.) and electrically connected to the TSV structure (see FIG. 1F); and
a first bonding and interconnecting layer (138), arranged in the first substrate above the first interconnecting structure (problem; this is the same issue as directly above; please fix before allowance; Examiner will play along with Applicant’s wording in the claim, but, Applicant is advised to fix it before allowance; for purposes of rejection, Yu has whatever it is that Applicant claims [Wingdings font/0xE0] 138 is exactly where it needs to be) and electrically connected to the first interconnecting structure and the second wafer (see FIG. 1F).
Regarding claim 14, the combined device of Yu and Shank disclose in cited figures and related text, e.g., wherein the second wafer further comprises: a second interconnecting structure (206), arranged in the second substrate (same issue as above, regarding claim 13; “interconnecting structure” in “second substrate”? again, please fix before allowance; Examiner will play along with Applicant’s wording in the claim, but, Applicant is advised to fix it before allowance; for purposes of rejection, Yu has whatever it is that Applicant claims [Wingdings font/0xE0] 206 is exactly where it needs to be); and
a second bonding and interconnecting layer (210), arranged in the second substrate (problem; this is the same issue as directly above; please fix before allowance; Examiner will play along with Applicant’s wording in the claim, but, Applicant is advised to fix it before allowance; for purposes of rejection, Yu has whatever it is that Applicant claims [Wingdings font/0xE0] 210 is exactly where it needs to be) above the second interconnecting structure and electrically connected to the second interconnecting structure and the first bonding and interconnecting layer (see FIG. 1F).
Regarding claim 15, the combined device of Yu and Shank disclose in cited figures and related text, e.g., further comprising: a passivation layer (148 reads on the limitation), arranged on a surface of the first substrate facing away from the first dielectric layer; and a pad structure (146, 150), arranged in the passivation layer and electrically connected to the TSV structure (see FIG. 1F).
Regarding claim 16, the combined device of Yu and Shank disclose in cited figures and related text, e.g., substantially the entire claim structure, as recited in above claims, except wherein a material of the passivation layer comprises at least one of silicon oxide, silicon nitride, or a high-k dielectric material.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the device of Yu and Shank with “wherein a material of the passivation layer comprises at least one of silicon oxide, silicon nitride, or a high-k dielectric material”, since these are notoriously well-known materials for forming passivation layers, and are notoriously well-known to be suited for this purpose.
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Alexander Belousov/Patent Examiner, Art Unit 2894
06/28/26
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights