DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3-11, 13-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
To elaborate briefly on the above, the Applicant, starting in claim 3, recites a combination of “shallow trench isolation structure” (STI) and “deep trench isolation structure” (DTI). Applicant’s drawings do not describe STIs at all. There are some structures that can be interpreted as DTIs, but not the STIs. Examiner has no idea of spatial relationship between the STIs and DTIs. Is one on top and the other on the bottom? Which one? Are they overlapping? Examiner has no idea. Therefore, in examination of claims 3-11, Examiner has no clue what structure to search for. In prior art rejections below, Examiner will make further comments, as appropriate on each of the claims in question.
Furthermore, claims 13-14 contradict Applicant’s explicit disclosure. See prior art rejections below for detailed explanations.
Drawings
The subject matter of this application admits of illustration by a drawing to facilitate understanding of the invention. Applicant is required to furnish a drawing under 37 CFR 1.81(c). No new matter may be introduced in the required drawing. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d).
The drawings are not of sufficient quality to permit examination. Accordingly, replacement drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to this Office action. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action.
Applicant is given a shortened statutory period of TWO (2) MONTHS to submit new drawings in compliance with 37 CFR 1.81. Extensions of time may be obtained under the provisions of 37 CFR 1.136(a) but in no case can any extension carry the date for reply to this letter beyond the maximum period of SIX MONTHS set by statute (35 U.S.C. 133). Failure to timely submit replacement drawing sheets will result in ABANDONMENT of the application.
New corrected drawings in compliance with 37 CFR 1.121(d) are required in this application because of the issues explained in great detail in various 112 and prior art rejections. See the 112 and prior art rejections for detailed explanations. Applicant is advised to employ the services of a competent patent draftsperson outside the Office, as the U.S. Patent and Trademark Office no longer prepares new drawings. The corrected drawings are required in reply to the Office action to avoid abandonment of the application. The requirement for corrected drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-10 and 12-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by (US-9,620,488) by Yu et al (“Yu”).
Regarding claim 1, Yu discloses in FIG. 1F and related text, e.g., a semiconductor structure, comprising:
a first wafer (100, etc.), comprising a first substrate (100) and a first dielectric layer (107, 122, etc.) on the first substrate, wherein a plurality of through-silicon via (TSV) structures (118) in an array arrangement (“at least one through substrate via (TSV) 118”; thus, at least 2 are explicitly taught; thus making it a 2 by 1 array, by definition; thus meeting limitations) are formed in the first substrate, and the TSV structures extend through the first substrate along a direction from the first substrate to the first dielectric layer (see FIG. 1F) and extend into a partial thickness of the first dielectric layer (see FIG. 1F); and
an isolation ring structure (contains 142, 144, 148 on the sides of the device), arranged in the first substrate around the plurality of TSV structures (it is shown around one; thus, per explicit teachings, it will also be present around the second one) and extending through the first substrate along the direction from the first substrate to the first dielectric layer (compare FIGs. 1A and FIG. 1B; specific removal of substrate and first dielectric layer is explicitly shown; thus meeting limitations).
Regarding claim 2, Yu discloses in FIG. 1F and related text, e.g., wherein the semiconductor structure comprises a plurality of isolation ring structures (such arrangement is at the very least obvious in light of explicit teachings; since it is taught around one 118, thus it is at the very least obvious to make it around another one).
Regarding claim 3, Yu discloses in FIG. 1F and related text, e.g., wherein the isolation ring structure comprises: a first deep trench isolation structure (either to the left or to the right of 118; contains 142/144/148); or a shallow trench isolation structure and a second deep trench isolation structure on the shallow trench isolation structure (Examiner has no clue what these limitations mean; they are not present in Applicant’s drawings; please provide a drawing of STI and DTI in question, with proper reference numerals, so Examiner would know what to search for).
Regarding claim 4, Yu discloses in FIG. 1F and related text, e.g., wherein the first deep trench isolation structure comprises a first deep trench, a first isolation layer on a bottom and a sidewall of the first deep trench, and a first isolation material layer on the first isolation layer and filling the first deep trench (Examiner has no clue what these limitations mean; they are not present in Applicant’s drawings; please provide a drawing of STI and DTI in question, with proper reference numerals, so Examiner would know what to search for; please note that “a first isolation layer” is recited twice; this is a 112, 2nd issue, in addition to 112, 1st issues).
Regarding claim 5, Yu discloses in FIG. 1F and related text, e.g., wherein a material of the first isolation layer comprises at least one of silicon oxide, silicon nitride, or a high-k dielectric material (142/144/148 can be formed from the above materials).
Regarding claim 7, Yu discloses in FIG. 1F and related text, e.g., wherein a material of the shallow trench isolation structure comprises a shallow trench and a second isolation material layer in the shallow trench (Examiner has no clue what these limitations mean; they are not present in Applicant’s drawings; please provide a drawing of STI and DTI in question, with proper reference numerals, so Examiner would know what to search for).
Regarding claim 8, Yu discloses in FIG. 1F and related text, e.g., wherein a material of the second isolation material layer comprises silicon oxide (142/144/148 can be formed from the above materials; also, Examiner has no clue what these limitations mean; where in Applicant’s drawings is “second isolation material layer” located?).
Regarding claim 9, Yu discloses in FIG. 1F and related text, e.g., wherein the second deep trench isolation structure comprises a second deep trench, a second isolation layer on a bottom and a sidewall of the second deep trench, and a third isolation material layer on the second isolation layer and filling the second deep trench (Examiner has no clue what these limitations mean; they are not present in Applicant’s drawings; please provide a drawing of STI and DTI in question, with proper reference numerals, so Examiner would know what to search for).
Regarding claim 10, Yu discloses in FIG. 1F and related text, e.g., wherein a material of the second isolation layer comprises at least one of silicon oxide, silicon nitride, or a high-k dielectric material (142/144/148 can be formed from the above materials; also, Examiner has no clue what these limitations mean; where in Applicant’s drawings is “second isolation material layer” located?).
Regarding claim 12, Yu discloses in FIG. 1F and related text, e.g., further comprising: a second wafer (200, etc.), bonded to the first wafer and comprising a second substrate (200) and a second dielectric layer (202, 208, etc.) on the second substrate, wherein the second dielectric layer faces the first dielectric layer (see FIG. 1F).
Regarding claim 13, Yu discloses in FIG. 1F and related text, e.g., wherein the first wafer further comprises: a first interconnecting structure (various 123/125/131, etc.), arranged in the first substrate (problem; they are in first wafer in Applicant’s disclosure, not in first substrate; Yu’s 123/125/131 are in first wafer) and electrically connected to the TSV structure (see FIG. 1F); and
a first bonding and interconnecting layer (138), arranged in the first substrate above the first interconnecting structure (problem; they are in first wafer in Applicant’s disclosure, not in first substrate; Yu’s 138 are in first wafer; they are also below and not above in Applicant’s disclosure) and electrically connected to the first interconnecting structure and the second wafer (see FIG. 1F).
Regarding claim 14, Yu discloses in FIG. 1F and related text, e.g., wherein the second wafer further comprises: a second interconnecting structure (206), arranged in the second substrate (in wafer, not in substrate); and
a second bonding and interconnecting layer (210), arranged in the second substrate (in wafer, not in substrate) above the second interconnecting structure and electrically connected to the second interconnecting structure and the first bonding and interconnecting layer (see FIG. 1F).
Regarding claim 15, Yu discloses in FIG. 1F and related text, e.g., further comprising: a passivation layer (148 reads on the limitation), arranged on a surface of the first substrate facing away from the first dielectric layer; and a pad structure(146, 150), arranged in the passivation layer and electrically connected to the TSV structure (see FIG. 1F).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 11, 16 are rejected under 35 U.S.C. 103 as being unpatentable over (US-9,620,488) by Yu et al (“Yu”).
Regarding claim 6, Yu discloses in FIG. 1F and related text, e.g., substantially the entire claim structure, as recited in above claims, except wherein the first isolation material layer comprises at least one of polysilicon, copper, or tungsten.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Yu with “wherein the first isolation material layer comprises at least one of polysilicon, copper, or tungsten”, since these are notoriously well-known materials for forming deep trench isolation structures, and are notoriously well-known to be suited for this purpose.
Regarding claim 11, Yu discloses in FIG. 1F and related text, e.g., wherein the third isolation material layer comprises at least one of polysilicon, copper, or tungsten (see rejection of claim 6; same logic applies).
Regarding claim 16, Yu discloses in FIG. 1F and related text, e.g., substantially the entire claim structure, as recited in above claims, except wherein a material of the passivation layer comprises at least one of silicon oxide, silicon nitride, or a high-k dielectric material.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Yu with “wherein a material of the passivation layer comprises at least one of silicon oxide, silicon nitride, or a high-k dielectric material”, since these are notoriously well-known materials for forming passivation layers, and are notoriously well-known to be suited for this purpose.
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
02/21/26
/Mounir S Amer/Primary Examiner, Art Unit 2818