DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/26/2023 is/are in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Response to Arguments
Applicant’s arguments, see pages 9-12 of argument, filed 12/03/2025, with respect to independent claims 1, 11 and 21 have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. No new claims were added. Claim 19 is cancelled
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 and 21-26 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Wei et al., herein referred to as Wei (US 20220367391) Fig. 3C
As to claim 1, a substrate (substrate 102/202, [0014], Wei) comprising:
a first insulating layer (210 +208 + 206, Fig. 3C, Wei);
a second insulating layer (110 + 108 + 106, Fig. 3C, Wei); disposed on the first insulating layer (208 + 206 Fig, 3C); and
a via hole (via opening 216, Fig. 3C, Wei); including a lower hole (Annotated lower hole, Fig. 3C, Wei) formed in the first insulating layer (208 +206), and
an upper hole (Annotated upper hole, Fig. 3C, Wei) formed in the second insulating layer (110 + 108 + 106, Fig. 3C, Wei) and connected to the lower hole (Annotated lower hole, Fig. 3C Wei) wherein
a width of an upper side (Annotated upper width (W1) of lower hole, Fig. 3C Wei) of the lower hole is larger than a width of a lower side (Annotated lower width (W2) of lower hole Fig. 3C, Wei) of the lower hole, and
a width of an upper side (Annotated upper width (W4) of upper hole, Fig. 3C Wei) of the upper hole is smaller than a width of a lower side of the upper hole (Annotated lower width (W3) of upper hole, Fig. 3C Wei).
and wherein the width of the upper side of the lower hole (W1) is equal to the width of the lower side of the upper hole (W3). (Annotated, Fig. 3C Wei)
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As to claim 2, Wei teaches the substrate of claim 1, as discussed above further comprising:
a lower conductive pattern (lower conduction pattern 204, Fig. 3C Wei) disposed at a lower portion of the first insulating layer (210 +208 + 206, Fig. 3C, Wei); and
an upper conductive pattern (upper conduction pattern 104, Fig. 3C Wei) disposed above the second insulating layer (110 + 108 + 106, Fig. 3C, Wei), wherein
the lower hole has a first width (Annotated lower hole (W2), Fig. 3C Wei) at a portion where the lower hole adjoins the lower conductive pattern (204), wherein
the via hole has a second width (Annotated lower hole, (W1 and or W3 ) Fig. 3C Wei) between the lower conductive pattern (204) and the upper conductive pattern (104), wherein
the upper hole (Annotated upper hole, Fig. 3C Wei) has a third width (W4) at a portion where the upper hole adjoins the upper conductive pattern (104), and wherein
each of the first width (W2) and the third width (W4) is smaller than the second width (Annotated W2, W4, (W1 and or W3) , Fig. 3C Wei).
As to claim 3, Wei teaches the substrate of claim 2, as discussed above wherein:
the second width is largest at an interface between the first insulating layer and the second insulating layer (Annotated W1 and W3, Fig. 3C Wei).
As to claim 4, Wei teaches the substrate of claim 2, as discussed above further comprising:
a connection conductive pattern (216) disposed in the via hole and connected to the lower conductive pattern (204 lower conduction pattern, Fig. 3C Wei) and the upper conductive pattern (104 upper conductive pattern, Fig. 3C Wei).
As to claim 5, Wei teaches the substrate of claim 1, as discussed above wherein:
a width of the lower hole increases from the lower side to the upper side of the lower hole (Annotated W2-W1, Fig. 3C Wei)., and
a width of the upper hole decreases from the lower side to the upper side of the upper hole (Annotated W4-W3, Fig. 3C Wei).
As to claim 21, Wei teaches a substrate (substrate 102/202, [0014], Wei) comprising:
at least one insulating layer (210, 208, 206, 202,110, 108, 106, 102 Fig. 3C, Wei) ;
a lower conductive pattern (204, Wei) and an upper conductive pattern (104, Wei) disposed at a lower portion (Annotated lower hole, Fig. 3C Wei) and an upper portion (Annotated upper hole, Fig. 3C, Wei) of the at least one insulating layer (210, 208, 206, 110, 108, 106, Fig. 3C, Wei), respectively; and
a connection conductive pattern (216/116) penetrating through the at least one insulating layer to be connected to the lower and upper conductive patterns (204/104), wherein
a width of a middle portion of the connection conductive pattern (width of connection conduction pattern 216/116, Wei) is larger than widths of upper and lower portions of the connection conductive patterns (width of 216/116 Fig. 3C, Wei) wherein
the connection conductive pattern (216/116 Fig. 3C) includes a lower connection conductive pattern and an upper connection conductive pattern extended from the lower connection conductive pattern, wherein
a width (W1) of an upper side of the lower connection conductive pattern is larger than a width (W2) of a lower side of the lower connection conductive pattern, and
a width (W4) of an upper side of the upper connection conductive pattern is smaller than a width (W3) of a lower side of the upper connection conductive pattern, and wherein
the width (W1) of the upper side of the lower connection conductive pattern is equal to the width (W3) of the lower side of the upper connection conductive pattern.
As to claim 22, Wei teaches the substrate of claim 21, as discussed above further comprising
a via hole (via opening 216/116, Fig. 3C2 Wei) in which the connection conductive pattern (216/116) is disposed, the via hole (via opening 216/116) including a lower hole and an upper hole connected to each other (Fig. 3C Wei), wherein
the at least one insulating layer comprises a first insulating layer and a second insulating layer stacked on one another (Fig. 3C Wei), and
the lower hole (Annotated lower hole, Fig. 3C Wei) is formed in the first insulating layer (210 +208 + 206, Fig. 3C, Wei) and the upper hole (Annotated upper hole, Fig. 3C Wei) is formed in the second insulating layer (110 + 108 + 106, Fig. 3C, Wei).
As to claim Wei teaches 23, the substrate of claim 22, as discussed above wherein
a width of the via hole (via opening where 216 meets 116, Fig. 3C, Wei) is largest at an interface between the first insulating layer (210) and the second insulating layer (110).
As to claim 24, Wei teaches the substrate of claim 21, as discussed above wherein
a largest width of the connection conductive pattern (via opening where 216 meets 116, Fig. 3C, Wei) is closer to an interface between the connection conductive pattern and the upper conductive pattern than an interface between the connection conductive pattern and the lower conductive pattern.
As to claim 25, Wei teaches the substrate of claim 21, as discussed above wherein
a width of the connection conductive pattern (via opening where 216 meets 116, Fig. 3C, Wei) at an interface between the connection conductive pattern and the upper conductive pattern is larger than a width of the connection conductive pattern at an interface between the connection conductive pattern and the lower conductive pattern.
As to claim 26, Wei teaches the substrate of claim 21, as discussed above wherein
the lower conductive pattern (204, Wei) is embedded in the lower portion of the at least one insulating layer (layers 206 -202, Wei), and
the upper conductive pattern (104, Wei) is disposed above the upper portion of the at least one insulating layer (106, Wei).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 9-10 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al., herein referred to as Wei (US 20220367391) Fig. 3C
As to claim 9, Wei teaches the substrate of claim 1, as discussed above further comprising:
a conductive film (layer 112 becomes layer 116 [0030], See Fig. 1G, Wei) disposed on the second insulating layer (110 + 108 + 106, Fig. 3C, Wei) , wherein deposition of seed layer (obvious)
the upper hole (Annotated upper hole, 3C, Wei) is formed in the second insulating layer (110 + 108 + 106, Fig. 3C, Wei) and the conductive film (116, Wei).
Wei does not appear to expressly disclose "a conductive film wherein there is a deposition of a seed layer "
However, It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, that the conductive material 112 as disclosed in [0030] of Wei is used in a plating process, which uses a copper seed layer.
The plating process in semiconductor manufacturing involves depositing metal layers onto semiconductor substrates to create conductive pathways essential for device functionality. Though not explicitly stated, the plating process of Wei is performed using a copper seed layer so as to use an industrially tested and accepted device/process/material.)
As to claim 10, Wei teaches the substrate of claim 9, as discussed above wherein:
a width of the upper hole (Annotated upper hole, Fig. 3C, Wei) formed in the conductive film (116, Wei) is not smaller than a width of the upper hole (Annotated upper hole, Fig. 3C, Wei) formed in the second insulating layer (110 + 108 + 106, Fig. 3C, Wei).
As to claim 27, Wei teaches the substrate of claim 21, as discussed above further comprising
a conductive film (layer 112 becomes layer 116 [0030], See Fig. 1G, Wei) disposed between the at least one insulating layer (210, 208, 206, 202,110, 108, 106, 102 Fig. 3C, Wei) and the upper conductive pattern (104, Wei).
Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al., herein referred to as Wei (US 20220367391) Fig. 3C in view of Yang et al., herein referred to as Yang (US 11205618) Figs. 2 and 7
As to claim 6, Wei teaches the substrate (102/202 Wei) of claim 5, as discussed above and further teaches the first insulating layer (210 +208 + 206, Fig. 3C, Wei);
Wei does not teach “the first insulating layer includes prepreg and is impregnated with fiberglass prepreg impregnated fiberglass. “
However, Yang does teach “the first insulating layer includes prepreg and is impregnated with fiberglass (Black Diamond® teaches prepreg impregnated fiberglass, col 6 line 56, Yang) prepreg impregnated fiberglass.“ Prepreg fiberglass (pre-impregnated fiberglass) is used in semiconductor insulating layers for its superior dielectric properties thermal stability, mechanical strength, and consistent quality, allowing for reliable, multi-layered circuits with precise impedance control and high performance.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the first insulating layer of the Wei device include prepreg impregnated fiberglass such as is used in the Yang device so as to use an industrially tested and accepted material.
As to claim 7, Wei and Yang as combined teach the substrate of claim 1, as discussed above wherein:
the first insulating layer (210 + 208 + 206, Fig. 3C, Wei) and the second insulating layer (110 + 108 + 106, Fig. 3C, Wei)
Wei does not teach “the first insulating layer includes a reinforcing material and the second insulating layer includes no reinforcing material.”
However, Yang does teach the first insulating layer (208 + 206, Fig. 3C, Wei) includes a reinforcing material (silicon nitride, col 6 lines 50-62, Yang) Reinforcing materials are used in the insulating layers of semiconductors primarily to provide structural integrity and mechanical support, enhance thermal management, and improve long-term reliability of the device.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the first insulating layer (210 +208 + 206, Fig. 3C, Wei) of the Wei device include prepreg impregnated fiberglass such as is used in the Yang device so as to use an industrially tested and accepted material.
Yang also teaches the second insulating layer (110 +108 + 106, Fig. 3C, Wei) includes no reinforcing material. (Xerogel and Aerogel are resins, col 6 line 57, Yang). Non-reinforcing (insulating) materials are used in semiconductor layers, like dielectrics, to electrically isolate components, prevent short circuits, control current flow (gate oxides), manage heat, and provide mechanical stability for delicate structures, ensuring signals stay clear and devices function reliably without interference or damage.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the second insulating layer of the Wei device include no reinforcing material such as is used in the Yang device so as to use an industrially tested and accepted material.
As to claim 8, Wei and Yang as combined teach the substrate of claim 1, as discussed above wherein:
the second insulating layer (110 + 108 + 106, Fig. 3C, Wei) includes resin.
Wei does not teach “the second insulating layer includes resin.”
However, Yang does teach the second insulating layer that includes a resin (Parylene, BCB, SILK, and polyimide are resins, col 6 line 58, Yang)
Reinforcing materials are used in the insulating layers of semiconductors primarily to provide structural integrity and mechanical support, enhance thermal management, and improve long-term reliability of the device. Resins are used in semiconductor insulation for their excellent electrical isolation, moisture/chemical resistance, mechanical strength, and adhesion, protecting delicate components from shorts, contaminants, and physical damage while enabling reliable, miniaturized packaging like interlayer dielectrics and encapsulants, crucial for device longevity and performance in demanding environments.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the second insulating layer of the Wei device include a resin, such as is used in the Yang device so as to use an industrially tested and accepted material.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al., herein referred to as Wei (US 20220367391) Fig. 3C in view of Cheng et al., herein referred to as Cheng (US-20230230849) Fig. 23.
As to claim 11, Wei teaches a method of manufacturing a substrate, the method as discussed above comprising:
stacking a first insulating layer (210 + 208 + 206, Fig. 3C, Wei);
forming a second insulating layer (110 + 108 + 106, Fig. 3C, Wei); on the first insulating layer 208 + 206, Fig. 3C, Wei);
wherein the forming of the via hole comprises forming a lower hole (via opening 216, Fig. 3C, Wei) in the first insulating layer and
an upper hole (via opening 116, Fig. 3C, Wei) in the second insulating layer to connect the upper and lower holes to each other, wherein
a width of an upper side of the lower hole is larger than a width of a lower side of the lower hole, and (Annotated , Fig. 3C Wei).
a width of an upper side of the upper hole is smaller than a width of a lower side of the upper hole, and wherein (Annotated , Fig. 3C Wei).
the width of the upper side of the lower hole is equal to the width of the lower side of the upper hole. (Annotated , Fig. 3C Wei) wherein
the forming of the via hole comprises forming a lower hole in the first insulating layer and an upper hole in the second insulating layer to connect the upper and lower holes to each other, (Fig. 3C Wei) wherein
a width (W1) of an upper side of the lower hole is larger than a width (W2) of a lower side of the lower hole, and
a width (W4) of an upper side of the upper hole is smaller than a width (W3) of a lower side of the upper hole, and wherein
the width (W1) of the upper side of the lower hole is equal to the width (W3) of the lower side of the upper hole.
Wei does not explicitly teach “forming a sub-hole by primarily removing the second insulating layer and the first insulating layer by emitting a first laser.”
However, Cheng does teach
forming a sub-hole by primarily removing the second insulating layer and the first insulating layer by emitting a first laser (¶ 0056, “performing the first laser sequences 302.sub.1, a second laser sequence 302.sub.2 is performed on the package region of the first package component 100”, Fig. 22-23, Cheng); and
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to form a sub-hole by primarily removing the second insulating layer and the first insulating layer by emitting a first laser such as is used in the Cheng device.
Fabricating sub holes through the use of a laser provides precise and efficient semiconductor manufacturing and is a well-known industrially tested and accepted process.
Wei does not explicitly teach “forming a via hole by secondarily removing the second insulating layer and the first insulating layer by emitting a second laser different from the first laser.”
However, Cheng does teach
forming a via hole by secondarily removing the second insulating layer and the first insulating layer by emitting a second laser different from the first laser (¶ 0056, “after performing the first laser sequences 302.sub.1, a second laser sequence 302.sub.2 is performed on the package region of the first package component 100”, Cheng).
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to form a sub-hole by primarily removing the second insulating layer and the first insulating layer by emitting a first laser such as is used in the Cheng device. Fabricating sub holes through the use of a laser provides precise and efficient semiconductor manufacturing and is a well-known industrially tested and accepted process.
Claim Rejections - 35 USC § 103
Claim(s) 12 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al. (US 20220367391) herein referred to as Wei, in view of Cheng et al. (US 20230230849) herein referred to as Cheng, in further view of Takenaka et al. herein referred to as Takenaka (US 20100006334).
As to claim 12, Wei and Cheng as combined teach the method of claim 11, as discussed above wherein there is a “the first laser” and “second laser”. The Wei /Cheng combination teaches the use of subsequent laser shots to remove portions of an insulating layer. Cheng does not teach the first laser as a YAG laser, and the second laser as a carbon dioxide gas laser. Wei and Chen as combined do not explicitly teach “the first laser is a YAG laser, and the second laser is a carbon dioxide gas laser.”
However, Takenaka does teach:
the first laser is a YAG laser, and the second laser is a carbon dioxide gas laser
(¶ 0136 , “Then, the same processes as above, first laser process and second laser process, are conducted on resin insulation layers (24U, 24L) to form via-conductor opening portions (17UVO, 17LVO) for interlayer connection, and conductive-circuit opening portions (17UO, 17LO) (see FIG. 6B). To form via-conductor opening portions (17UVO, 17LVO), any laser selected from among a group of carbon dioxide gas lasers, exima lasers and YAG lasers may be used.” Takenaka)
Takenaka teaches the use of a first laser process and a second laser process by a YAG laser and carbon dioxide gas laser. The use of different lasers to cut semiconductor materials depends on the material's unique physical properties, the desired cut quality, and the specific application. Key factors like a laser's wavelength, pulse duration, and power are adjusted to optimize how the laser energy interacts with the semiconductor’s physical properties.
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to equip the Wei/Cheng device with two different lasers as in the Takenaka device so as to minimize damage and ensure precision and accuracy when cutting two layers of different materials.
As to claim 14, the Wei/Chen/Takenaka combination teaches the method of claim 12, as discussed above and further comprising:
forming a lower conductive pattern (204, Wei) below the first insulating layer (210 + 208 +206, Wei);
forming a connection conductive pattern in the via hole (216, Wei), the connection conductive pattern being connected to the lower conductive pattern (204, Wei); and
forming an upper conductive pattern above the via hole (116, Wei), the upper conductive pattern being connected to the connection conductive pattern (104, Wei).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al., herein referred to as Wei (US 20220367391), in view of Cheng et al., herein referred to as Cheng (US 20230230849), further in view of Takenaka et al. herein referred to as Takenaka (US 20100006334), as discussed above and further in view of Sakamoto et al., herein referred to as Sakamoto (US 20090173530).
As to claim 15, Wei/Chen/Takenaka as combined teaches the method of claim 14, as discussed above, and the forming of the connection conductive pattern. Though not explicit, Wei discloses the limitations of claim 15, as discussed in claim 9 above. Nonetheless, Sakamoto explicitly describes the forming of the connection conductive pattern comprising:
stacking a plating seed layer on an upper surface of the lower conductive pattern and an inner wall of the via hole (¶ 0046 “The via conductor 32 and the second wiring 31 are formed with copper plating and a seed layer 131 underneath the copper plating, Sakamoto); and
performing plating by using the plating seed layer (“Next, as illustrated in FIG. 4 (b), using the seed layer 126 as an electricity supply layer, electrolytic-copper-plating is performed to form an electrolytic copper-plated layer 127. It will suffice to perform electrolytic copper-plating with a conventional method known to the public.”, Sakamoto).
(Regarding claim 15, the Wei/Cheng/ Takenaka combination teaches the teach the limitations of claim 15 as discussed in claim 9. However, Sakamoto explicitly discloses the stacking a plating seed layer and performing plating by using the plating seed layer. Sakamoto also teaches the stacking of a plating seed layer on an upper surface of the lower conductive pattern and an inner wall of the via hole, by using a plating seed layer. In semiconductor manufacturing, a stacked plating seed layer is used because different materials are required to provide the best adhesion, conductivity, and diffusion barrier properties during electroplating.
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to use the process of Sakamoto for stacking and plating, in the combined device of Wei/Cheng/ Takenaka, so as to allow for the formation of a robust, high-performance, and reliable plated metal feature; thereby improving adhesion, diffusion-barrier properties, and conductivity so as to use an industrially tested and accepted device or process.)
Allowable Subject Matter
Claims 13 and 16-20 are objected to as being dependent upon a rejected base claims, 12 and 15 but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art does not teach:
the forming of a conductive film on the second insulating layer, wherein the sub-hole and the via hole are formed in the conductive film.
a width of the lower hole increases from a lower side to an upper side of the lower hole, and a width of the upper hole decreases from a lower side to an upper side of the upper hole.
the fiberglass of the first insulating layer is processed in the emitting of the second laser.
Conclusion
13/03/2025THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
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/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897