Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1-5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Mok (PGPub No. 20050280162) in further view of Neal (PGPub No. 20200203256).
Regarding claim 1, Mok teaches a semiconductor device comprising: a semiconductor chip comprising a semiconductor integrated circuit (Fig. 6 points to an integrated circuit device comprising a semiconductor device 608 (integrated circuit) and a thermal interposer 602 (semiconductor chip).); and a cooling channel comprising: at least a first portion that is inside the semiconductor chip (Fig. 6 and [0068] point to thermal interposer 608 (semiconductor chip) comprising plates 604 and 606 which form a vapor chamber (cooling channel).); a wall surface comprising a fine pattern configured to generate a capillary force that causes a liquid coolant to flow in the cooling channel (Fig. 9 and [0010-11] point to an alternative embodiment comprising a vapor chamber 22 (cooling channel) with a bottom inner surface (wall surface) lined with a wick structure (fine pattern).); a liquid channel area in a first area of the cooling channel where the fine pattern is formed and configured to pass the liquid coolant (Id.); and a gas channel area in a second area of the cooling channel where the fine pattern is not formed and configured to pass a gaseous coolant (Fig. 9 points to the vapor chamber 22 comprising an open area (gas channel area) which allows the evaporated working fluid (coolant) to move away from the wick structure located along the bottom inner surface (fine pattern).).
Mok fails to teach a substrate on the semiconductor integrated circuit and having an upper surface comprising at least one opening in communication with an outside; wherein the liquid coolant is supplied into the substrate from the outside through the at least one opening of the upper surface of the substrate, and the gaseous coolant is discharged from the substrate to the outside through the at least one opening of the upper surface of the substrate.
Neal teaches a substrate on the semiconductor integrated circuit and having an upper surface comprising at least one opening in communication with an outside (Fig. 16 points to an integrated circuit package 190 comprising a substrate 100 on an integrated circuit device 180, the substrate 100 further comprising heat transfer fluid conduits 126 and 128 (at least one opening).); wherein the liquid coolant is supplied into the substrate from the outside through the at least one opening of the upper surface of the substrate, and the gaseous coolant is discharged from the substrate to the outside through the at least one opening of the upper surface of the substrate (Fig. 16 and [0039] point to a heat transfer fluid 120, which in certain embodiments may comprise two phases such as liquid-phase and gas-phase dielectric refrigerant.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Mok and Neal, such that a substrate is formed comprising a flow path by which coolant directly enters/leaves said substrate in order to allow for cooling within the substrate, which may significantly reduce thermal damage to the components of the substrate and/or integrated circuit devices within the substrate.
Regarding claim 2, Mok teaches wherein an entirety of the cooling channel is formed inside the semiconductor chip (Fig. 6 and [0068] point to thermal interposer 608 (semiconductor chip) comprising plates 604 and 606 which form a vapor chamber (cooling channel).).
Regarding claim 4, Mok teaches wherein the wall surface comprises a first wall surface extending in a transverse direction in the cooling channel and a second wall surface extending in a longitudinal direction from the first wall surface (Fig. 9 points to an alternative embodiment of a vapor chamber 22 (cooling channel) comprising a bottom inner surface (first wall surface) and sidewalls (second wall surface).), and wherein the fine pattern comprises: a first fine pattern formed on the first wall surface, and a second fine pattern formed on the second wall surface ([0010-11] point to a wick structure (fine pattern) lining the inside of the vapor chamber 22, including along the bottom inner surface (first fine pattern) and the sidewalls (second fine pattern).).
Regarding claim 5, Mok teaches wherein the first fine pattern is configured to generate a capillary force that moves the liquid coolant in the transverse direction along the first wall surface, and wherein the second fine pattern is configured to generate a capillary force that moves the liquid coolant in the longitudinal direction along the second wall surface and to the first wall surface ([0010-11] point to a wick structure lining the inside of the vapor chamber 22, including along the bottom inner surface (first fine pattern) and the sidewalls (second fine pattern).).
Regarding claim 14, Mok teaches a semiconductor device comprising: a semiconductor chip comprising a substrate and a semiconductor integrated circuit formed on the substrate (Fig. 6 points to an integrated circuit device comprising a semiconductor device 608 (integrated circuit) and a thermal interposer 602 (substrate).); and a cooling channel comprising: at least a first portion that is inside the semiconductor chip (Fig. 6 and [0068] point to thermal interposer 608 (substrate; semiconductor chip) comprising plates 604 and 606 which form a vapor chamber (cooling channel).), a first wall surface comprising a first fine pattern configured to generate a capillary force that moves a liquid coolant in a transverse direction, a second wall surface extending in a longitudinal direction from the first wall surface and comprising a second fine pattern configured to generate a capillary force that moves the liquid coolant in the longitudinal direction and supplies the liquid coolant to the first wall surface (Fig. 9 points to an alternative embodiment of a vapor chamber 22 (cooling channel) comprising a bottom inner surface (first wall surface) and sidewalls (second wall surface), which are each lined with a wick structure (first fine pattern; second fine pattern) which transports a working fluid (coolant).), a liquid channel area in a first area of the cooling channel where the first fine pattern and the second fine pattern are formed and configured to pass the liquid coolant (Id.), and a gas channel area in a second area of the cooling channel where the first fine pattern and the second fine pattern are not formed and configured to pass a gaseous coolant (Fig. 9 points to the vapor chamber 22 comprising an open area (gas channel area) which allows the evaporated working fluid (coolant) to move away from the wick structure located along the bottom inner surface (fine pattern).).
Mok fails to teach a substrate on the semiconductor integrated circuit and having an upper surface comprising at least one opening in communication with an outside; wherein the liquid coolant is supplied into the substrate from the outside through the at least one opening of the upper surface of the substrate, and the gaseous coolant is discharged from the substrate to the outside through the at least one opening of the upper surface of the substrate.
Neal teaches a substrate on the semiconductor integrated circuit and having an upper surface comprising at least one opening in communication with an outside (Fig. 16 points to an integrated circuit package 190 comprising a substrate 100 on an integrated circuit device 180, the substrate 100 further comprising heat transfer fluid conduits 126 and 128 (at least one opening).); wherein the liquid coolant is supplied into the substrate from the outside through the at least one opening of the upper surface of the substrate, and the gaseous coolant is discharged from the substrate to the outside through the at least one opening of the upper surface of the substrate (Fig. 16 and [0039] point to a heat transfer fluid 120, which in certain embodiments may comprise two phases such as liquid-phase and gas-phase dielectric refrigerant.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Mok and Neal, such that a substrate is formed comprising a flow path by which coolant directly enters/leaves said substrate in order to allow for cooling within the substrate, which may significantly reduce thermal damage to the components of the substrate and/or integrated circuit devices within the substrate.
Claim(s) 6-13 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mok et al. in further view of Suwada (PGPub No. 20160351471).
Regarding claim 6, Suwada teaches a package housing at least partially surrounding the semiconductor chip, wherein the package housing has a first opening configured to discharge the gaseous coolant from the cooling channel, and a second opening configured to supply the liquid coolant to the cooling channel (Fig. 2 points to a semiconductor package comprising an enclosure 22B (package housing), a coolant inflow port 26B (second opening), and a coolant outflow port 27B (first opening). [0026] further points to a coolant 19B, which changes to a gas phase (gaseous coolant) from a liquid phase (liquid coolant).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Mok et al. and Suwada, such that an enclosure/package housing with ports/openings is additionally formed in order to create a seal that allows for the liquid coolant to flow towards the semiconductor chip while also allowing the gaseous coolant to escape and be replaced.
Regarding claim 7, Suwada teaches a supply channel provided on an upper surface of the semiconductor chip and connecting the second opening to the cooling channel (Fig. 2 points to a coolant inflow port 26B (second opening) that communicates with an interior (cooling channel) of the enclosure 22B. Additionally, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the formation of a “supply channel” to be a result effective variable affecting the speed and/or direction of the overall flow path. Thus, it would have been obvious to modify the device of Suwada to have a supply channel connecting the second opening and the cooling channel in order to improve thermal management via better control of the coolant flow path. See MPEP 2144.05(II)(B) and 2143.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Mok et al. and Suwada, such that the second opening and the cooling channel are connected to each other in order to allow for liquid coolant to flow and provide heat dissipation to the semiconductor chip.
Regarding claim 8, Mok teaches wherein the supply channel comprises a third fine pattern on the upper surface of the semiconductor chip and configured to generate a capillary force that moves the liquid coolant ([0012] points to a heat pipe (supply channel) with a wick structure (third fine pattern) on the inside, such that a working fluid is transported by the capillary effect.).
Regarding claim 9, Suwada teaches a plurality of cooling channels, including the cooling channel, provided in the semiconductor chip, wherein a plurality of first openings respectively corresponding to the plurality of cooling channels are provided in the package housing (Fig. 2 points to enclosure 22B (package housing), channels 10B and 14B (a plurality of cooling channels) and coolant outflow ports 24B and 27B (a plurality of first openings).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Mok et al. and Suwada, such that a plurality of cooling channels and a plurality of first openings are formed in order to increase the flow of coolant by providing multiple outflow paths by which the gaseous coolant can escape and be replaced by liquid coolant.
Regarding claim 10, Suwada teaches a plurality of semiconductor chips stacked in a longitudinal direction and each including the cooling channel (Fig. 2 points to a stacked body 6B comprised of semiconductor elements 5B (semiconductor chips), which is positioned inside channel 14B (cooling channel).), wherein each of the plurality of semiconductor chips other than a lowest semiconductor chip of the plurality of semiconductor chips comprises a connection channel penetrating in the longitudinal direction (Id. points to the coolant flowing through a path(s) (connection channel) defined by solder balls 4B. [0023] further points to upper surface of the stacked body 6B is tightly fitted to the enclosure 21B.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Mok et al. and Suwada, such that a plurality of semiconductor chips, along with connection channels between each chip, are formed in the cooling channel in order to better manage the heat dissipation of additional components without obstructing the flow of coolant by creating additional paths between each component.
Regarding claim 11, Mok in combination with Suwada teaches wherein the connection channel comprises a wall surface comprising a second fine pattern extending in the longitudinal direction (Fig. 2 of Suwada points to the coolant flowing through a path(s) (connection channel) defined by solder balls 4B. [0010] of Mok points to the formation of wick structures (second fine pattern).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Mok et al. and Suwada, such that the connection channel further comprises a fine pattern such as a wick structure in order to allow for the flow of coolant via capillary action.
Regarding claim 12, Mok in combination with Suwada teaches an outer cooling channel between two adjacent semiconductor chips of the plurality of semiconductor chips (Fig. 2 of Suwada points to a stacked body 6B comprised of semiconductor elements 5B (semiconductor chips). It is considered obvious that one of ordinary skill in the art could form additional elements within the stacked body 6B, such as partitions, in order to further isolate each of the semiconductor elements 5B.), wherein a first fine pattern configured to generate a capillary force that moves the liquid coolant in a transverse direction is provided on at least a portion of a wall surface of the outer cooling channel in the transverse direction ([0010] of Mok points to the formation of wick structures (first fine pattern).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Mok et al. and Suwada, such that additional outer cooling channel(s) are formed in order to create additional flow paths that increase the flow of coolant and by extension improve heat dissipation.
Regarding claim 13, Mok in combination with Suwada teaches wherein the first fine pattern is provided on an upper surface of a lower semiconductor chip of two adjacent semiconductor chips of the plurality of semiconductor chips (Fig. 2 of Suwada points to a stacked body 6B comprised of semiconductor elements 5B (semiconductor chips), and a flow path between each element defined by solder balls 4B. [0010] of Mok points to the formation of wick structures (first fine pattern).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Mok et al. and Suwada, such that the wick structure/fine pattern is formed on an upper surface of a lower semiconductor chip of two adjacent semiconductor chips in order to enhance the flow path between said chips by allowing the coolant to flow via capillary action.
Regarding claim 15, Suwada teaches a package housing at least partially surrounding the semiconductor chip, wherein the package housing has a first opening configured to discharge the gaseous coolant from the cooling channel, and a second opening configured to supply the liquid coolant to the cooling channel (Fig. 2 points to a semiconductor package comprising an enclosure 22B (package housing), a coolant inflow port 26B (second opening), and a coolant outflow port 27B (first opening). [0026] further points to a coolant 19B, which changes to a gas phase (gaseous coolant) from a liquid phase (liquid coolant).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Mok et al. and Suwada, such that an enclosure/package housing with ports/openings is additionally formed in order to create a seal that allows for the liquid coolant to flow towards the semiconductor chip while also allowing the gaseous coolant to escape and be replaced.
Regarding claim 16, Mok in combination with Suwada teaches a supply channel provided on the upper surface of the substrate and connecting the second opening to the cooling channel (Fig. 2 of Suwada points to a coolant inflow port 26B (second opening) that communicates with an interior (cooling channel) of the enclosure 22B. Additionally, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the formation of a “supply channel” to be a result effective variable affecting the speed and/or direction of the overall flow path. Thus, it would have been obvious to modify the device of Suwada to have a supply channel connecting the second opening and the cooling channel in order to improve thermal management via better control of the coolant flow path. See MPEP 2144.05(II)(B) and 2143.), wherein the supply channel comprises a third fine pattern provided on the upper surface of the substrate and configured to generate a capillary force that moves the liquid coolant ([0010-11] of Mok points to the formation of a wick structure (third fine pattern) which transports a condensed working fluid (liquid coolant) via capillary action.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Mok et al. and Suwada, such that the second opening and the cooling channel are connected to each other in order to allow for liquid coolant to flow and provide heat dissipation to the semiconductor chip.
Regarding claim 17, Suwada teaches a plurality of cooling channels, including the cooling channel, provided in the semiconductor chip, wherein a plurality of first openings respectively corresponding to the plurality of cooling channels are provided in the package housing (Fig. 2 points to enclosure 22B (package housing), channels 10B and 14B (a plurality of cooling channels) and coolant outflow ports 24B and 27B (a plurality of first openings).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Mok et al. and Suwada, such that a plurality of cooling channels and a plurality of first openings are formed in order to increase the flow of coolant by providing multiple outflow paths by which the gaseous coolant can escape and be replaced by liquid coolant.
Regarding claim 18, Mok in combination with Suwada teaches a plurality of semiconductor chips stacked in the longitudinal direction (Fig. 2 points to a stacked body 6B comprised of semiconductor elements 5B (semiconductor chips), which is positioned inside channel 14B (cooling channel).), wherein each of the plurality of semiconductor chips other than a lowest semiconductor chip of the plurality of semiconductor chips comprises a connection channel penetrating in the longitudinal direction (Id. points to the coolant flowing through a path(s) (connection channel) defined by solder balls 4B. [0023] further points to upper surface of the stacked body 6B is tightly fitted to the enclosure 21B.), and wherein the second fine pattern is provided on at least a portion of a wall surface of the connection channel ([0010-11] of Mok points to the formation of a wick structure (second fine pattern).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Mok et al. and Suwada, such that a plurality of semiconductor chips, along with connection channels between each chip, are formed in the cooling channel in order to better manage the heat dissipation of additional components without obstructing the flow of coolant by creating additional paths between each component.
Regarding claim 19, Suwada teaches an outer cooling channel between two adjacent semiconductor chips of the plurality of semiconductor chips (Fig. 2 of Suwada points to a stacked body 6B comprised of semiconductor elements 5B (semiconductor chips). It is considered obvious that one of ordinary skill in the art could form additional elements within the stacked body 6B, such as partitions, in order to further isolate each of the semiconductor elements 5B.), wherein a fourth fine pattern is provided on at least a portion of a wall surface of the outer cooling channel in the transverse direction ([0010] of Mok points to the formation of wick structures (fourth fine pattern).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Mok et al. and Suwada, such that additional outer cooling channel(s) are formed in order to create additional flow paths that increase the flow of coolant and by extension improve heat dissipation.
Regarding claim 20, Mok in combination with Suwada teaches wherein the fourth fine pattern is provided on an upper surface of a lower semiconductor chip of two adjacent semiconductor chips of the plurality of semiconductor chips (Fig. 2 of Suwada points to a stacked body 6B comprised of semiconductor elements 5B (semiconductor chips), and a flow path between each element defined by solder balls 4B. [0010] of Mok points to the formation of wick structures (fourth fine pattern).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Mok et al. and Suwada, such that the wick structure/fine pattern is formed on an upper surface of a lower semiconductor chip of two adjacent semiconductor chips in order to enhance the flow path between said chips by allowing the coolant to flow via capillary action.
Response to Arguments
Applicant’s arguments, see Remarks, filed 01/22/2026, with respect to the rejection(s) of claim(s) 1 and 14 (and by extension any dependent claims) under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Mok in further view of Neal (PGPub No. 20200203256).
Applicant’s arguments, see Remarks, filed 01/22/2026, with respect to the rejection(s) of claim(s) 7 and 16 under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation(s) of the previously applied references.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST.
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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