DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-7 and 9-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Min et al. (PG Pub. No. US 2023/0122379 A1).
Regarding claim 1, Min teaches an integrated circuit structure, comprising:
a sub-fin structure (¶ 0030 & fig. 3: BP1) beneath a stack of nanowires (¶ 0030 & fig. 3: BP1 arranged under stack of sheet patterns NS1);
a dielectric channel cap (¶ 0099: 125) having an opening over the stack of nanowires (fig. 3: opening in 125 arranged over NS1);
a gate electrode (¶ 0052: 120) over and around the stack of nanowires (fig. 3: 120 arranged over and around each NS1);
a gate dielectric structure (¶ 0025: 130) between the gate electrode and the stack of nanowires (fig. 3: 130 arranged between 120 and stack of NS1);
a conductive tap (¶ 0025: 170) on the gate electrode and in the opening in the dielectric channel cap (fig. 3: 170 arranged on 120 and in opening of 125); and
a dielectric layer (¶ 0087: 145) on the gate electrode and laterally adjacent to the conductive tap (fig. 3: 145 arranged on 120 and laterally adjacent to 170).
Regarding claim 2, Min teaches the integrated circuit structure of claim 1, wherein the conductive tap is in direct contact with the dielectric channel cap (fig. 3: 170 in direct contact with 125).
Regarding claim 4, Min teaches the integrated circuit structure of claim 1, wherein the sub-fin structure is a semiconductor sub-fin structure (¶ 0027: BP1 formed from substrate 100, which includes semiconductor material).
Regarding claim 5, Min teaches the integrated circuit structure of claim 1, wherein the sub-fin structure is an insulator sub-fin structure (¶ 0027: BP1 formed from substrate 100, which includes insulating material in at least one embodiment).
Regarding claim 6, Min teaches an integrated circuit structure, comprising:
a sub-fin structure (¶ 0030: BP1) beneath a fin (fig. 3: BP1 formed beneath fin of sheet patterns NS1);
a dielectric channel cap (¶ 0099: 125) having an opening over the fin (fig. 3: 125 includes an opening above NS1);
a gate electrode (¶ 0052: 120) over the fin (fig. 3: at least a portion of 120 disposed over NS1);
a gate dielectric structure (¶ 0052: 130) between the gate electrode and the fin (fig. 3: 130 arranged between 120 and NS1);
a conductive tap (¶ 0025: 170) on the gate electrode and in the opening in the dielectric channel cap (fig. 3: 170 arranged on 120 and in opening of 125); and
a dielectric layer (¶ 0087: 145) on the gate electrode and laterally adjacent to the conductive tap (fig. 3: 145 arranged on 120 and laterally adjacent to 170).
Regarding claim 7, Min teaches the integrated circuit structure of claim 6, wherein the conductive tap is in direct contact with the dielectric channel cap (fig. 3: 170 in direct contact with 125).
Regarding claim 9, Min teaches the integrated circuit structure of claim 6, wherein the sub-fin structure is a semiconductor sub-fin structure (¶ 0027: BP1 formed from substrate 100, which includes semiconductor material).
Regarding claim 10, Min teaches the integrated circuit structure of claim 6, wherein the sub-fin structure is an insulator sub-fin structure (¶ 0027: BP1 formed from substrate 100, which includes insulating material in at least one embodiment).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Min as applied to claims 1 and 6 above, and further in view of Guler et al. (PG Pub. No. US 2022/0093592 A1).
Regarding claims 3 and 8, Min teaches the integrated circuit structures of claims 1 and 6, comprising a gate dielectric structure (130) and a dielectric channel cap (125).
Min does not teach wherein a portion of the gate dielectric structure is on a top surface of the dielectric channel cap.
Guler teaches an integrated circuit structure (figs. 4H, 4J among others) including gate dielectric structure (¶ 0077: 428) disposed on a top surface of a dielectric channel cap (¶ 0071 & figs. 4D-4J: 428 disposed on a top surface of protective cap 408).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the integrate circuit structures of Min to include the gate dielectric structure on a top surface of the dielectric channel cap, as a means to protect a top surface of the channel, and/or reduce the number of etching steps for forming the gate structure, improving manufacturing efficiency.
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Min in view of Guler.
Regarding claim 11, Min teaches a device, comprising:
an integrated circuit structure (figs. 2-3 among others), comprising:
a sub-fin structure (¶ 0030 & fig. 3: BP1) beneath a stack of nanowires or a fin (¶ 0030 & fig. 3: BP1 arranged under fin-shaped stack of sheet patterns NS1);
a dielectric channel cap (¶ 0099: 125) having an opening over the stack of nanowires or the fin (fig. 3: opening in 125 arranged over NS1);
a gate electrode (¶ 0052: 120) over and around the stack of nanowires or the fin (fig. 3: 120 arranged over and around each NS1);
a gate dielectric structure (¶ 0025: 130) between the gate electrode and the stack of nanowires or the fin (fig. 3: 130 arranged between 120 and stack of NS1);
a conductive tap (¶ 0025: 170) on the gate electrode and in the opening in the dielectric channel cap (fig. 3: 170 arranged on 120 and in opening of 125); and
a dielectric layer (¶ 0087: 145) on the gate electrode and laterally adjacent to the conductive tap (fig. 3: 145 arranged on 120 and laterally adjacent to 170).
Min fails to teach the device comprises a computing device, comprising:
a board; and
a component coupled to the board, the component including the integrated circuit structure
Guler teaches a computing device (¶ 0019 & fig. 9: 900), comprising:
a board (¶ 0142: 902); and
a component (¶ 0145) coupled to the board (fig. 9: at least one component coupled to 902), the component including an integrated circuit structure (¶ 0147: component housed in 900 and at least indirectly coupled to 902 comprises an integrated circuit die).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the computing device of Guler with the integrated circuit structure of Min, as a means to provide an electronic device that processes data (Guler, ¶ 0148).
Since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 538, 416, 82 USPQ2d 1385, 1395 (2007); Sakraida v. AG Pro, Inc., 425 U.S. 273, 282, 189 USPQ 449, 453 (1976); Anderson' s-Black Rock, Inc. v. Pavement Salvage Co., 396 U.S. 57, 62-63, 163 USPQ 673, 675 (1969); Great Atlantic & P. Tea Co. v. Supermarket Equip. Corp., 340 U.S. 147, 152, 87 USPQ 303, 306 (1950). See MPEP § 2143.02. In the instant case, the integrated circuit structure of Min could have been combined with the computing device of Guler, with no change in their respective functions.
Regarding claim 12, Min in view of Guler teaches the computing device of claim 11, comprising the stack of nanowires (Min, ¶ 0030: NS1).
Regarding claim 13, Min in view of Guler teaches the computing device of claim 11, comprising the fin (Min, ¶ 0003, fig. 1: in at least one embodiment, BP1 comprises a fin shape).
Regarding claim 14, Min in view of Guler teaches the computing device of claim 11, further comprising:
a memory (Guler, ¶ 0143: DRAM) coupled to the board (Guler, fig. 9: DRAM coupled to 902).
Regarding claim 15, Min in view of Guler teaches the computing device of claim 11, further comprising:
a communication chip (Guler, ¶ 0143: 146) coupled to the board (Guler, fig. 9: 146 coupled to 902).
Regarding claim 16, Min in view of Guler teaches the computing device of claim 11, further comprising:
a battery (Guler, ¶ 0143: battery) coupled to the board (Guler, fig. 9: battery coupled to 902).
Regarding claim 17, Min in view of Guler teaches the computing device of claim 11, further comprising:
a camera coupled to the board (Guler, ¶ 0143: camera coupled to 902).
Regarding claim 18, Min in view of Guler teaches the computing device of claim 11, further comprising:
a display (Guler, ¶ 0143: touchscreen display) coupled to the board (Guler, fig. 9: touchscreen display coupled to 902).
Regarding claim 19, Min in view of Guler teaches the computing device of claim 11, wherein the component is a packaged integrated circuit die (Guler, ¶ 0145).
Regarding claim 20, Min in view of Guler teaches the computing device of claim 11, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (Guler, ¶ 0145).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818
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