Prosecution Insights
Last updated: May 29, 2026
Application No. 18/203,258

FAULT DETECTION IN PARALLEL HARDWARE

Non-Final OA §103
Filed
May 30, 2023
Examiner
FEATHERSTONE, MARK D
Art Unit
2111
Tech Center
2100 — Computer Architecture & Software
Assignee
Nvidia Corporation
OA Round
5 (Non-Final)
59%
Grant Probability
Moderate
5-6
OA Rounds
1y 2m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 59% of resolved cases
59%
Career Allowance Rate
181 granted / 308 resolved
+3.8% vs TC avg
Strong +25% interview lift
Without
With
+24.8%
Interview Lift
resolved cases with interview
Typical timeline
4y 2m
Avg Prosecution
7 currently pending
Career history
316
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
87.3%
+47.3% vs TC avg
§102
6.8%
-33.2% vs TC avg
§112
2.4%
-37.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 308 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Detailed Action Response to the Applicant’s amendment filed on 04/15/2026. Claims 1-21 have been submitted for examination. Claims 1, 10, and 19 have been amended. Claim 21 is newly presented. Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/15/2026 has been entered. Response to Arguments Applicant’s arguments, filed on 10/06/2025, with respect to the rejections of claims 1-20 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: Determining the scope and contents of the prior art. Ascertaining the differences between the prior art and the claims at issue. Resolving the level of ordinary skill in the pertinent art. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-3, 5-7, 9-13, 15-19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Ashmore (US 2008/0201616) in view of Fan et al (CN 116193424) hereinafter Fan. In regard to claim 1, Ashmore teaches: A method comprising: causing one or more hardware components of a machine to perform one or more diagnostic tests of the one or mor hardware component in accordance with at least one diagnostic test pattern to generate at least one result value; and ( Section [0043] in Ashmore; a diagnostic test is performed for a RAID controller) using the at least one result value to determine one or more hardware faults associated with the one or more hardware components are present([0043], RAID controller detects a fault, corresponding to a hardware fault). Ashmore does not explicitly teach the hardware components include one or more graphics processing units (GPUs) and performing in parallel with performing one or more non-diagnostic operations associated with planning, navigation, or control of the machine, the diagnostic test. Fan teaches, the hardware components include one or more graphics processing units (GPUs) and performing in parallel with performing one or more non-diagnostic operations associated with planning, navigation, or control of the machine, the diagnostic test (page 21, the computing unit may be a GPU; page 2, automatic driving vehicle; page 3, diagnostic and non-diagnostic operations performed in parallel, diagnostic routing and non-diagnostic routing of communication; page 4, upgrading process through diagnostic communication; non-diagnostic communication to realize vehicle function). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Ashmore with the teaching of Fan of parallel diagnostic/non-diagnostic operation in order to improve the intelligence degree of the vehicle and to operate the vehicle while upgrading as taught by Fan on page 4). In regard to claim 2, Ashmore in view of Fan teaches: The method of claim 1, further comprising: causing one or more corrective operations to be performed in response to the one or more hardware faults being detected. ( Section [0043] in Ashmore ) In regard to claim 3, Ashmore in view of Fan teaches: The method of claim 1, further comprising: causing the one or more hardware components to generate the at least one result value based at least on providing the one or more hardware components with one or more input values associated with the at least one diagnostic test pattern. ( Section [0043] in Ashmore ) In regard to claim 5, Ashmore in view of Fan teaches: The method of claim 1, wherein the one or more hardware components are caused to generate the at least one result value in accordance with a diagnostic frequency. ( Section [0043] in Ashmore ) In regard to claim 6, Ashmore in view of Fan teaches: The method of claim 1, further comprising: algorithmically generating a portion of the at least one diagnostic test pattern based at least in part on a portion of the one or more hardware components, the portion of the at least one diagnostic test pattern to cause the portion of the one or more hardware components to execute one or more instructions in parallel. ( Section [0043] in Ashmore ) In regard to claim 7, Ashmore in view of Fan teaches: The method of claim 1, further comprising: providing an indication of the one or more hardware faults. ( Section [0043] in Ashmore ) In regard to claim 9, Ashmore in view of Fan teaches: The method of claim 1, further comprising: selecting the at least one diagnostic test pattern from a plurality of pre-existing diagnostic test patterns. (Section [0043] in Ashmore ) Claim 10 is rejected for the same reasons as claim 1. Claim 19 is rejected for the same reasons as per claim 1. Claims 11-13, 15-18 and 21 are rejected for the same reasons as per claims 2-3, 5-7, and 9. Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ashmore and further in view of Fan et al, (CN 116193424), hereinafter Fan, in view of Huang, (US 2023/0177000), hereinafter Huang. In regard to claim 4, Ashmore in view of Fan teaches the method of claim 1, however fails to teach/Huang teaches wherein the one or more hardware components comprise at least one tensor processor ( Sections [0026]] in Huang). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Ashmore in view of Fan of detecting hardware faults with the teaching of Huang of tensor processor as tensor operations are advantageous in reducing the time required to complete the operations in a parallel manner as described by Huang in the cited section. Claim 14 corresponds to claim 4 and is rejected accordingly. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ashmore and further in view of Fan et al, (CN 116193424), hereinafter Fan, in view of Jain, (US 2012/0030532), hereinafter Jain. In regard to claim 8, Ashmore in view of Fan teaches the method of claim 1, however fails to teach/Jain teaches wherein the at least one diagnostic test pattern is to test one or more of: a floating-point vector operation; an integer point vector operation; a matrix multiplication operation; a bit operation; a memory operation; a data path operation; an asynchronous data operation; a cache stride access operation; misaligned cache access; missed buffer access; an operation following a cache compression; or a transfer between the one or more hardware components and a host device. ( Figure 2 in Jain ) Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ashmore and further in view of Fan et al, (CN 116193424), hereinafter Fan, in view of Lyra et al (U.S. 2024/0166236), hereinafter Lyra. In regard to claim 20, Ashmore in view of Fan teaches the processor of claim 19, however fails to teach/Lyra teaches wherein the processor is comprised in at least one of: a control system for an autonomous or semi-autonomous machine; a perception system for an autonomous or semi-autonomous machine; a first system for performing simulation operations; a second system for performing deep learning operations; a third system implemented using an edge device; a fourth system implemented using a robot; a fifth system incorporating one or more virtual machines (VMs); a sixth system implemented at least partially in a data center; a seventh system for performing digital twin operations; an eighth system for performing light transport simulation; a nineth system for performing collaborative content creation for 3D assets; a tenth system for performing conversational Artificial Intelligence operations; an eleventh system for generating synthetic data; a twelfth system for implementing a web-hosted service for detecting program workload inefficiencies; an application as an application programming interface ("API"); a thirteenth system implemented at least partially using cloud computing resources; or a fourteenth system for presenting one or more of virtual reality content, augmented reality content, or mixed reality content ([0101], autonomous driving scenario in parallel with the GPU performing other tasks). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Ashmore in view of Fan that teaches GPU with the teaching of Lyra of using the GPU for autonomous driving to apply the parallel processing system for autonomous driving as described by Lyra in the cited section. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Featherstone whose telephone number is (571)270-3750. The examiner can normally be reached on M-F, 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached on 571-272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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Prosecution Timeline

Show 9 earlier events
Sep 11, 2025
Examiner Interview Summary
Oct 06, 2025
Response Filed
Jan 08, 2026
Final Rejection mailed — §103
Jan 30, 2026
Examiner Interview Summary
Mar 06, 2026
Response after Non-Final Action
Apr 15, 2026
Request for Continued Examination
Apr 24, 2026
Response after Non-Final Action
May 07, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
59%
Grant Probability
84%
With Interview (+24.8%)
4y 2m (~1y 2m remaining)
Median Time to Grant
High
PTA Risk
Based on 308 resolved cases by this examiner. Grant probability derived from career allowance rate.

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